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28#ifndef __RADEON_H__
29#define __RADEON_H__
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63#include <linux/atomic.h>
64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67#include <linux/interval_tree.h>
68#include <linux/hashtable.h>
69#include <linux/dma-fence.h>
70
71#include <drm/ttm/ttm_bo_api.h>
72#include <drm/ttm/ttm_bo_driver.h>
73#include <drm/ttm/ttm_placement.h>
74#include <drm/ttm/ttm_module.h>
75#include <drm/ttm/ttm_execbuf_util.h>
76
77#include <drm/drm_gem.h>
78
79#include "radeon_family.h"
80#include "radeon_mode.h"
81#include "radeon_reg.h"
82
83
84
85
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
94extern int radeon_testing;
95extern int radeon_connector_table;
96extern int radeon_tv;
97extern int radeon_audio;
98extern int radeon_disp_priority;
99extern int radeon_hw_i2c;
100extern int radeon_pcie_gen2;
101extern int radeon_msi;
102extern int radeon_lockup_timeout;
103extern int radeon_fastfb;
104extern int radeon_dpm;
105extern int radeon_aspm;
106extern int radeon_runtime_pm;
107extern int radeon_hard_reset;
108extern int radeon_vm_size;
109extern int radeon_vm_block_size;
110extern int radeon_deep_color;
111extern int radeon_use_pflipirq;
112extern int radeon_bapm;
113extern int radeon_backlight;
114extern int radeon_auxch;
115extern int radeon_mst;
116extern int radeon_uvd;
117extern int radeon_vce;
118extern int radeon_si_support;
119extern int radeon_cik_support;
120
121
122
123
124
125#define RADEON_MAX_USEC_TIMEOUT 100000
126#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
127#define RADEON_USEC_IB_TEST_TIMEOUT 1000000
128
129#define RADEON_IB_POOL_SIZE 16
130#define RADEON_DEBUGFS_MAX_COMPONENTS 32
131#define RADEONFB_CONN_LIMIT 4
132#define RADEON_BIOS_NUM_SCRATCH 8
133
134
135
136#define RADEON_RING_TYPE_GFX_INDEX 0
137
138
139#define CAYMAN_RING_TYPE_CP1_INDEX 1
140#define CAYMAN_RING_TYPE_CP2_INDEX 2
141
142
143#define R600_RING_TYPE_DMA_INDEX 3
144
145#define CAYMAN_RING_TYPE_DMA1_INDEX 4
146
147
148#define R600_RING_TYPE_UVD_INDEX 5
149
150
151#define TN_RING_TYPE_VCE1_INDEX 6
152#define TN_RING_TYPE_VCE2_INDEX 7
153
154
155#define RADEON_NUM_RINGS 8
156
157
158#define RADEON_NUM_SYNCS 4
159
160
161#define RADEON_VA_IB_OFFSET (1 << 20)
162#define RADEON_VA_RESERVED_SIZE (8 << 20)
163#define RADEON_IB_VM_MAX_SIZE (64 << 10)
164
165
166#define RADEON_ASIC_RESET_DATA 0x39d5e86b
167
168
169#define RADEON_RESET_GFX (1 << 0)
170#define RADEON_RESET_COMPUTE (1 << 1)
171#define RADEON_RESET_DMA (1 << 2)
172#define RADEON_RESET_CP (1 << 3)
173#define RADEON_RESET_GRBM (1 << 4)
174#define RADEON_RESET_DMA1 (1 << 5)
175#define RADEON_RESET_RLC (1 << 6)
176#define RADEON_RESET_SEM (1 << 7)
177#define RADEON_RESET_IH (1 << 8)
178#define RADEON_RESET_VMC (1 << 9)
179#define RADEON_RESET_MC (1 << 10)
180#define RADEON_RESET_DISPLAY (1 << 11)
181
182
183#define RADEON_CG_BLOCK_GFX (1 << 0)
184#define RADEON_CG_BLOCK_MC (1 << 1)
185#define RADEON_CG_BLOCK_SDMA (1 << 2)
186#define RADEON_CG_BLOCK_UVD (1 << 3)
187#define RADEON_CG_BLOCK_VCE (1 << 4)
188#define RADEON_CG_BLOCK_HDP (1 << 5)
189#define RADEON_CG_BLOCK_BIF (1 << 6)
190
191
192#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
193#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
194#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
195#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
196#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
197#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
198#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
199#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
200#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
201#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
202#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
203#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
204#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
205#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
206#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
207#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
208#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
209
210
211#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
212#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
213#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
214#define RADEON_PG_SUPPORT_UVD (1 << 3)
215#define RADEON_PG_SUPPORT_VCE (1 << 4)
216#define RADEON_PG_SUPPORT_CP (1 << 5)
217#define RADEON_PG_SUPPORT_GDS (1 << 6)
218#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
219#define RADEON_PG_SUPPORT_SDMA (1 << 8)
220#define RADEON_PG_SUPPORT_ACP (1 << 9)
221#define RADEON_PG_SUPPORT_SAMU (1 << 10)
222
223
224#define CURSOR_WIDTH 64
225#define CURSOR_HEIGHT 64
226
227#define CIK_CURSOR_WIDTH 128
228#define CIK_CURSOR_HEIGHT 128
229
230
231
232
233enum radeon_pll_errata {
234 CHIP_ERRATA_R300_CG = 0x00000001,
235 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
236 CHIP_ERRATA_PLL_DELAY = 0x00000004
237};
238
239
240struct radeon_device;
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246bool radeon_get_bios(struct radeon_device *rdev);
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251struct radeon_dummy_page {
252 uint64_t entry;
253 struct page *page;
254 dma_addr_t addr;
255};
256int radeon_dummy_page_init(struct radeon_device *rdev);
257void radeon_dummy_page_fini(struct radeon_device *rdev);
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263struct radeon_clock {
264 struct radeon_pll p1pll;
265 struct radeon_pll p2pll;
266 struct radeon_pll dcpll;
267 struct radeon_pll spll;
268 struct radeon_pll mpll;
269
270 uint32_t default_mclk;
271 uint32_t default_sclk;
272 uint32_t default_dispclk;
273 uint32_t current_dispclk;
274 uint32_t dp_extclk;
275 uint32_t max_pixel_clock;
276 uint32_t vco_freq;
277};
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281
282int radeon_pm_init(struct radeon_device *rdev);
283int radeon_pm_late_init(struct radeon_device *rdev);
284void radeon_pm_fini(struct radeon_device *rdev);
285void radeon_pm_compute_clocks(struct radeon_device *rdev);
286void radeon_pm_suspend(struct radeon_device *rdev);
287void radeon_pm_resume(struct radeon_device *rdev);
288void radeon_combios_get_power_modes(struct radeon_device *rdev);
289void radeon_atombios_get_power_modes(struct radeon_device *rdev);
290int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
291 u8 clock_type,
292 u32 clock,
293 bool strobe_mode,
294 struct atom_clock_dividers *dividers);
295int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
296 u32 clock,
297 bool strobe_mode,
298 struct atom_mpll_param *mpll_param);
299void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
300int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
301 u16 voltage_level, u8 voltage_type,
302 u32 *gpio_value, u32 *gpio_mask);
303void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
304 u32 eng_clock, u32 mem_clock);
305int radeon_atom_get_voltage_step(struct radeon_device *rdev,
306 u8 voltage_type, u16 *voltage_step);
307int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
308 u16 voltage_id, u16 *voltage);
309int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
310 u16 *voltage,
311 u16 leakage_idx);
312int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
313 u16 *leakage_id);
314int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
315 u16 *vddc, u16 *vddci,
316 u16 virtual_voltage_id,
317 u16 vbios_voltage_id);
318int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
319 u16 virtual_voltage_id,
320 u16 *voltage);
321int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
322 u8 voltage_type,
323 u16 nominal_voltage,
324 u16 *true_voltage);
325int radeon_atom_get_min_voltage(struct radeon_device *rdev,
326 u8 voltage_type, u16 *min_voltage);
327int radeon_atom_get_max_voltage(struct radeon_device *rdev,
328 u8 voltage_type, u16 *max_voltage);
329int radeon_atom_get_voltage_table(struct radeon_device *rdev,
330 u8 voltage_type, u8 voltage_mode,
331 struct atom_voltage_table *voltage_table);
332bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
333 u8 voltage_type, u8 voltage_mode);
334int radeon_atom_get_svi2_info(struct radeon_device *rdev,
335 u8 voltage_type,
336 u8 *svd_gpio_id, u8 *svc_gpio_id);
337void radeon_atom_update_memory_dll(struct radeon_device *rdev,
338 u32 mem_clock);
339void radeon_atom_set_ac_timing(struct radeon_device *rdev,
340 u32 mem_clock);
341int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
342 u8 module_index,
343 struct atom_mc_reg_table *reg_table);
344int radeon_atom_get_memory_info(struct radeon_device *rdev,
345 u8 module_index, struct atom_memory_info *mem_info);
346int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
347 bool gddr5, u8 module_index,
348 struct atom_memory_clock_range_table *mclk_range_table);
349int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
350 u16 voltage_id, u16 *voltage);
351void rs690_pm_info(struct radeon_device *rdev);
352extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
353 unsigned *bankh, unsigned *mtaspect,
354 unsigned *tile_split);
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358
359struct radeon_fence_driver {
360 struct radeon_device *rdev;
361 uint32_t scratch_reg;
362 uint64_t gpu_addr;
363 volatile uint32_t *cpu_addr;
364
365 uint64_t sync_seq[RADEON_NUM_RINGS];
366 atomic64_t last_seq;
367 bool initialized, delayed_irq;
368 struct delayed_work lockup_work;
369};
370
371struct radeon_fence {
372 struct dma_fence base;
373
374 struct radeon_device *rdev;
375 uint64_t seq;
376
377 unsigned ring;
378 bool is_vm_update;
379
380 wait_queue_entry_t fence_wake;
381};
382
383int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
384int radeon_fence_driver_init(struct radeon_device *rdev);
385void radeon_fence_driver_fini(struct radeon_device *rdev);
386void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
387int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
388void radeon_fence_process(struct radeon_device *rdev, int ring);
389bool radeon_fence_signaled(struct radeon_fence *fence);
390long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
391int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
392int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
393int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
394int radeon_fence_wait_any(struct radeon_device *rdev,
395 struct radeon_fence **fences,
396 bool intr);
397struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
398void radeon_fence_unref(struct radeon_fence **fence);
399unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
400bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
401void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
402static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
403 struct radeon_fence *b)
404{
405 if (!a) {
406 return b;
407 }
408
409 if (!b) {
410 return a;
411 }
412
413 BUG_ON(a->ring != b->ring);
414
415 if (a->seq > b->seq) {
416 return a;
417 } else {
418 return b;
419 }
420}
421
422static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
423 struct radeon_fence *b)
424{
425 if (!a) {
426 return false;
427 }
428
429 if (!b) {
430 return true;
431 }
432
433 BUG_ON(a->ring != b->ring);
434
435 return a->seq < b->seq;
436}
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439
440
441struct radeon_surface_reg {
442 struct radeon_bo *bo;
443};
444
445#define RADEON_GEM_MAX_SURFACES 8
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447
448
449
450struct radeon_mman {
451 struct ttm_bo_global_ref bo_global_ref;
452 struct drm_global_reference mem_global_ref;
453 struct ttm_bo_device bdev;
454 bool mem_global_referenced;
455 bool initialized;
456
457#if defined(CONFIG_DEBUG_FS)
458 struct dentry *vram;
459 struct dentry *gtt;
460#endif
461};
462
463struct radeon_bo_list {
464 struct radeon_bo *robj;
465 struct ttm_validate_buffer tv;
466 uint64_t gpu_offset;
467 unsigned preferred_domains;
468 unsigned allowed_domains;
469 uint32_t tiling_flags;
470};
471
472
473struct radeon_bo_va {
474
475 struct list_head bo_list;
476 uint32_t flags;
477 struct radeon_fence *last_pt_update;
478 unsigned ref_count;
479
480
481 struct interval_tree_node it;
482 struct list_head vm_status;
483
484
485 struct radeon_vm *vm;
486 struct radeon_bo *bo;
487};
488
489struct radeon_bo {
490
491 struct list_head list;
492
493 u32 initial_domain;
494 struct ttm_place placements[4];
495 struct ttm_placement placement;
496 struct ttm_buffer_object tbo;
497 struct ttm_bo_kmap_obj kmap;
498 u32 flags;
499 unsigned pin_count;
500 void *kptr;
501 u32 tiling_flags;
502 u32 pitch;
503 int surface_reg;
504 unsigned prime_shared_count;
505
506
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508 struct list_head va;
509
510 struct radeon_device *rdev;
511 struct drm_gem_object gem_base;
512
513 struct ttm_bo_kmap_obj dma_buf_vmap;
514 pid_t pid;
515
516 struct radeon_mn *mn;
517 struct list_head mn_list;
518};
519#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
520
521int radeon_gem_debugfs_init(struct radeon_device *rdev);
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546struct radeon_sa_manager {
547 wait_queue_head_t wq;
548 struct radeon_bo *bo;
549 struct list_head *hole;
550 struct list_head flist[RADEON_NUM_RINGS];
551 struct list_head olist;
552 unsigned size;
553 uint64_t gpu_addr;
554 void *cpu_ptr;
555 uint32_t domain;
556 uint32_t align;
557};
558
559struct radeon_sa_bo;
560
561
562struct radeon_sa_bo {
563 struct list_head olist;
564 struct list_head flist;
565 struct radeon_sa_manager *manager;
566 unsigned soffset;
567 unsigned eoffset;
568 struct radeon_fence *fence;
569};
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572
573
574struct radeon_gem {
575 struct mutex mutex;
576 struct list_head objects;
577};
578
579int radeon_gem_init(struct radeon_device *rdev);
580void radeon_gem_fini(struct radeon_device *rdev);
581int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
582 int alignment, int initial_domain,
583 u32 flags, bool kernel,
584 struct drm_gem_object **obj);
585
586int radeon_mode_dumb_create(struct drm_file *file_priv,
587 struct drm_device *dev,
588 struct drm_mode_create_dumb *args);
589int radeon_mode_dumb_mmap(struct drm_file *filp,
590 struct drm_device *dev,
591 uint32_t handle, uint64_t *offset_p);
592
593
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595
596struct radeon_semaphore {
597 struct radeon_sa_bo *sa_bo;
598 signed waiters;
599 uint64_t gpu_addr;
600};
601
602int radeon_semaphore_create(struct radeon_device *rdev,
603 struct radeon_semaphore **semaphore);
604bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
605 struct radeon_semaphore *semaphore);
606bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
607 struct radeon_semaphore *semaphore);
608void radeon_semaphore_free(struct radeon_device *rdev,
609 struct radeon_semaphore **semaphore,
610 struct radeon_fence *fence);
611
612
613
614
615struct radeon_sync {
616 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
617 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
618 struct radeon_fence *last_vm_update;
619};
620
621void radeon_sync_create(struct radeon_sync *sync);
622void radeon_sync_fence(struct radeon_sync *sync,
623 struct radeon_fence *fence);
624int radeon_sync_resv(struct radeon_device *rdev,
625 struct radeon_sync *sync,
626 struct reservation_object *resv,
627 bool shared);
628int radeon_sync_rings(struct radeon_device *rdev,
629 struct radeon_sync *sync,
630 int waiting_ring);
631void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
632 struct radeon_fence *fence);
633
634
635
636
637struct radeon_mc;
638
639#define RADEON_GPU_PAGE_SIZE 4096
640#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
641#define RADEON_GPU_PAGE_SHIFT 12
642#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
643
644#define RADEON_GART_PAGE_DUMMY 0
645#define RADEON_GART_PAGE_VALID (1 << 0)
646#define RADEON_GART_PAGE_READ (1 << 1)
647#define RADEON_GART_PAGE_WRITE (1 << 2)
648#define RADEON_GART_PAGE_SNOOP (1 << 3)
649
650struct radeon_gart {
651 dma_addr_t table_addr;
652 struct radeon_bo *robj;
653 void *ptr;
654 unsigned num_gpu_pages;
655 unsigned num_cpu_pages;
656 unsigned table_size;
657 struct page **pages;
658 uint64_t *pages_entry;
659 bool ready;
660};
661
662int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
663void radeon_gart_table_ram_free(struct radeon_device *rdev);
664int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
665void radeon_gart_table_vram_free(struct radeon_device *rdev);
666int radeon_gart_table_vram_pin(struct radeon_device *rdev);
667void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
668int radeon_gart_init(struct radeon_device *rdev);
669void radeon_gart_fini(struct radeon_device *rdev);
670void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
671 int pages);
672int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
673 int pages, struct page **pagelist,
674 dma_addr_t *dma_addr, uint32_t flags);
675
676
677
678
679
680struct radeon_mc {
681 resource_size_t aper_size;
682 resource_size_t aper_base;
683 resource_size_t agp_base;
684
685
686 u64 mc_vram_size;
687 u64 visible_vram_size;
688 u64 gtt_size;
689 u64 gtt_start;
690 u64 gtt_end;
691 u64 vram_start;
692 u64 vram_end;
693 unsigned vram_width;
694 u64 real_vram_size;
695 int vram_mtrr;
696 bool vram_is_ddr;
697 bool igp_sideport_enabled;
698 u64 gtt_base_align;
699 u64 mc_mask;
700};
701
702bool radeon_combios_sideport_present(struct radeon_device *rdev);
703bool radeon_atombios_sideport_present(struct radeon_device *rdev);
704
705
706
707
708struct radeon_scratch {
709 unsigned num_reg;
710 uint32_t reg_base;
711 bool free[32];
712 uint32_t reg[32];
713};
714
715int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
716void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
717
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719
720
721#define RADEON_MAX_DOORBELLS 1024
722
723struct radeon_doorbell {
724
725 resource_size_t base;
726 resource_size_t size;
727 u32 __iomem *ptr;
728 u32 num_doorbells;
729 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
730};
731
732int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
733void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
734
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738
739struct radeon_flip_work {
740 struct work_struct flip_work;
741 struct work_struct unpin_work;
742 struct radeon_device *rdev;
743 int crtc_id;
744 u32 target_vblank;
745 uint64_t base;
746 struct drm_pending_vblank_event *event;
747 struct radeon_bo *old_rbo;
748 struct dma_fence *fence;
749 bool async;
750};
751
752struct r500_irq_stat_regs {
753 u32 disp_int;
754 u32 hdmi0_status;
755};
756
757struct r600_irq_stat_regs {
758 u32 disp_int;
759 u32 disp_int_cont;
760 u32 disp_int_cont2;
761 u32 d1grph_int;
762 u32 d2grph_int;
763 u32 hdmi0_status;
764 u32 hdmi1_status;
765};
766
767struct evergreen_irq_stat_regs {
768 u32 disp_int[6];
769 u32 grph_int[6];
770 u32 afmt_status[6];
771};
772
773struct cik_irq_stat_regs {
774 u32 disp_int;
775 u32 disp_int_cont;
776 u32 disp_int_cont2;
777 u32 disp_int_cont3;
778 u32 disp_int_cont4;
779 u32 disp_int_cont5;
780 u32 disp_int_cont6;
781 u32 d1grph_int;
782 u32 d2grph_int;
783 u32 d3grph_int;
784 u32 d4grph_int;
785 u32 d5grph_int;
786 u32 d6grph_int;
787};
788
789union radeon_irq_stat_regs {
790 struct r500_irq_stat_regs r500;
791 struct r600_irq_stat_regs r600;
792 struct evergreen_irq_stat_regs evergreen;
793 struct cik_irq_stat_regs cik;
794};
795
796struct radeon_irq {
797 bool installed;
798 spinlock_t lock;
799 atomic_t ring_int[RADEON_NUM_RINGS];
800 bool crtc_vblank_int[RADEON_MAX_CRTCS];
801 atomic_t pflip[RADEON_MAX_CRTCS];
802 wait_queue_head_t vblank_queue;
803 bool hpd[RADEON_MAX_HPD_PINS];
804 bool afmt[RADEON_MAX_AFMT_BLOCKS];
805 union radeon_irq_stat_regs stat_regs;
806 bool dpm_thermal;
807};
808
809int radeon_irq_kms_init(struct radeon_device *rdev);
810void radeon_irq_kms_fini(struct radeon_device *rdev);
811void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
812bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
813void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
814void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
815void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
816void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
817void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
818void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
819void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
820
821
822
823
824
825struct radeon_ib {
826 struct radeon_sa_bo *sa_bo;
827 uint32_t length_dw;
828 uint64_t gpu_addr;
829 uint32_t *ptr;
830 int ring;
831 struct radeon_fence *fence;
832 struct radeon_vm *vm;
833 bool is_const_ib;
834 struct radeon_sync sync;
835};
836
837struct radeon_ring {
838 struct radeon_bo *ring_obj;
839 volatile uint32_t *ring;
840 unsigned rptr_offs;
841 unsigned rptr_save_reg;
842 u64 next_rptr_gpu_addr;
843 volatile u32 *next_rptr_cpu_addr;
844 unsigned wptr;
845 unsigned wptr_old;
846 unsigned ring_size;
847 unsigned ring_free_dw;
848 int count_dw;
849 atomic_t last_rptr;
850 atomic64_t last_activity;
851 uint64_t gpu_addr;
852 uint32_t align_mask;
853 uint32_t ptr_mask;
854 bool ready;
855 u32 nop;
856 u32 idx;
857 u64 last_semaphore_signal_addr;
858 u64 last_semaphore_wait_addr;
859
860 u32 me;
861 u32 pipe;
862 u32 queue;
863 struct radeon_bo *mqd_obj;
864 u32 doorbell_index;
865 unsigned wptr_offs;
866};
867
868struct radeon_mec {
869 struct radeon_bo *hpd_eop_obj;
870 u64 hpd_eop_gpu_addr;
871 u32 num_pipe;
872 u32 num_mec;
873 u32 num_queue;
874};
875
876
877
878
879
880
881#define RADEON_NUM_VM 16
882
883
884#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
885
886
887#define RADEON_VM_PTB_ALIGN_SIZE 32768
888#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
889#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
890
891#define R600_PTE_VALID (1 << 0)
892#define R600_PTE_SYSTEM (1 << 1)
893#define R600_PTE_SNOOPED (1 << 2)
894#define R600_PTE_READABLE (1 << 5)
895#define R600_PTE_WRITEABLE (1 << 6)
896
897
898#define R600_PTE_FRAG_4KB (0 << 7)
899#define R600_PTE_FRAG_64KB (4 << 7)
900#define R600_PTE_FRAG_256KB (6 << 7)
901
902
903#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
904 R600_PTE_SYSTEM | R600_PTE_VALID )
905
906struct radeon_vm_pt {
907 struct radeon_bo *bo;
908 uint64_t addr;
909};
910
911struct radeon_vm_id {
912 unsigned id;
913 uint64_t pd_gpu_addr;
914
915 struct radeon_fence *flushed_updates;
916
917 struct radeon_fence *last_id_use;
918};
919
920struct radeon_vm {
921 struct mutex mutex;
922
923 struct rb_root_cached va;
924
925
926 spinlock_t status_lock;
927
928
929 struct list_head invalidated;
930
931
932 struct list_head freed;
933
934
935 struct list_head cleared;
936
937
938 struct radeon_bo *page_directory;
939 unsigned max_pde_used;
940
941
942 struct radeon_vm_pt *page_tables;
943
944 struct radeon_bo_va *ib_bo_va;
945
946
947 struct radeon_vm_id ids[RADEON_NUM_RINGS];
948};
949
950struct radeon_vm_manager {
951 struct radeon_fence *active[RADEON_NUM_VM];
952 uint32_t max_pfn;
953
954 unsigned nvm;
955
956 u64 vram_base_offset;
957
958 bool enabled;
959
960 uint32_t saved_table_addr[RADEON_NUM_VM];
961};
962
963
964
965
966struct radeon_fpriv {
967 struct radeon_vm vm;
968};
969
970
971
972
973struct r600_ih {
974 struct radeon_bo *ring_obj;
975 volatile uint32_t *ring;
976 unsigned rptr;
977 unsigned ring_size;
978 uint64_t gpu_addr;
979 uint32_t ptr_mask;
980 atomic_t lock;
981 bool enabled;
982};
983
984
985
986
987#include "clearstate_defs.h"
988
989struct radeon_rlc {
990
991 struct radeon_bo *save_restore_obj;
992 uint64_t save_restore_gpu_addr;
993 volatile uint32_t *sr_ptr;
994 const u32 *reg_list;
995 u32 reg_list_size;
996
997 struct radeon_bo *clear_state_obj;
998 uint64_t clear_state_gpu_addr;
999 volatile uint32_t *cs_ptr;
1000 const struct cs_section_def *cs_data;
1001 u32 clear_state_size;
1002
1003 struct radeon_bo *cp_table_obj;
1004 uint64_t cp_table_gpu_addr;
1005 volatile uint32_t *cp_table_ptr;
1006 u32 cp_table_size;
1007};
1008
1009int radeon_ib_get(struct radeon_device *rdev, int ring,
1010 struct radeon_ib *ib, struct radeon_vm *vm,
1011 unsigned size);
1012void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
1013int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1014 struct radeon_ib *const_ib, bool hdp_flush);
1015int radeon_ib_pool_init(struct radeon_device *rdev);
1016void radeon_ib_pool_fini(struct radeon_device *rdev);
1017int radeon_ib_ring_tests(struct radeon_device *rdev);
1018
1019bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1020 struct radeon_ring *ring);
1021void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1022int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1023int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1024void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1025 bool hdp_flush);
1026void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1027 bool hdp_flush);
1028void radeon_ring_undo(struct radeon_ring *ring);
1029void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1030int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1031void radeon_ring_lockup_update(struct radeon_device *rdev,
1032 struct radeon_ring *ring);
1033bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1034unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1035 uint32_t **data);
1036int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1037 unsigned size, uint32_t *data);
1038int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1039 unsigned rptr_offs, u32 nop);
1040void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1041
1042
1043
1044void r600_dma_stop(struct radeon_device *rdev);
1045int r600_dma_resume(struct radeon_device *rdev);
1046void r600_dma_fini(struct radeon_device *rdev);
1047
1048void cayman_dma_stop(struct radeon_device *rdev);
1049int cayman_dma_resume(struct radeon_device *rdev);
1050void cayman_dma_fini(struct radeon_device *rdev);
1051
1052
1053
1054
1055struct radeon_cs_chunk {
1056 uint32_t length_dw;
1057 uint32_t *kdata;
1058 void __user *user_ptr;
1059};
1060
1061struct radeon_cs_parser {
1062 struct device *dev;
1063 struct radeon_device *rdev;
1064 struct drm_file *filp;
1065
1066 unsigned nchunks;
1067 struct radeon_cs_chunk *chunks;
1068 uint64_t *chunks_array;
1069
1070 unsigned idx;
1071
1072 unsigned nrelocs;
1073 struct radeon_bo_list *relocs;
1074 struct radeon_bo_list *vm_bos;
1075 struct list_head validated;
1076 unsigned dma_reloc_idx;
1077
1078 struct radeon_cs_chunk *chunk_ib;
1079 struct radeon_cs_chunk *chunk_relocs;
1080 struct radeon_cs_chunk *chunk_flags;
1081 struct radeon_cs_chunk *chunk_const_ib;
1082 struct radeon_ib ib;
1083 struct radeon_ib const_ib;
1084 void *track;
1085 unsigned family;
1086 int parser_error;
1087 u32 cs_flags;
1088 u32 ring;
1089 s32 priority;
1090 struct ww_acquire_ctx ticket;
1091};
1092
1093static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1094{
1095 struct radeon_cs_chunk *ibc = p->chunk_ib;
1096
1097 if (ibc->kdata)
1098 return ibc->kdata[idx];
1099 return p->ib.ptr[idx];
1100}
1101
1102
1103struct radeon_cs_packet {
1104 unsigned idx;
1105 unsigned type;
1106 unsigned reg;
1107 unsigned opcode;
1108 int count;
1109 unsigned one_reg_wr;
1110};
1111
1112typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1113 struct radeon_cs_packet *pkt,
1114 unsigned idx, unsigned reg);
1115typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1116 struct radeon_cs_packet *pkt);
1117
1118
1119
1120
1121
1122int radeon_agp_init(struct radeon_device *rdev);
1123void radeon_agp_resume(struct radeon_device *rdev);
1124void radeon_agp_suspend(struct radeon_device *rdev);
1125void radeon_agp_fini(struct radeon_device *rdev);
1126
1127
1128
1129
1130
1131struct radeon_wb {
1132 struct radeon_bo *wb_obj;
1133 volatile uint32_t *wb;
1134 uint64_t gpu_addr;
1135 bool enabled;
1136 bool use_event;
1137};
1138
1139#define RADEON_WB_SCRATCH_OFFSET 0
1140#define RADEON_WB_RING0_NEXT_RPTR 256
1141#define RADEON_WB_CP_RPTR_OFFSET 1024
1142#define RADEON_WB_CP1_RPTR_OFFSET 1280
1143#define RADEON_WB_CP2_RPTR_OFFSET 1536
1144#define R600_WB_DMA_RPTR_OFFSET 1792
1145#define R600_WB_IH_WPTR_OFFSET 2048
1146#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1147#define R600_WB_EVENT_OFFSET 3072
1148#define CIK_WB_CP1_WPTR_OFFSET 3328
1149#define CIK_WB_CP2_WPTR_OFFSET 3584
1150#define R600_WB_DMA_RING_TEST_OFFSET 3588
1151#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173enum radeon_pm_method {
1174 PM_METHOD_PROFILE,
1175 PM_METHOD_DYNPM,
1176 PM_METHOD_DPM,
1177};
1178
1179enum radeon_dynpm_state {
1180 DYNPM_STATE_DISABLED,
1181 DYNPM_STATE_MINIMUM,
1182 DYNPM_STATE_PAUSED,
1183 DYNPM_STATE_ACTIVE,
1184 DYNPM_STATE_SUSPENDED,
1185};
1186enum radeon_dynpm_action {
1187 DYNPM_ACTION_NONE,
1188 DYNPM_ACTION_MINIMUM,
1189 DYNPM_ACTION_DOWNCLOCK,
1190 DYNPM_ACTION_UPCLOCK,
1191 DYNPM_ACTION_DEFAULT
1192};
1193
1194enum radeon_voltage_type {
1195 VOLTAGE_NONE = 0,
1196 VOLTAGE_GPIO,
1197 VOLTAGE_VDDC,
1198 VOLTAGE_SW
1199};
1200
1201enum radeon_pm_state_type {
1202
1203 POWER_STATE_TYPE_DEFAULT,
1204 POWER_STATE_TYPE_POWERSAVE,
1205
1206 POWER_STATE_TYPE_BATTERY,
1207 POWER_STATE_TYPE_BALANCED,
1208 POWER_STATE_TYPE_PERFORMANCE,
1209
1210 POWER_STATE_TYPE_INTERNAL_UVD,
1211 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1212 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1213 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1214 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1215 POWER_STATE_TYPE_INTERNAL_BOOT,
1216 POWER_STATE_TYPE_INTERNAL_THERMAL,
1217 POWER_STATE_TYPE_INTERNAL_ACPI,
1218 POWER_STATE_TYPE_INTERNAL_ULV,
1219 POWER_STATE_TYPE_INTERNAL_3DPERF,
1220};
1221
1222enum radeon_pm_profile_type {
1223 PM_PROFILE_DEFAULT,
1224 PM_PROFILE_AUTO,
1225 PM_PROFILE_LOW,
1226 PM_PROFILE_MID,
1227 PM_PROFILE_HIGH,
1228};
1229
1230#define PM_PROFILE_DEFAULT_IDX 0
1231#define PM_PROFILE_LOW_SH_IDX 1
1232#define PM_PROFILE_MID_SH_IDX 2
1233#define PM_PROFILE_HIGH_SH_IDX 3
1234#define PM_PROFILE_LOW_MH_IDX 4
1235#define PM_PROFILE_MID_MH_IDX 5
1236#define PM_PROFILE_HIGH_MH_IDX 6
1237#define PM_PROFILE_MAX 7
1238
1239struct radeon_pm_profile {
1240 int dpms_off_ps_idx;
1241 int dpms_on_ps_idx;
1242 int dpms_off_cm_idx;
1243 int dpms_on_cm_idx;
1244};
1245
1246enum radeon_int_thermal_type {
1247 THERMAL_TYPE_NONE,
1248 THERMAL_TYPE_EXTERNAL,
1249 THERMAL_TYPE_EXTERNAL_GPIO,
1250 THERMAL_TYPE_RV6XX,
1251 THERMAL_TYPE_RV770,
1252 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1253 THERMAL_TYPE_EVERGREEN,
1254 THERMAL_TYPE_SUMO,
1255 THERMAL_TYPE_NI,
1256 THERMAL_TYPE_SI,
1257 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1258 THERMAL_TYPE_CI,
1259 THERMAL_TYPE_KV,
1260};
1261
1262struct radeon_voltage {
1263 enum radeon_voltage_type type;
1264
1265 struct radeon_gpio_rec gpio;
1266 u32 delay;
1267 bool active_high;
1268
1269 u8 vddc_id;
1270 u8 vddci_id;
1271 bool vddci_enabled;
1272
1273 u16 voltage;
1274
1275 u16 vddci;
1276};
1277
1278
1279#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1280
1281struct radeon_pm_clock_info {
1282
1283 u32 mclk;
1284
1285 u32 sclk;
1286
1287 struct radeon_voltage voltage;
1288
1289 u32 flags;
1290};
1291
1292
1293#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1294
1295struct radeon_power_state {
1296 enum radeon_pm_state_type type;
1297 struct radeon_pm_clock_info *clock_info;
1298
1299 int num_clock_modes;
1300 struct radeon_pm_clock_info *default_clock_mode;
1301
1302 u32 flags;
1303 u32 misc;
1304 u32 misc2;
1305 int pcie_lanes;
1306};
1307
1308
1309
1310
1311#define RADEON_MODE_OVERCLOCK_MARGIN 500
1312
1313enum radeon_dpm_auto_throttle_src {
1314 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1315 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1316};
1317
1318enum radeon_dpm_event_src {
1319 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1320 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1321 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1322 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1323 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1324};
1325
1326#define RADEON_MAX_VCE_LEVELS 6
1327
1328enum radeon_vce_level {
1329 RADEON_VCE_LEVEL_AC_ALL = 0,
1330 RADEON_VCE_LEVEL_DC_EE = 1,
1331 RADEON_VCE_LEVEL_DC_LL_LOW = 2,
1332 RADEON_VCE_LEVEL_DC_LL_HIGH = 3,
1333 RADEON_VCE_LEVEL_DC_GP_LOW = 4,
1334 RADEON_VCE_LEVEL_DC_GP_HIGH = 5,
1335};
1336
1337struct radeon_ps {
1338 u32 caps;
1339 u32 class;
1340 u32 class2;
1341
1342 u32 vclk;
1343 u32 dclk;
1344
1345 u32 evclk;
1346 u32 ecclk;
1347 bool vce_active;
1348 enum radeon_vce_level vce_level;
1349
1350 void *ps_priv;
1351};
1352
1353struct radeon_dpm_thermal {
1354
1355 struct work_struct work;
1356
1357 int min_temp;
1358
1359 int max_temp;
1360
1361 bool high_to_low;
1362};
1363
1364enum radeon_clk_action
1365{
1366 RADEON_SCLK_UP = 1,
1367 RADEON_SCLK_DOWN
1368};
1369
1370struct radeon_blacklist_clocks
1371{
1372 u32 sclk;
1373 u32 mclk;
1374 enum radeon_clk_action action;
1375};
1376
1377struct radeon_clock_and_voltage_limits {
1378 u32 sclk;
1379 u32 mclk;
1380 u16 vddc;
1381 u16 vddci;
1382};
1383
1384struct radeon_clock_array {
1385 u32 count;
1386 u32 *values;
1387};
1388
1389struct radeon_clock_voltage_dependency_entry {
1390 u32 clk;
1391 u16 v;
1392};
1393
1394struct radeon_clock_voltage_dependency_table {
1395 u32 count;
1396 struct radeon_clock_voltage_dependency_entry *entries;
1397};
1398
1399union radeon_cac_leakage_entry {
1400 struct {
1401 u16 vddc;
1402 u32 leakage;
1403 };
1404 struct {
1405 u16 vddc1;
1406 u16 vddc2;
1407 u16 vddc3;
1408 };
1409};
1410
1411struct radeon_cac_leakage_table {
1412 u32 count;
1413 union radeon_cac_leakage_entry *entries;
1414};
1415
1416struct radeon_phase_shedding_limits_entry {
1417 u16 voltage;
1418 u32 sclk;
1419 u32 mclk;
1420};
1421
1422struct radeon_phase_shedding_limits_table {
1423 u32 count;
1424 struct radeon_phase_shedding_limits_entry *entries;
1425};
1426
1427struct radeon_uvd_clock_voltage_dependency_entry {
1428 u32 vclk;
1429 u32 dclk;
1430 u16 v;
1431};
1432
1433struct radeon_uvd_clock_voltage_dependency_table {
1434 u8 count;
1435 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1436};
1437
1438struct radeon_vce_clock_voltage_dependency_entry {
1439 u32 ecclk;
1440 u32 evclk;
1441 u16 v;
1442};
1443
1444struct radeon_vce_clock_voltage_dependency_table {
1445 u8 count;
1446 struct radeon_vce_clock_voltage_dependency_entry *entries;
1447};
1448
1449struct radeon_ppm_table {
1450 u8 ppm_design;
1451 u16 cpu_core_number;
1452 u32 platform_tdp;
1453 u32 small_ac_platform_tdp;
1454 u32 platform_tdc;
1455 u32 small_ac_platform_tdc;
1456 u32 apu_tdp;
1457 u32 dgpu_tdp;
1458 u32 dgpu_ulv_power;
1459 u32 tj_max;
1460};
1461
1462struct radeon_cac_tdp_table {
1463 u16 tdp;
1464 u16 configurable_tdp;
1465 u16 tdc;
1466 u16 battery_power_limit;
1467 u16 small_power_limit;
1468 u16 low_cac_leakage;
1469 u16 high_cac_leakage;
1470 u16 maximum_power_delivery_limit;
1471};
1472
1473struct radeon_dpm_dynamic_state {
1474 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1475 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1476 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1477 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1478 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1479 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1480 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1481 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1482 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1483 struct radeon_clock_array valid_sclk_values;
1484 struct radeon_clock_array valid_mclk_values;
1485 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1486 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1487 u32 mclk_sclk_ratio;
1488 u32 sclk_mclk_delta;
1489 u16 vddc_vddci_delta;
1490 u16 min_vddc_for_pcie_gen2;
1491 struct radeon_cac_leakage_table cac_leakage_table;
1492 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1493 struct radeon_ppm_table *ppm_table;
1494 struct radeon_cac_tdp_table *cac_tdp_table;
1495};
1496
1497struct radeon_dpm_fan {
1498 u16 t_min;
1499 u16 t_med;
1500 u16 t_high;
1501 u16 pwm_min;
1502 u16 pwm_med;
1503 u16 pwm_high;
1504 u8 t_hyst;
1505 u32 cycle_delay;
1506 u16 t_max;
1507 u8 control_mode;
1508 u16 default_max_fan_pwm;
1509 u16 default_fan_output_sensitivity;
1510 u16 fan_output_sensitivity;
1511 bool ucode_fan_control;
1512};
1513
1514enum radeon_pcie_gen {
1515 RADEON_PCIE_GEN1 = 0,
1516 RADEON_PCIE_GEN2 = 1,
1517 RADEON_PCIE_GEN3 = 2,
1518 RADEON_PCIE_GEN_INVALID = 0xffff
1519};
1520
1521enum radeon_dpm_forced_level {
1522 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1523 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1524 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1525};
1526
1527struct radeon_vce_state {
1528
1529 u32 evclk;
1530 u32 ecclk;
1531
1532 u32 sclk;
1533 u32 mclk;
1534 u8 clk_idx;
1535 u8 pstate;
1536};
1537
1538struct radeon_dpm {
1539 struct radeon_ps *ps;
1540
1541 int num_ps;
1542
1543 struct radeon_ps *current_ps;
1544
1545 struct radeon_ps *requested_ps;
1546
1547 struct radeon_ps *boot_ps;
1548
1549 struct radeon_ps *uvd_ps;
1550
1551 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1552 enum radeon_vce_level vce_level;
1553 enum radeon_pm_state_type state;
1554 enum radeon_pm_state_type user_state;
1555 u32 platform_caps;
1556 u32 voltage_response_time;
1557 u32 backbias_response_time;
1558 void *priv;
1559 u32 new_active_crtcs;
1560 int new_active_crtc_count;
1561 u32 current_active_crtcs;
1562 int current_active_crtc_count;
1563 bool single_display;
1564 struct radeon_dpm_dynamic_state dyn_state;
1565 struct radeon_dpm_fan fan;
1566 u32 tdp_limit;
1567 u32 near_tdp_limit;
1568 u32 near_tdp_limit_adjusted;
1569 u32 sq_ramping_threshold;
1570 u32 cac_leakage;
1571 u16 tdp_od_limit;
1572 u32 tdp_adjustment;
1573 u16 load_line_slope;
1574 bool power_control;
1575 bool ac_power;
1576
1577 bool thermal_active;
1578 bool uvd_active;
1579 bool vce_active;
1580
1581 struct radeon_dpm_thermal thermal;
1582
1583 enum radeon_dpm_forced_level forced_level;
1584
1585 unsigned sd;
1586 unsigned hd;
1587};
1588
1589void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1590void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1591
1592struct radeon_pm {
1593 struct mutex mutex;
1594
1595 struct rw_semaphore mclk_lock;
1596 u32 active_crtcs;
1597 int active_crtc_count;
1598 int req_vblank;
1599 bool vblank_sync;
1600 fixed20_12 max_bandwidth;
1601 fixed20_12 igp_sideport_mclk;
1602 fixed20_12 igp_system_mclk;
1603 fixed20_12 igp_ht_link_clk;
1604 fixed20_12 igp_ht_link_width;
1605 fixed20_12 k8_bandwidth;
1606 fixed20_12 sideport_bandwidth;
1607 fixed20_12 ht_bandwidth;
1608 fixed20_12 core_bandwidth;
1609 fixed20_12 sclk;
1610 fixed20_12 mclk;
1611 fixed20_12 needed_bandwidth;
1612 struct radeon_power_state *power_state;
1613
1614 int num_power_states;
1615 int current_power_state_index;
1616 int current_clock_mode_index;
1617 int requested_power_state_index;
1618 int requested_clock_mode_index;
1619 int default_power_state_index;
1620 u32 current_sclk;
1621 u32 current_mclk;
1622 u16 current_vddc;
1623 u16 current_vddci;
1624 u32 default_sclk;
1625 u32 default_mclk;
1626 u16 default_vddc;
1627 u16 default_vddci;
1628 struct radeon_i2c_chan *i2c_bus;
1629
1630 enum radeon_pm_method pm_method;
1631
1632 struct delayed_work dynpm_idle_work;
1633 enum radeon_dynpm_state dynpm_state;
1634 enum radeon_dynpm_action dynpm_planned_action;
1635 unsigned long dynpm_action_timeout;
1636 bool dynpm_can_upclock;
1637 bool dynpm_can_downclock;
1638
1639 enum radeon_pm_profile_type profile;
1640 int profile_index;
1641 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1642
1643 enum radeon_int_thermal_type int_thermal_type;
1644 struct device *int_hwmon_dev;
1645
1646 bool no_fan;
1647 u8 fan_pulses_per_revolution;
1648 u8 fan_min_rpm;
1649 u8 fan_max_rpm;
1650
1651 bool dpm_enabled;
1652 bool sysfs_initialized;
1653 struct radeon_dpm dpm;
1654};
1655
1656int radeon_pm_get_type_index(struct radeon_device *rdev,
1657 enum radeon_pm_state_type ps_type,
1658 int instance);
1659
1660
1661
1662#define RADEON_DEFAULT_UVD_HANDLES 10
1663#define RADEON_MAX_UVD_HANDLES 30
1664#define RADEON_UVD_STACK_SIZE (200*1024)
1665#define RADEON_UVD_HEAP_SIZE (256*1024)
1666#define RADEON_UVD_SESSION_SIZE (50*1024)
1667
1668struct radeon_uvd {
1669 bool fw_header_present;
1670 struct radeon_bo *vcpu_bo;
1671 void *cpu_addr;
1672 uint64_t gpu_addr;
1673 unsigned max_handles;
1674 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1675 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1676 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1677 struct delayed_work idle_work;
1678};
1679
1680int radeon_uvd_init(struct radeon_device *rdev);
1681void radeon_uvd_fini(struct radeon_device *rdev);
1682int radeon_uvd_suspend(struct radeon_device *rdev);
1683int radeon_uvd_resume(struct radeon_device *rdev);
1684int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1685 uint32_t handle, struct radeon_fence **fence);
1686int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1687 uint32_t handle, struct radeon_fence **fence);
1688void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1689 uint32_t allowed_domains);
1690void radeon_uvd_free_handles(struct radeon_device *rdev,
1691 struct drm_file *filp);
1692int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1693void radeon_uvd_note_usage(struct radeon_device *rdev);
1694int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1695 unsigned vclk, unsigned dclk,
1696 unsigned vco_min, unsigned vco_max,
1697 unsigned fb_factor, unsigned fb_mask,
1698 unsigned pd_min, unsigned pd_max,
1699 unsigned pd_even,
1700 unsigned *optimal_fb_div,
1701 unsigned *optimal_vclk_div,
1702 unsigned *optimal_dclk_div);
1703int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1704 unsigned cg_upll_func_cntl);
1705
1706
1707
1708
1709#define RADEON_MAX_VCE_HANDLES 16
1710
1711struct radeon_vce {
1712 struct radeon_bo *vcpu_bo;
1713 uint64_t gpu_addr;
1714 unsigned fw_version;
1715 unsigned fb_version;
1716 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1717 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1718 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1719 struct delayed_work idle_work;
1720 uint32_t keyselect;
1721};
1722
1723int radeon_vce_init(struct radeon_device *rdev);
1724void radeon_vce_fini(struct radeon_device *rdev);
1725int radeon_vce_suspend(struct radeon_device *rdev);
1726int radeon_vce_resume(struct radeon_device *rdev);
1727int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1728 uint32_t handle, struct radeon_fence **fence);
1729int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1730 uint32_t handle, struct radeon_fence **fence);
1731void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1732void radeon_vce_note_usage(struct radeon_device *rdev);
1733int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1734int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1735bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1736 struct radeon_ring *ring,
1737 struct radeon_semaphore *semaphore,
1738 bool emit_wait);
1739void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1740void radeon_vce_fence_emit(struct radeon_device *rdev,
1741 struct radeon_fence *fence);
1742int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1743int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1744
1745struct r600_audio_pin {
1746 int channels;
1747 int rate;
1748 int bits_per_sample;
1749 u8 status_bits;
1750 u8 category_code;
1751 u32 offset;
1752 bool connected;
1753 u32 id;
1754};
1755
1756struct r600_audio {
1757 bool enabled;
1758 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1759 int num_pins;
1760 struct radeon_audio_funcs *hdmi_funcs;
1761 struct radeon_audio_funcs *dp_funcs;
1762 struct radeon_audio_basic_funcs *funcs;
1763};
1764
1765
1766
1767
1768void radeon_benchmark(struct radeon_device *rdev, int test_number);
1769
1770
1771
1772
1773
1774void radeon_test_moves(struct radeon_device *rdev);
1775void radeon_test_ring_sync(struct radeon_device *rdev,
1776 struct radeon_ring *cpA,
1777 struct radeon_ring *cpB);
1778void radeon_test_syncing(struct radeon_device *rdev);
1779
1780
1781
1782
1783#if defined(CONFIG_MMU_NOTIFIER)
1784int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1785void radeon_mn_unregister(struct radeon_bo *bo);
1786#else
1787static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1788{
1789 return -ENODEV;
1790}
1791static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1792#endif
1793
1794
1795
1796
1797struct radeon_debugfs {
1798 struct drm_info_list *files;
1799 unsigned num_files;
1800};
1801
1802int radeon_debugfs_add_files(struct radeon_device *rdev,
1803 struct drm_info_list *files,
1804 unsigned nfiles);
1805int radeon_debugfs_fence_init(struct radeon_device *rdev);
1806
1807
1808
1809
1810struct radeon_asic_ring {
1811
1812 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1813 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1814 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1815
1816
1817 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1818 int (*cs_parse)(struct radeon_cs_parser *p);
1819
1820
1821 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1822 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1823 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1824 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1825 struct radeon_semaphore *semaphore, bool emit_wait);
1826 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1827 unsigned vm_id, uint64_t pd_addr);
1828
1829
1830 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1831 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1832 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1833
1834
1835 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1836};
1837
1838
1839
1840
1841struct radeon_asic {
1842 int (*init)(struct radeon_device *rdev);
1843 void (*fini)(struct radeon_device *rdev);
1844 int (*resume)(struct radeon_device *rdev);
1845 int (*suspend)(struct radeon_device *rdev);
1846 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1847 int (*asic_reset)(struct radeon_device *rdev, bool hard);
1848
1849 void (*mmio_hdp_flush)(struct radeon_device *rdev);
1850
1851 bool (*gui_idle)(struct radeon_device *rdev);
1852
1853 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1854
1855 u32 (*get_xclk)(struct radeon_device *rdev);
1856
1857 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1858
1859 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
1860
1861 struct {
1862 void (*tlb_flush)(struct radeon_device *rdev);
1863 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
1864 void (*set_page)(struct radeon_device *rdev, unsigned i,
1865 uint64_t entry);
1866 } gart;
1867 struct {
1868 int (*init)(struct radeon_device *rdev);
1869 void (*fini)(struct radeon_device *rdev);
1870 void (*copy_pages)(struct radeon_device *rdev,
1871 struct radeon_ib *ib,
1872 uint64_t pe, uint64_t src,
1873 unsigned count);
1874 void (*write_pages)(struct radeon_device *rdev,
1875 struct radeon_ib *ib,
1876 uint64_t pe,
1877 uint64_t addr, unsigned count,
1878 uint32_t incr, uint32_t flags);
1879 void (*set_pages)(struct radeon_device *rdev,
1880 struct radeon_ib *ib,
1881 uint64_t pe,
1882 uint64_t addr, unsigned count,
1883 uint32_t incr, uint32_t flags);
1884 void (*pad_ib)(struct radeon_ib *ib);
1885 } vm;
1886
1887 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1888
1889 struct {
1890 int (*set)(struct radeon_device *rdev);
1891 int (*process)(struct radeon_device *rdev);
1892 } irq;
1893
1894 struct {
1895
1896 void (*bandwidth_update)(struct radeon_device *rdev);
1897
1898 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1899
1900 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1901
1902 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1903
1904 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1905
1906 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1907 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1908 } display;
1909
1910 struct {
1911 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1912 uint64_t src_offset,
1913 uint64_t dst_offset,
1914 unsigned num_gpu_pages,
1915 struct reservation_object *resv);
1916 u32 blit_ring_index;
1917 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1918 uint64_t src_offset,
1919 uint64_t dst_offset,
1920 unsigned num_gpu_pages,
1921 struct reservation_object *resv);
1922 u32 dma_ring_index;
1923
1924 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1925 uint64_t src_offset,
1926 uint64_t dst_offset,
1927 unsigned num_gpu_pages,
1928 struct reservation_object *resv);
1929
1930 u32 copy_ring_index;
1931 } copy;
1932
1933 struct {
1934 int (*set_reg)(struct radeon_device *rdev, int reg,
1935 uint32_t tiling_flags, uint32_t pitch,
1936 uint32_t offset, uint32_t obj_size);
1937 void (*clear_reg)(struct radeon_device *rdev, int reg);
1938 } surface;
1939
1940 struct {
1941 void (*init)(struct radeon_device *rdev);
1942 void (*fini)(struct radeon_device *rdev);
1943 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1944 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1945 } hpd;
1946
1947 struct {
1948 void (*misc)(struct radeon_device *rdev);
1949 void (*prepare)(struct radeon_device *rdev);
1950 void (*finish)(struct radeon_device *rdev);
1951 void (*init_profile)(struct radeon_device *rdev);
1952 void (*get_dynpm_state)(struct radeon_device *rdev);
1953 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1954 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1955 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1956 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1957 int (*get_pcie_lanes)(struct radeon_device *rdev);
1958 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1959 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1960 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1961 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1962 int (*get_temperature)(struct radeon_device *rdev);
1963 } pm;
1964
1965 struct {
1966 int (*init)(struct radeon_device *rdev);
1967 void (*setup_asic)(struct radeon_device *rdev);
1968 int (*enable)(struct radeon_device *rdev);
1969 int (*late_enable)(struct radeon_device *rdev);
1970 void (*disable)(struct radeon_device *rdev);
1971 int (*pre_set_power_state)(struct radeon_device *rdev);
1972 int (*set_power_state)(struct radeon_device *rdev);
1973 void (*post_set_power_state)(struct radeon_device *rdev);
1974 void (*display_configuration_changed)(struct radeon_device *rdev);
1975 void (*fini)(struct radeon_device *rdev);
1976 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1977 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1978 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1979 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1980 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1981 bool (*vblank_too_short)(struct radeon_device *rdev);
1982 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1983 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1984 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
1985 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
1986 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
1987 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
1988 u32 (*get_current_sclk)(struct radeon_device *rdev);
1989 u32 (*get_current_mclk)(struct radeon_device *rdev);
1990 } dpm;
1991
1992 struct {
1993 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
1994 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
1995 } pflip;
1996};
1997
1998
1999
2000
2001struct r100_asic {
2002 const unsigned *reg_safe_bm;
2003 unsigned reg_safe_bm_size;
2004 u32 hdp_cntl;
2005};
2006
2007struct r300_asic {
2008 const unsigned *reg_safe_bm;
2009 unsigned reg_safe_bm_size;
2010 u32 resync_scratch;
2011 u32 hdp_cntl;
2012};
2013
2014struct r600_asic {
2015 unsigned max_pipes;
2016 unsigned max_tile_pipes;
2017 unsigned max_simds;
2018 unsigned max_backends;
2019 unsigned max_gprs;
2020 unsigned max_threads;
2021 unsigned max_stack_entries;
2022 unsigned max_hw_contexts;
2023 unsigned max_gs_threads;
2024 unsigned sx_max_export_size;
2025 unsigned sx_max_export_pos_size;
2026 unsigned sx_max_export_smx_size;
2027 unsigned sq_num_cf_insts;
2028 unsigned tiling_nbanks;
2029 unsigned tiling_npipes;
2030 unsigned tiling_group_size;
2031 unsigned tile_config;
2032 unsigned backend_map;
2033 unsigned active_simds;
2034};
2035
2036struct rv770_asic {
2037 unsigned max_pipes;
2038 unsigned max_tile_pipes;
2039 unsigned max_simds;
2040 unsigned max_backends;
2041 unsigned max_gprs;
2042 unsigned max_threads;
2043 unsigned max_stack_entries;
2044 unsigned max_hw_contexts;
2045 unsigned max_gs_threads;
2046 unsigned sx_max_export_size;
2047 unsigned sx_max_export_pos_size;
2048 unsigned sx_max_export_smx_size;
2049 unsigned sq_num_cf_insts;
2050 unsigned sx_num_of_sets;
2051 unsigned sc_prim_fifo_size;
2052 unsigned sc_hiz_tile_fifo_size;
2053 unsigned sc_earlyz_tile_fifo_fize;
2054 unsigned tiling_nbanks;
2055 unsigned tiling_npipes;
2056 unsigned tiling_group_size;
2057 unsigned tile_config;
2058 unsigned backend_map;
2059 unsigned active_simds;
2060};
2061
2062struct evergreen_asic {
2063 unsigned num_ses;
2064 unsigned max_pipes;
2065 unsigned max_tile_pipes;
2066 unsigned max_simds;
2067 unsigned max_backends;
2068 unsigned max_gprs;
2069 unsigned max_threads;
2070 unsigned max_stack_entries;
2071 unsigned max_hw_contexts;
2072 unsigned max_gs_threads;
2073 unsigned sx_max_export_size;
2074 unsigned sx_max_export_pos_size;
2075 unsigned sx_max_export_smx_size;
2076 unsigned sq_num_cf_insts;
2077 unsigned sx_num_of_sets;
2078 unsigned sc_prim_fifo_size;
2079 unsigned sc_hiz_tile_fifo_size;
2080 unsigned sc_earlyz_tile_fifo_size;
2081 unsigned tiling_nbanks;
2082 unsigned tiling_npipes;
2083 unsigned tiling_group_size;
2084 unsigned tile_config;
2085 unsigned backend_map;
2086 unsigned active_simds;
2087};
2088
2089struct cayman_asic {
2090 unsigned max_shader_engines;
2091 unsigned max_pipes_per_simd;
2092 unsigned max_tile_pipes;
2093 unsigned max_simds_per_se;
2094 unsigned max_backends_per_se;
2095 unsigned max_texture_channel_caches;
2096 unsigned max_gprs;
2097 unsigned max_threads;
2098 unsigned max_gs_threads;
2099 unsigned max_stack_entries;
2100 unsigned sx_num_of_sets;
2101 unsigned sx_max_export_size;
2102 unsigned sx_max_export_pos_size;
2103 unsigned sx_max_export_smx_size;
2104 unsigned max_hw_contexts;
2105 unsigned sq_num_cf_insts;
2106 unsigned sc_prim_fifo_size;
2107 unsigned sc_hiz_tile_fifo_size;
2108 unsigned sc_earlyz_tile_fifo_size;
2109
2110 unsigned num_shader_engines;
2111 unsigned num_shader_pipes_per_simd;
2112 unsigned num_tile_pipes;
2113 unsigned num_simds_per_se;
2114 unsigned num_backends_per_se;
2115 unsigned backend_disable_mask_per_asic;
2116 unsigned backend_map;
2117 unsigned num_texture_channel_caches;
2118 unsigned mem_max_burst_length_bytes;
2119 unsigned mem_row_size_in_kb;
2120 unsigned shader_engine_tile_size;
2121 unsigned num_gpus;
2122 unsigned multi_gpu_tile_size;
2123
2124 unsigned tile_config;
2125 unsigned active_simds;
2126};
2127
2128struct si_asic {
2129 unsigned max_shader_engines;
2130 unsigned max_tile_pipes;
2131 unsigned max_cu_per_sh;
2132 unsigned max_sh_per_se;
2133 unsigned max_backends_per_se;
2134 unsigned max_texture_channel_caches;
2135 unsigned max_gprs;
2136 unsigned max_gs_threads;
2137 unsigned max_hw_contexts;
2138 unsigned sc_prim_fifo_size_frontend;
2139 unsigned sc_prim_fifo_size_backend;
2140 unsigned sc_hiz_tile_fifo_size;
2141 unsigned sc_earlyz_tile_fifo_size;
2142
2143 unsigned num_tile_pipes;
2144 unsigned backend_enable_mask;
2145 unsigned backend_disable_mask_per_asic;
2146 unsigned backend_map;
2147 unsigned num_texture_channel_caches;
2148 unsigned mem_max_burst_length_bytes;
2149 unsigned mem_row_size_in_kb;
2150 unsigned shader_engine_tile_size;
2151 unsigned num_gpus;
2152 unsigned multi_gpu_tile_size;
2153
2154 unsigned tile_config;
2155 uint32_t tile_mode_array[32];
2156 uint32_t active_cus;
2157};
2158
2159struct cik_asic {
2160 unsigned max_shader_engines;
2161 unsigned max_tile_pipes;
2162 unsigned max_cu_per_sh;
2163 unsigned max_sh_per_se;
2164 unsigned max_backends_per_se;
2165 unsigned max_texture_channel_caches;
2166 unsigned max_gprs;
2167 unsigned max_gs_threads;
2168 unsigned max_hw_contexts;
2169 unsigned sc_prim_fifo_size_frontend;
2170 unsigned sc_prim_fifo_size_backend;
2171 unsigned sc_hiz_tile_fifo_size;
2172 unsigned sc_earlyz_tile_fifo_size;
2173
2174 unsigned num_tile_pipes;
2175 unsigned backend_enable_mask;
2176 unsigned backend_disable_mask_per_asic;
2177 unsigned backend_map;
2178 unsigned num_texture_channel_caches;
2179 unsigned mem_max_burst_length_bytes;
2180 unsigned mem_row_size_in_kb;
2181 unsigned shader_engine_tile_size;
2182 unsigned num_gpus;
2183 unsigned multi_gpu_tile_size;
2184
2185 unsigned tile_config;
2186 uint32_t tile_mode_array[32];
2187 uint32_t macrotile_mode_array[16];
2188 uint32_t active_cus;
2189};
2190
2191union radeon_asic_config {
2192 struct r300_asic r300;
2193 struct r100_asic r100;
2194 struct r600_asic r600;
2195 struct rv770_asic rv770;
2196 struct evergreen_asic evergreen;
2197 struct cayman_asic cayman;
2198 struct si_asic si;
2199 struct cik_asic cik;
2200};
2201
2202
2203
2204
2205void radeon_agp_disable(struct radeon_device *rdev);
2206int radeon_asic_init(struct radeon_device *rdev);
2207
2208
2209
2210
2211
2212int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2213 struct drm_file *filp);
2214int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2215 struct drm_file *filp);
2216int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2217 struct drm_file *filp);
2218int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2219 struct drm_file *file_priv);
2220int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2221 struct drm_file *file_priv);
2222int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2223 struct drm_file *file_priv);
2224int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2225 struct drm_file *file_priv);
2226int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2227 struct drm_file *filp);
2228int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *filp);
2230int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *filp);
2232int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *filp);
2234int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *filp);
2236int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *filp);
2238int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2239int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2240 struct drm_file *filp);
2241int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2242 struct drm_file *filp);
2243
2244
2245struct r600_vram_scratch {
2246 struct radeon_bo *robj;
2247 volatile uint32_t *ptr;
2248 u64 gpu_addr;
2249};
2250
2251
2252
2253
2254struct radeon_atif_notification_cfg {
2255 bool enabled;
2256 int command_code;
2257};
2258
2259struct radeon_atif_notifications {
2260 bool display_switch;
2261 bool expansion_mode_change;
2262 bool thermal_state;
2263 bool forced_power_state;
2264 bool system_power_state;
2265 bool display_conf_change;
2266 bool px_gfx_switch;
2267 bool brightness_change;
2268 bool dgpu_display_event;
2269};
2270
2271struct radeon_atif_functions {
2272 bool system_params;
2273 bool sbios_requests;
2274 bool select_active_disp;
2275 bool lid_state;
2276 bool get_tv_standard;
2277 bool set_tv_standard;
2278 bool get_panel_expansion_mode;
2279 bool set_panel_expansion_mode;
2280 bool temperature_change;
2281 bool graphics_device_types;
2282};
2283
2284struct radeon_atif {
2285 struct radeon_atif_notifications notifications;
2286 struct radeon_atif_functions functions;
2287 struct radeon_atif_notification_cfg notification_cfg;
2288 struct radeon_encoder *encoder_for_bl;
2289};
2290
2291struct radeon_atcs_functions {
2292 bool get_ext_state;
2293 bool pcie_perf_req;
2294 bool pcie_dev_rdy;
2295 bool pcie_bus_width;
2296};
2297
2298struct radeon_atcs {
2299 struct radeon_atcs_functions functions;
2300};
2301
2302
2303
2304
2305typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2306typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2307
2308struct radeon_device {
2309 struct device *dev;
2310 struct drm_device *ddev;
2311 struct pci_dev *pdev;
2312 struct rw_semaphore exclusive_lock;
2313
2314 union radeon_asic_config config;
2315 enum radeon_family family;
2316 unsigned long flags;
2317 int usec_timeout;
2318 enum radeon_pll_errata pll_errata;
2319 int num_gb_pipes;
2320 int num_z_pipes;
2321 int disp_priority;
2322
2323 uint8_t *bios;
2324 bool is_atom_bios;
2325 uint16_t bios_header_start;
2326 struct radeon_bo *stolen_vga_memory;
2327
2328 resource_size_t rmmio_base;
2329 resource_size_t rmmio_size;
2330
2331 spinlock_t mmio_idx_lock;
2332
2333 spinlock_t smc_idx_lock;
2334
2335 spinlock_t pll_idx_lock;
2336
2337 spinlock_t mc_idx_lock;
2338
2339 spinlock_t pcie_idx_lock;
2340
2341 spinlock_t pciep_idx_lock;
2342
2343 spinlock_t pif_idx_lock;
2344
2345 spinlock_t cg_idx_lock;
2346
2347 spinlock_t uvd_idx_lock;
2348
2349 spinlock_t rcu_idx_lock;
2350
2351 spinlock_t didt_idx_lock;
2352
2353 spinlock_t end_idx_lock;
2354 void __iomem *rmmio;
2355 radeon_rreg_t mc_rreg;
2356 radeon_wreg_t mc_wreg;
2357 radeon_rreg_t pll_rreg;
2358 radeon_wreg_t pll_wreg;
2359 uint32_t pcie_reg_mask;
2360 radeon_rreg_t pciep_rreg;
2361 radeon_wreg_t pciep_wreg;
2362
2363 void __iomem *rio_mem;
2364 resource_size_t rio_mem_size;
2365 struct radeon_clock clock;
2366 struct radeon_mc mc;
2367 struct radeon_gart gart;
2368 struct radeon_mode_info mode_info;
2369 struct radeon_scratch scratch;
2370 struct radeon_doorbell doorbell;
2371 struct radeon_mman mman;
2372 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2373 wait_queue_head_t fence_queue;
2374 u64 fence_context;
2375 struct mutex ring_lock;
2376 struct radeon_ring ring[RADEON_NUM_RINGS];
2377 bool ib_pool_ready;
2378 struct radeon_sa_manager ring_tmp_bo;
2379 struct radeon_irq irq;
2380 struct radeon_asic *asic;
2381 struct radeon_gem gem;
2382 struct radeon_pm pm;
2383 struct radeon_uvd uvd;
2384 struct radeon_vce vce;
2385 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2386 struct radeon_wb wb;
2387 struct radeon_dummy_page dummy_page;
2388 bool shutdown;
2389 bool need_dma32;
2390 bool accel_working;
2391 bool fastfb_working;
2392 bool needs_reset, in_reset;
2393 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2394 const struct firmware *me_fw;
2395 const struct firmware *pfp_fw;
2396 const struct firmware *rlc_fw;
2397 const struct firmware *mc_fw;
2398 const struct firmware *ce_fw;
2399 const struct firmware *mec_fw;
2400 const struct firmware *mec2_fw;
2401 const struct firmware *sdma_fw;
2402 const struct firmware *smc_fw;
2403 const struct firmware *uvd_fw;
2404 const struct firmware *vce_fw;
2405 bool new_fw;
2406 struct r600_vram_scratch vram_scratch;
2407 int msi_enabled;
2408 struct r600_ih ih;
2409 struct radeon_rlc rlc;
2410 struct radeon_mec mec;
2411 struct delayed_work hotplug_work;
2412 struct work_struct dp_work;
2413 struct work_struct audio_work;
2414 int num_crtc;
2415 struct mutex dc_hw_i2c_mutex;
2416 bool has_uvd;
2417 bool has_vce;
2418 struct r600_audio audio;
2419 struct notifier_block acpi_nb;
2420
2421 struct drm_file *hyperz_filp;
2422 struct drm_file *cmask_filp;
2423
2424 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2425
2426 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2427 unsigned debugfs_count;
2428
2429 struct radeon_vm_manager vm_manager;
2430 struct mutex gpu_clock_mutex;
2431
2432 atomic64_t vram_usage;
2433 atomic64_t gtt_usage;
2434 atomic64_t num_bytes_moved;
2435 atomic_t gpu_reset_counter;
2436
2437 struct radeon_atif atif;
2438 struct radeon_atcs atcs;
2439
2440 struct mutex srbm_mutex;
2441
2442 u32 cg_flags;
2443 u32 pg_flags;
2444
2445 struct dev_pm_domain vga_pm_domain;
2446 bool have_disp_power_ref;
2447 u32 px_quirk_flags;
2448
2449
2450 u64 vram_pin_size;
2451 u64 gart_pin_size;
2452
2453 struct mutex mn_lock;
2454 DECLARE_HASHTABLE(mn_hash, 7);
2455};
2456
2457bool radeon_is_px(struct drm_device *dev);
2458int radeon_device_init(struct radeon_device *rdev,
2459 struct drm_device *ddev,
2460 struct pci_dev *pdev,
2461 uint32_t flags);
2462void radeon_device_fini(struct radeon_device *rdev);
2463int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2464
2465#define RADEON_MIN_MMIO_SIZE 0x10000
2466
2467uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2468void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2469static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2470 bool always_indirect)
2471{
2472
2473 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2474 return readl(((void __iomem *)rdev->rmmio) + reg);
2475 else
2476 return r100_mm_rreg_slow(rdev, reg);
2477}
2478static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2479 bool always_indirect)
2480{
2481 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2482 writel(v, ((void __iomem *)rdev->rmmio) + reg);
2483 else
2484 r100_mm_wreg_slow(rdev, reg, v);
2485}
2486
2487u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2488void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2489
2490u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2491void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2492
2493
2494
2495
2496extern const struct dma_fence_ops radeon_fence_ops;
2497
2498static inline struct radeon_fence *to_radeon_fence(struct dma_fence *f)
2499{
2500 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2501
2502 if (__f->base.ops == &radeon_fence_ops)
2503 return __f;
2504
2505 return NULL;
2506}
2507
2508
2509
2510
2511#define RREG8(reg) readb((rdev->rmmio) + (reg))
2512#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2513#define RREG16(reg) readw((rdev->rmmio) + (reg))
2514#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2515#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2516#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2517#define DREG32(reg) pr_info("REGISTER: " #reg " : 0x%08X\n", \
2518 r100_mm_rreg(rdev, (reg), false))
2519#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2520#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2521#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2522#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2523#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2524#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2525#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2526#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2527#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2528#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2529#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2530#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2531#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2532#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2533#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2534#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2535#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2536#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2537#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2538#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2539#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2540#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2541#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2542#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2543#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2544#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2545#define WREG32_P(reg, val, mask) \
2546 do { \
2547 uint32_t tmp_ = RREG32(reg); \
2548 tmp_ &= (mask); \
2549 tmp_ |= ((val) & ~(mask)); \
2550 WREG32(reg, tmp_); \
2551 } while (0)
2552#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2553#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2554#define WREG32_PLL_P(reg, val, mask) \
2555 do { \
2556 uint32_t tmp_ = RREG32_PLL(reg); \
2557 tmp_ &= (mask); \
2558 tmp_ |= ((val) & ~(mask)); \
2559 WREG32_PLL(reg, tmp_); \
2560 } while (0)
2561#define WREG32_SMC_P(reg, val, mask) \
2562 do { \
2563 uint32_t tmp_ = RREG32_SMC(reg); \
2564 tmp_ &= (mask); \
2565 tmp_ |= ((val) & ~(mask)); \
2566 WREG32_SMC(reg, tmp_); \
2567 } while (0)
2568#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2569#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2570#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2571
2572#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2573#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2584void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2585u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2586void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2587u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2588void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2589u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2590void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2591u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2592void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2593u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2594void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2595u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2596void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2597u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2598void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2599
2600void r100_pll_errata_after_index(struct radeon_device *rdev);
2601
2602
2603
2604
2605
2606#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2607 (rdev->pdev->device == 0x5969))
2608#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2609 (rdev->family == CHIP_RV200) || \
2610 (rdev->family == CHIP_RS100) || \
2611 (rdev->family == CHIP_RS200) || \
2612 (rdev->family == CHIP_RV250) || \
2613 (rdev->family == CHIP_RV280) || \
2614 (rdev->family == CHIP_RS300))
2615#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2616 (rdev->family == CHIP_RV350) || \
2617 (rdev->family == CHIP_R350) || \
2618 (rdev->family == CHIP_RV380) || \
2619 (rdev->family == CHIP_R420) || \
2620 (rdev->family == CHIP_R423) || \
2621 (rdev->family == CHIP_RV410) || \
2622 (rdev->family == CHIP_RS400) || \
2623 (rdev->family == CHIP_RS480))
2624#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2625 (rdev->ddev->pdev->device == 0x9443) || \
2626 (rdev->ddev->pdev->device == 0x944B) || \
2627 (rdev->ddev->pdev->device == 0x9506) || \
2628 (rdev->ddev->pdev->device == 0x9509) || \
2629 (rdev->ddev->pdev->device == 0x950F) || \
2630 (rdev->ddev->pdev->device == 0x689C) || \
2631 (rdev->ddev->pdev->device == 0x689D))
2632#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2633#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2634 (rdev->family == CHIP_RS690) || \
2635 (rdev->family == CHIP_RS740) || \
2636 (rdev->family >= CHIP_R600))
2637#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2638#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2639#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2640#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2641 (rdev->flags & RADEON_IS_IGP))
2642#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2643#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2644#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2645 (rdev->flags & RADEON_IS_IGP))
2646#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2647#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2648#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2649#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2650#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2651#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2652 (rdev->family == CHIP_MULLINS))
2653
2654#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2655 (rdev->ddev->pdev->device == 0x6850) || \
2656 (rdev->ddev->pdev->device == 0x6858) || \
2657 (rdev->ddev->pdev->device == 0x6859) || \
2658 (rdev->ddev->pdev->device == 0x6840) || \
2659 (rdev->ddev->pdev->device == 0x6841) || \
2660 (rdev->ddev->pdev->device == 0x6842) || \
2661 (rdev->ddev->pdev->device == 0x6843))
2662
2663
2664
2665
2666#define RBIOS8(i) (rdev->bios[i])
2667#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2668#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2669
2670int radeon_combios_init(struct radeon_device *rdev);
2671void radeon_combios_fini(struct radeon_device *rdev);
2672int radeon_atombios_init(struct radeon_device *rdev);
2673void radeon_atombios_fini(struct radeon_device *rdev);
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2689{
2690 if (ring->count_dw <= 0)
2691 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2692
2693 ring->ring[ring->wptr++] = v;
2694 ring->wptr &= ring->ptr_mask;
2695 ring->count_dw--;
2696 ring->ring_free_dw--;
2697}
2698
2699
2700
2701
2702#define radeon_init(rdev) (rdev)->asic->init((rdev))
2703#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2704#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2705#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2706#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2707#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2708#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
2709#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2710#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2711#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
2712#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2713#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2714#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2715#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2716#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2717#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
2718#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2719#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2720#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2721#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2722#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2723#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2724#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2725#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2726#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2727#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2728#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2729#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2730#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2731#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2732#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2733#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2734#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2735#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2736#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2737#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2738#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2739#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
2740#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2741#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2742#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2743#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2744#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2745#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2746#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2747#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2748#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2749#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2750#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2751#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2752#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2753#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2754#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2755#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2756#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2757#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2758#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2759#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2760#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2761#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2762#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2763#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2764#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2765#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2766#define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
2767#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
2768#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2769#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2770#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2771#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2772#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
2773#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2774#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2775#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2776#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2777#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2778#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2779#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2780#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2781#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2782#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2783#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2784#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2785#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2786#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2787#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2788#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2789#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2790#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2791#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2792#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
2793
2794
2795
2796extern int radeon_gpu_reset(struct radeon_device *rdev);
2797extern void radeon_pci_config_reset(struct radeon_device *rdev);
2798extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2799extern void radeon_agp_disable(struct radeon_device *rdev);
2800extern int radeon_modeset_init(struct radeon_device *rdev);
2801extern void radeon_modeset_fini(struct radeon_device *rdev);
2802extern bool radeon_card_posted(struct radeon_device *rdev);
2803extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2804extern void radeon_update_display_priority(struct radeon_device *rdev);
2805extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2806extern void radeon_scratch_init(struct radeon_device *rdev);
2807extern void radeon_wb_fini(struct radeon_device *rdev);
2808extern int radeon_wb_init(struct radeon_device *rdev);
2809extern void radeon_wb_disable(struct radeon_device *rdev);
2810extern void radeon_surface_init(struct radeon_device *rdev);
2811extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2812extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2813extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2814extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2815extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2816extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2817 uint32_t flags);
2818extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2819extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
2820extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2821extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2822extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2823extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2824 bool fbcon, bool freeze);
2825extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2826extern void radeon_program_register_sequence(struct radeon_device *rdev,
2827 const u32 *registers,
2828 const u32 array_size);
2829
2830
2831
2832
2833int radeon_vm_manager_init(struct radeon_device *rdev);
2834void radeon_vm_manager_fini(struct radeon_device *rdev);
2835int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2836void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2837struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2838 struct radeon_vm *vm,
2839 struct list_head *head);
2840struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2841 struct radeon_vm *vm, int ring);
2842void radeon_vm_flush(struct radeon_device *rdev,
2843 struct radeon_vm *vm,
2844 int ring, struct radeon_fence *fence);
2845void radeon_vm_fence(struct radeon_device *rdev,
2846 struct radeon_vm *vm,
2847 struct radeon_fence *fence);
2848uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2849int radeon_vm_update_page_directory(struct radeon_device *rdev,
2850 struct radeon_vm *vm);
2851int radeon_vm_clear_freed(struct radeon_device *rdev,
2852 struct radeon_vm *vm);
2853int radeon_vm_clear_invalids(struct radeon_device *rdev,
2854 struct radeon_vm *vm);
2855int radeon_vm_bo_update(struct radeon_device *rdev,
2856 struct radeon_bo_va *bo_va,
2857 struct ttm_mem_reg *mem);
2858void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2859 struct radeon_bo *bo);
2860struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2861 struct radeon_bo *bo);
2862struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2863 struct radeon_vm *vm,
2864 struct radeon_bo *bo);
2865int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2866 struct radeon_bo_va *bo_va,
2867 uint64_t offset,
2868 uint32_t flags);
2869void radeon_vm_bo_rmv(struct radeon_device *rdev,
2870 struct radeon_bo_va *bo_va);
2871
2872
2873void r600_audio_update_hdmi(struct work_struct *work);
2874struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2875struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2876void r600_audio_enable(struct radeon_device *rdev,
2877 struct r600_audio_pin *pin,
2878 u8 enable_mask);
2879void dce6_audio_enable(struct radeon_device *rdev,
2880 struct r600_audio_pin *pin,
2881 u8 enable_mask);
2882
2883
2884
2885
2886int r600_vram_scratch_init(struct radeon_device *rdev);
2887void r600_vram_scratch_fini(struct radeon_device *rdev);
2888
2889
2890
2891
2892unsigned r600_mip_minify(unsigned size, unsigned level);
2893bool r600_fmt_is_valid_color(u32 format);
2894bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2895int r600_fmt_get_blocksize(u32 format);
2896int r600_fmt_get_nblocksx(u32 format, u32 w);
2897int r600_fmt_get_nblocksy(u32 format, u32 h);
2898
2899
2900
2901
2902struct radeon_hdmi_acr {
2903 u32 clock;
2904
2905 int n_32khz;
2906 int cts_32khz;
2907
2908 int n_44_1khz;
2909 int cts_44_1khz;
2910
2911 int n_48khz;
2912 int cts_48khz;
2913
2914};
2915
2916extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2917
2918extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2919 u32 tiling_pipe_num,
2920 u32 max_rb_num,
2921 u32 total_max_rb_num,
2922 u32 enabled_rb_mask);
2923
2924
2925
2926
2927
2928extern int ni_init_microcode(struct radeon_device *rdev);
2929extern int ni_mc_load_microcode(struct radeon_device *rdev);
2930
2931
2932#if defined(CONFIG_ACPI)
2933extern int radeon_acpi_init(struct radeon_device *rdev);
2934extern void radeon_acpi_fini(struct radeon_device *rdev);
2935extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2936extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2937 u8 perf_req, bool advertise);
2938extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2939#else
2940static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2941static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2942#endif
2943
2944int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2945 struct radeon_cs_packet *pkt,
2946 unsigned idx);
2947bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2948void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2949 struct radeon_cs_packet *pkt);
2950int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2951 struct radeon_bo_list **cs_reloc,
2952 int nomm);
2953int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2954 uint32_t *vline_start_end,
2955 uint32_t *vline_status);
2956
2957
2958void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
2959 u32 reg, u32 mask,
2960 bool enable, const char *name,
2961 unsigned n);
2962
2963#include "radeon_object.h"
2964
2965#endif
2966