linux/drivers/gpu/drm/radeon/radeon_ttm.c
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   1/*
   2 * Copyright 2009 Jerome Glisse.
   3 * All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the
   7 * "Software"), to deal in the Software without restriction, including
   8 * without limitation the rights to use, copy, modify, merge, publish,
   9 * distribute, sub license, and/or sell copies of the Software, and to
  10 * permit persons to whom the Software is furnished to do so, subject to
  11 * the following conditions:
  12 *
  13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 *
  21 * The above copyright notice and this permission notice (including the
  22 * next paragraph) shall be included in all copies or substantial portions
  23 * of the Software.
  24 *
  25 */
  26/*
  27 * Authors:
  28 *    Jerome Glisse <glisse@freedesktop.org>
  29 *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30 *    Dave Airlie
  31 */
  32#include <drm/ttm/ttm_bo_api.h>
  33#include <drm/ttm/ttm_bo_driver.h>
  34#include <drm/ttm/ttm_placement.h>
  35#include <drm/ttm/ttm_module.h>
  36#include <drm/ttm/ttm_page_alloc.h>
  37#include <drm/drmP.h>
  38#include <drm/radeon_drm.h>
  39#include <linux/seq_file.h>
  40#include <linux/slab.h>
  41#include <linux/swiotlb.h>
  42#include <linux/swap.h>
  43#include <linux/pagemap.h>
  44#include <linux/debugfs.h>
  45#include "radeon_reg.h"
  46#include "radeon.h"
  47
  48#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  49
  50static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
  51static void radeon_ttm_debugfs_fini(struct radeon_device *rdev);
  52
  53static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
  54{
  55        struct radeon_mman *mman;
  56        struct radeon_device *rdev;
  57
  58        mman = container_of(bdev, struct radeon_mman, bdev);
  59        rdev = container_of(mman, struct radeon_device, mman);
  60        return rdev;
  61}
  62
  63
  64/*
  65 * Global memory.
  66 */
  67static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
  68{
  69        return ttm_mem_global_init(ref->object);
  70}
  71
  72static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
  73{
  74        ttm_mem_global_release(ref->object);
  75}
  76
  77static int radeon_ttm_global_init(struct radeon_device *rdev)
  78{
  79        struct drm_global_reference *global_ref;
  80        int r;
  81
  82        rdev->mman.mem_global_referenced = false;
  83        global_ref = &rdev->mman.mem_global_ref;
  84        global_ref->global_type = DRM_GLOBAL_TTM_MEM;
  85        global_ref->size = sizeof(struct ttm_mem_global);
  86        global_ref->init = &radeon_ttm_mem_global_init;
  87        global_ref->release = &radeon_ttm_mem_global_release;
  88        r = drm_global_item_ref(global_ref);
  89        if (r != 0) {
  90                DRM_ERROR("Failed setting up TTM memory accounting "
  91                          "subsystem.\n");
  92                return r;
  93        }
  94
  95        rdev->mman.bo_global_ref.mem_glob =
  96                rdev->mman.mem_global_ref.object;
  97        global_ref = &rdev->mman.bo_global_ref.ref;
  98        global_ref->global_type = DRM_GLOBAL_TTM_BO;
  99        global_ref->size = sizeof(struct ttm_bo_global);
 100        global_ref->init = &ttm_bo_global_init;
 101        global_ref->release = &ttm_bo_global_release;
 102        r = drm_global_item_ref(global_ref);
 103        if (r != 0) {
 104                DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 105                drm_global_item_unref(&rdev->mman.mem_global_ref);
 106                return r;
 107        }
 108
 109        rdev->mman.mem_global_referenced = true;
 110        return 0;
 111}
 112
 113static void radeon_ttm_global_fini(struct radeon_device *rdev)
 114{
 115        if (rdev->mman.mem_global_referenced) {
 116                drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
 117                drm_global_item_unref(&rdev->mman.mem_global_ref);
 118                rdev->mman.mem_global_referenced = false;
 119        }
 120}
 121
 122static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 123{
 124        return 0;
 125}
 126
 127static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 128                                struct ttm_mem_type_manager *man)
 129{
 130        struct radeon_device *rdev;
 131
 132        rdev = radeon_get_rdev(bdev);
 133
 134        switch (type) {
 135        case TTM_PL_SYSTEM:
 136                /* System memory */
 137                man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 138                man->available_caching = TTM_PL_MASK_CACHING;
 139                man->default_caching = TTM_PL_FLAG_CACHED;
 140                break;
 141        case TTM_PL_TT:
 142                man->func = &ttm_bo_manager_func;
 143                man->gpu_offset = rdev->mc.gtt_start;
 144                man->available_caching = TTM_PL_MASK_CACHING;
 145                man->default_caching = TTM_PL_FLAG_CACHED;
 146                man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 147#if IS_ENABLED(CONFIG_AGP)
 148                if (rdev->flags & RADEON_IS_AGP) {
 149                        if (!rdev->ddev->agp) {
 150                                DRM_ERROR("AGP is not enabled for memory type %u\n",
 151                                          (unsigned)type);
 152                                return -EINVAL;
 153                        }
 154                        if (!rdev->ddev->agp->cant_use_aperture)
 155                                man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 156                        man->available_caching = TTM_PL_FLAG_UNCACHED |
 157                                                 TTM_PL_FLAG_WC;
 158                        man->default_caching = TTM_PL_FLAG_WC;
 159                }
 160#endif
 161                break;
 162        case TTM_PL_VRAM:
 163                /* "On-card" video ram */
 164                man->func = &ttm_bo_manager_func;
 165                man->gpu_offset = rdev->mc.vram_start;
 166                man->flags = TTM_MEMTYPE_FLAG_FIXED |
 167                             TTM_MEMTYPE_FLAG_MAPPABLE;
 168                man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 169                man->default_caching = TTM_PL_FLAG_WC;
 170                break;
 171        default:
 172                DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 173                return -EINVAL;
 174        }
 175        return 0;
 176}
 177
 178static void radeon_evict_flags(struct ttm_buffer_object *bo,
 179                                struct ttm_placement *placement)
 180{
 181        static const struct ttm_place placements = {
 182                .fpfn = 0,
 183                .lpfn = 0,
 184                .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 185        };
 186
 187        struct radeon_bo *rbo;
 188
 189        if (!radeon_ttm_bo_is_radeon_bo(bo)) {
 190                placement->placement = &placements;
 191                placement->busy_placement = &placements;
 192                placement->num_placement = 1;
 193                placement->num_busy_placement = 1;
 194                return;
 195        }
 196        rbo = container_of(bo, struct radeon_bo, tbo);
 197        switch (bo->mem.mem_type) {
 198        case TTM_PL_VRAM:
 199                if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
 200                        radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 201                else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
 202                         bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
 203                        unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 204                        int i;
 205
 206                        /* Try evicting to the CPU inaccessible part of VRAM
 207                         * first, but only set GTT as busy placement, so this
 208                         * BO will be evicted to GTT rather than causing other
 209                         * BOs to be evicted from VRAM
 210                         */
 211                        radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
 212                                                         RADEON_GEM_DOMAIN_GTT);
 213                        rbo->placement.num_busy_placement = 0;
 214                        for (i = 0; i < rbo->placement.num_placement; i++) {
 215                                if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) {
 216                                        if (rbo->placements[i].fpfn < fpfn)
 217                                                rbo->placements[i].fpfn = fpfn;
 218                                } else {
 219                                        rbo->placement.busy_placement =
 220                                                &rbo->placements[i];
 221                                        rbo->placement.num_busy_placement = 1;
 222                                }
 223                        }
 224                } else
 225                        radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
 226                break;
 227        case TTM_PL_TT:
 228        default:
 229                radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
 230        }
 231        *placement = rbo->placement;
 232}
 233
 234static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 235{
 236        struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo);
 237
 238        if (radeon_ttm_tt_has_userptr(bo->ttm))
 239                return -EPERM;
 240        return drm_vma_node_verify_access(&rbo->gem_base.vma_node,
 241                                          filp->private_data);
 242}
 243
 244static void radeon_move_null(struct ttm_buffer_object *bo,
 245                             struct ttm_mem_reg *new_mem)
 246{
 247        struct ttm_mem_reg *old_mem = &bo->mem;
 248
 249        BUG_ON(old_mem->mm_node != NULL);
 250        *old_mem = *new_mem;
 251        new_mem->mm_node = NULL;
 252}
 253
 254static int radeon_move_blit(struct ttm_buffer_object *bo,
 255                        bool evict, bool no_wait_gpu,
 256                        struct ttm_mem_reg *new_mem,
 257                        struct ttm_mem_reg *old_mem)
 258{
 259        struct radeon_device *rdev;
 260        uint64_t old_start, new_start;
 261        struct radeon_fence *fence;
 262        unsigned num_pages;
 263        int r, ridx;
 264
 265        rdev = radeon_get_rdev(bo->bdev);
 266        ridx = radeon_copy_ring_index(rdev);
 267        old_start = (u64)old_mem->start << PAGE_SHIFT;
 268        new_start = (u64)new_mem->start << PAGE_SHIFT;
 269
 270        switch (old_mem->mem_type) {
 271        case TTM_PL_VRAM:
 272                old_start += rdev->mc.vram_start;
 273                break;
 274        case TTM_PL_TT:
 275                old_start += rdev->mc.gtt_start;
 276                break;
 277        default:
 278                DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 279                return -EINVAL;
 280        }
 281        switch (new_mem->mem_type) {
 282        case TTM_PL_VRAM:
 283                new_start += rdev->mc.vram_start;
 284                break;
 285        case TTM_PL_TT:
 286                new_start += rdev->mc.gtt_start;
 287                break;
 288        default:
 289                DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
 290                return -EINVAL;
 291        }
 292        if (!rdev->ring[ridx].ready) {
 293                DRM_ERROR("Trying to move memory with ring turned off.\n");
 294                return -EINVAL;
 295        }
 296
 297        BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
 298
 299        num_pages = new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
 300        fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->resv);
 301        if (IS_ERR(fence))
 302                return PTR_ERR(fence);
 303
 304        r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, new_mem);
 305        radeon_fence_unref(&fence);
 306        return r;
 307}
 308
 309static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
 310                                bool evict, bool interruptible,
 311                                bool no_wait_gpu,
 312                                struct ttm_mem_reg *new_mem)
 313{
 314        struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
 315        struct radeon_device *rdev;
 316        struct ttm_mem_reg *old_mem = &bo->mem;
 317        struct ttm_mem_reg tmp_mem;
 318        struct ttm_place placements;
 319        struct ttm_placement placement;
 320        int r;
 321
 322        rdev = radeon_get_rdev(bo->bdev);
 323        tmp_mem = *new_mem;
 324        tmp_mem.mm_node = NULL;
 325        placement.num_placement = 1;
 326        placement.placement = &placements;
 327        placement.num_busy_placement = 1;
 328        placement.busy_placement = &placements;
 329        placements.fpfn = 0;
 330        placements.lpfn = 0;
 331        placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 332        r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
 333        if (unlikely(r)) {
 334                return r;
 335        }
 336
 337        r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 338        if (unlikely(r)) {
 339                goto out_cleanup;
 340        }
 341
 342        r = ttm_tt_bind(bo->ttm, &tmp_mem, &ctx);
 343        if (unlikely(r)) {
 344                goto out_cleanup;
 345        }
 346        r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem);
 347        if (unlikely(r)) {
 348                goto out_cleanup;
 349        }
 350        r = ttm_bo_move_ttm(bo, &ctx, new_mem);
 351out_cleanup:
 352        ttm_bo_mem_put(bo, &tmp_mem);
 353        return r;
 354}
 355
 356static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
 357                                bool evict, bool interruptible,
 358                                bool no_wait_gpu,
 359                                struct ttm_mem_reg *new_mem)
 360{
 361        struct ttm_operation_ctx ctx = { interruptible, no_wait_gpu };
 362        struct radeon_device *rdev;
 363        struct ttm_mem_reg *old_mem = &bo->mem;
 364        struct ttm_mem_reg tmp_mem;
 365        struct ttm_placement placement;
 366        struct ttm_place placements;
 367        int r;
 368
 369        rdev = radeon_get_rdev(bo->bdev);
 370        tmp_mem = *new_mem;
 371        tmp_mem.mm_node = NULL;
 372        placement.num_placement = 1;
 373        placement.placement = &placements;
 374        placement.num_busy_placement = 1;
 375        placement.busy_placement = &placements;
 376        placements.fpfn = 0;
 377        placements.lpfn = 0;
 378        placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 379        r = ttm_bo_mem_space(bo, &placement, &tmp_mem, &ctx);
 380        if (unlikely(r)) {
 381                return r;
 382        }
 383        r = ttm_bo_move_ttm(bo, &ctx, &tmp_mem);
 384        if (unlikely(r)) {
 385                goto out_cleanup;
 386        }
 387        r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem);
 388        if (unlikely(r)) {
 389                goto out_cleanup;
 390        }
 391out_cleanup:
 392        ttm_bo_mem_put(bo, &tmp_mem);
 393        return r;
 394}
 395
 396static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
 397                          struct ttm_operation_ctx *ctx,
 398                          struct ttm_mem_reg *new_mem)
 399{
 400        struct radeon_device *rdev;
 401        struct radeon_bo *rbo;
 402        struct ttm_mem_reg *old_mem = &bo->mem;
 403        int r;
 404
 405        r = ttm_bo_wait(bo, ctx->interruptible, ctx->no_wait_gpu);
 406        if (r)
 407                return r;
 408
 409        /* Can't move a pinned BO */
 410        rbo = container_of(bo, struct radeon_bo, tbo);
 411        if (WARN_ON_ONCE(rbo->pin_count > 0))
 412                return -EINVAL;
 413
 414        rdev = radeon_get_rdev(bo->bdev);
 415        if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 416                radeon_move_null(bo, new_mem);
 417                return 0;
 418        }
 419        if ((old_mem->mem_type == TTM_PL_TT &&
 420             new_mem->mem_type == TTM_PL_SYSTEM) ||
 421            (old_mem->mem_type == TTM_PL_SYSTEM &&
 422             new_mem->mem_type == TTM_PL_TT)) {
 423                /* bind is enough */
 424                radeon_move_null(bo, new_mem);
 425                return 0;
 426        }
 427        if (!rdev->ring[radeon_copy_ring_index(rdev)].ready ||
 428            rdev->asic->copy.copy == NULL) {
 429                /* use memcpy */
 430                goto memcpy;
 431        }
 432
 433        if (old_mem->mem_type == TTM_PL_VRAM &&
 434            new_mem->mem_type == TTM_PL_SYSTEM) {
 435                r = radeon_move_vram_ram(bo, evict, ctx->interruptible,
 436                                        ctx->no_wait_gpu, new_mem);
 437        } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 438                   new_mem->mem_type == TTM_PL_VRAM) {
 439                r = radeon_move_ram_vram(bo, evict, ctx->interruptible,
 440                                            ctx->no_wait_gpu, new_mem);
 441        } else {
 442                r = radeon_move_blit(bo, evict, ctx->no_wait_gpu,
 443                                     new_mem, old_mem);
 444        }
 445
 446        if (r) {
 447memcpy:
 448                r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 449                if (r) {
 450                        return r;
 451                }
 452        }
 453
 454        /* update statistics */
 455        atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved);
 456        return 0;
 457}
 458
 459static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 460{
 461        struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 462        struct radeon_device *rdev = radeon_get_rdev(bdev);
 463
 464        mem->bus.addr = NULL;
 465        mem->bus.offset = 0;
 466        mem->bus.size = mem->num_pages << PAGE_SHIFT;
 467        mem->bus.base = 0;
 468        mem->bus.is_iomem = false;
 469        if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 470                return -EINVAL;
 471        switch (mem->mem_type) {
 472        case TTM_PL_SYSTEM:
 473                /* system memory */
 474                return 0;
 475        case TTM_PL_TT:
 476#if IS_ENABLED(CONFIG_AGP)
 477                if (rdev->flags & RADEON_IS_AGP) {
 478                        /* RADEON_IS_AGP is set only if AGP is active */
 479                        mem->bus.offset = mem->start << PAGE_SHIFT;
 480                        mem->bus.base = rdev->mc.agp_base;
 481                        mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
 482                }
 483#endif
 484                break;
 485        case TTM_PL_VRAM:
 486                mem->bus.offset = mem->start << PAGE_SHIFT;
 487                /* check if it's visible */
 488                if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
 489                        return -EINVAL;
 490                mem->bus.base = rdev->mc.aper_base;
 491                mem->bus.is_iomem = true;
 492#ifdef __alpha__
 493                /*
 494                 * Alpha: use bus.addr to hold the ioremap() return,
 495                 * so we can modify bus.base below.
 496                 */
 497                if (mem->placement & TTM_PL_FLAG_WC)
 498                        mem->bus.addr =
 499                                ioremap_wc(mem->bus.base + mem->bus.offset,
 500                                           mem->bus.size);
 501                else
 502                        mem->bus.addr =
 503                                ioremap_nocache(mem->bus.base + mem->bus.offset,
 504                                                mem->bus.size);
 505                if (!mem->bus.addr)
 506                        return -ENOMEM;
 507
 508                /*
 509                 * Alpha: Use just the bus offset plus
 510                 * the hose/domain memory base for bus.base.
 511                 * It then can be used to build PTEs for VRAM
 512                 * access, as done in ttm_bo_vm_fault().
 513                 */
 514                mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
 515                        rdev->ddev->hose->dense_mem_base;
 516#endif
 517                break;
 518        default:
 519                return -EINVAL;
 520        }
 521        return 0;
 522}
 523
 524static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 525{
 526}
 527
 528/*
 529 * TTM backend functions.
 530 */
 531struct radeon_ttm_tt {
 532        struct ttm_dma_tt               ttm;
 533        struct radeon_device            *rdev;
 534        u64                             offset;
 535
 536        uint64_t                        userptr;
 537        struct mm_struct                *usermm;
 538        uint32_t                        userflags;
 539};
 540
 541/* prepare the sg table with the user pages */
 542static int radeon_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 543{
 544        struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 545        struct radeon_ttm_tt *gtt = (void *)ttm;
 546        unsigned pinned = 0, nents;
 547        int r;
 548
 549        int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 550        enum dma_data_direction direction = write ?
 551                DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 552
 553        if (current->mm != gtt->usermm)
 554                return -EPERM;
 555
 556        if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
 557                /* check that we only pin down anonymous memory
 558                   to prevent problems with writeback */
 559                unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 560                struct vm_area_struct *vma;
 561                vma = find_vma(gtt->usermm, gtt->userptr);
 562                if (!vma || vma->vm_file || vma->vm_end < end)
 563                        return -EPERM;
 564        }
 565
 566        do {
 567                unsigned num_pages = ttm->num_pages - pinned;
 568                uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 569                struct page **pages = ttm->pages + pinned;
 570
 571                r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
 572                                   pages, NULL);
 573                if (r < 0)
 574                        goto release_pages;
 575
 576                pinned += r;
 577
 578        } while (pinned < ttm->num_pages);
 579
 580        r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 581                                      ttm->num_pages << PAGE_SHIFT,
 582                                      GFP_KERNEL);
 583        if (r)
 584                goto release_sg;
 585
 586        r = -ENOMEM;
 587        nents = dma_map_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 588        if (nents != ttm->sg->nents)
 589                goto release_sg;
 590
 591        drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 592                                         gtt->ttm.dma_address, ttm->num_pages);
 593
 594        return 0;
 595
 596release_sg:
 597        kfree(ttm->sg);
 598
 599release_pages:
 600        release_pages(ttm->pages, pinned);
 601        return r;
 602}
 603
 604static void radeon_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 605{
 606        struct radeon_device *rdev = radeon_get_rdev(ttm->bdev);
 607        struct radeon_ttm_tt *gtt = (void *)ttm;
 608        struct sg_page_iter sg_iter;
 609
 610        int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 611        enum dma_data_direction direction = write ?
 612                DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 613
 614        /* double check that we don't free the table twice */
 615        if (!ttm->sg->sgl)
 616                return;
 617
 618        /* free the sg table and pages again */
 619        dma_unmap_sg(rdev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 620
 621        for_each_sg_page(ttm->sg->sgl, &sg_iter, ttm->sg->nents, 0) {
 622                struct page *page = sg_page_iter_page(&sg_iter);
 623                if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
 624                        set_page_dirty(page);
 625
 626                mark_page_accessed(page);
 627                put_page(page);
 628        }
 629
 630        sg_free_table(ttm->sg);
 631}
 632
 633static int radeon_ttm_backend_bind(struct ttm_tt *ttm,
 634                                   struct ttm_mem_reg *bo_mem)
 635{
 636        struct radeon_ttm_tt *gtt = (void*)ttm;
 637        uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
 638                RADEON_GART_PAGE_WRITE;
 639        int r;
 640
 641        if (gtt->userptr) {
 642                radeon_ttm_tt_pin_userptr(ttm);
 643                flags &= ~RADEON_GART_PAGE_WRITE;
 644        }
 645
 646        gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
 647        if (!ttm->num_pages) {
 648                WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
 649                     ttm->num_pages, bo_mem, ttm);
 650        }
 651        if (ttm->caching_state == tt_cached)
 652                flags |= RADEON_GART_PAGE_SNOOP;
 653        r = radeon_gart_bind(gtt->rdev, gtt->offset, ttm->num_pages,
 654                             ttm->pages, gtt->ttm.dma_address, flags);
 655        if (r) {
 656                DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
 657                          ttm->num_pages, (unsigned)gtt->offset);
 658                return r;
 659        }
 660        return 0;
 661}
 662
 663static int radeon_ttm_backend_unbind(struct ttm_tt *ttm)
 664{
 665        struct radeon_ttm_tt *gtt = (void *)ttm;
 666
 667        radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages);
 668
 669        if (gtt->userptr)
 670                radeon_ttm_tt_unpin_userptr(ttm);
 671
 672        return 0;
 673}
 674
 675static void radeon_ttm_backend_destroy(struct ttm_tt *ttm)
 676{
 677        struct radeon_ttm_tt *gtt = (void *)ttm;
 678
 679        ttm_dma_tt_fini(&gtt->ttm);
 680        kfree(gtt);
 681}
 682
 683static struct ttm_backend_func radeon_backend_func = {
 684        .bind = &radeon_ttm_backend_bind,
 685        .unbind = &radeon_ttm_backend_unbind,
 686        .destroy = &radeon_ttm_backend_destroy,
 687};
 688
 689static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev,
 690                                    unsigned long size, uint32_t page_flags,
 691                                    struct page *dummy_read_page)
 692{
 693        struct radeon_device *rdev;
 694        struct radeon_ttm_tt *gtt;
 695
 696        rdev = radeon_get_rdev(bdev);
 697#if IS_ENABLED(CONFIG_AGP)
 698        if (rdev->flags & RADEON_IS_AGP) {
 699                return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge,
 700                                         size, page_flags, dummy_read_page);
 701        }
 702#endif
 703
 704        gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
 705        if (gtt == NULL) {
 706                return NULL;
 707        }
 708        gtt->ttm.ttm.func = &radeon_backend_func;
 709        gtt->rdev = rdev;
 710        if (ttm_dma_tt_init(&gtt->ttm, bdev, size, page_flags, dummy_read_page)) {
 711                kfree(gtt);
 712                return NULL;
 713        }
 714        return &gtt->ttm.ttm;
 715}
 716
 717static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct ttm_tt *ttm)
 718{
 719        if (!ttm || ttm->func != &radeon_backend_func)
 720                return NULL;
 721        return (struct radeon_ttm_tt *)ttm;
 722}
 723
 724static int radeon_ttm_tt_populate(struct ttm_tt *ttm,
 725                        struct ttm_operation_ctx *ctx)
 726{
 727        struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 728        struct radeon_device *rdev;
 729        bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 730
 731        if (ttm->state != tt_unpopulated)
 732                return 0;
 733
 734        if (gtt && gtt->userptr) {
 735                ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
 736                if (!ttm->sg)
 737                        return -ENOMEM;
 738
 739                ttm->page_flags |= TTM_PAGE_FLAG_SG;
 740                ttm->state = tt_unbound;
 741                return 0;
 742        }
 743
 744        if (slave && ttm->sg) {
 745                drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 746                                                 gtt->ttm.dma_address, ttm->num_pages);
 747                ttm->state = tt_unbound;
 748                return 0;
 749        }
 750
 751        rdev = radeon_get_rdev(ttm->bdev);
 752#if IS_ENABLED(CONFIG_AGP)
 753        if (rdev->flags & RADEON_IS_AGP) {
 754                return ttm_agp_tt_populate(ttm, ctx);
 755        }
 756#endif
 757
 758#ifdef CONFIG_SWIOTLB
 759        if (swiotlb_nr_tbl()) {
 760                return ttm_dma_populate(&gtt->ttm, rdev->dev, ctx);
 761        }
 762#endif
 763
 764        return ttm_populate_and_map_pages(rdev->dev, &gtt->ttm, ctx);
 765}
 766
 767static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm)
 768{
 769        struct radeon_device *rdev;
 770        struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 771        bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
 772
 773        if (gtt && gtt->userptr) {
 774                kfree(ttm->sg);
 775                ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
 776                return;
 777        }
 778
 779        if (slave)
 780                return;
 781
 782        rdev = radeon_get_rdev(ttm->bdev);
 783#if IS_ENABLED(CONFIG_AGP)
 784        if (rdev->flags & RADEON_IS_AGP) {
 785                ttm_agp_tt_unpopulate(ttm);
 786                return;
 787        }
 788#endif
 789
 790#ifdef CONFIG_SWIOTLB
 791        if (swiotlb_nr_tbl()) {
 792                ttm_dma_unpopulate(&gtt->ttm, rdev->dev);
 793                return;
 794        }
 795#endif
 796
 797        ttm_unmap_and_unpopulate_pages(rdev->dev, &gtt->ttm);
 798}
 799
 800int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
 801                              uint32_t flags)
 802{
 803        struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 804
 805        if (gtt == NULL)
 806                return -EINVAL;
 807
 808        gtt->userptr = addr;
 809        gtt->usermm = current->mm;
 810        gtt->userflags = flags;
 811        return 0;
 812}
 813
 814bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm)
 815{
 816        struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 817
 818        if (gtt == NULL)
 819                return false;
 820
 821        return !!gtt->userptr;
 822}
 823
 824bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm)
 825{
 826        struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(ttm);
 827
 828        if (gtt == NULL)
 829                return false;
 830
 831        return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
 832}
 833
 834static struct ttm_bo_driver radeon_bo_driver = {
 835        .ttm_tt_create = &radeon_ttm_tt_create,
 836        .ttm_tt_populate = &radeon_ttm_tt_populate,
 837        .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
 838        .invalidate_caches = &radeon_invalidate_caches,
 839        .init_mem_type = &radeon_init_mem_type,
 840        .eviction_valuable = ttm_bo_eviction_valuable,
 841        .evict_flags = &radeon_evict_flags,
 842        .move = &radeon_bo_move,
 843        .verify_access = &radeon_verify_access,
 844        .move_notify = &radeon_bo_move_notify,
 845        .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
 846        .io_mem_reserve = &radeon_ttm_io_mem_reserve,
 847        .io_mem_free = &radeon_ttm_io_mem_free,
 848};
 849
 850int radeon_ttm_init(struct radeon_device *rdev)
 851{
 852        int r;
 853
 854        r = radeon_ttm_global_init(rdev);
 855        if (r) {
 856                return r;
 857        }
 858        /* No others user of address space so set it to 0 */
 859        r = ttm_bo_device_init(&rdev->mman.bdev,
 860                               rdev->mman.bo_global_ref.ref.object,
 861                               &radeon_bo_driver,
 862                               rdev->ddev->anon_inode->i_mapping,
 863                               DRM_FILE_PAGE_OFFSET,
 864                               rdev->need_dma32);
 865        if (r) {
 866                DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
 867                return r;
 868        }
 869        rdev->mman.initialized = true;
 870        r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
 871                                rdev->mc.real_vram_size >> PAGE_SHIFT);
 872        if (r) {
 873                DRM_ERROR("Failed initializing VRAM heap.\n");
 874                return r;
 875        }
 876        /* Change the size here instead of the init above so only lpfn is affected */
 877        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 878
 879        r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
 880                             RADEON_GEM_DOMAIN_VRAM, 0, NULL,
 881                             NULL, &rdev->stolen_vga_memory);
 882        if (r) {
 883                return r;
 884        }
 885        r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
 886        if (r)
 887                return r;
 888        r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
 889        radeon_bo_unreserve(rdev->stolen_vga_memory);
 890        if (r) {
 891                radeon_bo_unref(&rdev->stolen_vga_memory);
 892                return r;
 893        }
 894        DRM_INFO("radeon: %uM of VRAM memory ready\n",
 895                 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
 896        r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
 897                                rdev->mc.gtt_size >> PAGE_SHIFT);
 898        if (r) {
 899                DRM_ERROR("Failed initializing GTT heap.\n");
 900                return r;
 901        }
 902        DRM_INFO("radeon: %uM of GTT memory ready.\n",
 903                 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
 904
 905        r = radeon_ttm_debugfs_init(rdev);
 906        if (r) {
 907                DRM_ERROR("Failed to init debugfs\n");
 908                return r;
 909        }
 910        return 0;
 911}
 912
 913void radeon_ttm_fini(struct radeon_device *rdev)
 914{
 915        int r;
 916
 917        if (!rdev->mman.initialized)
 918                return;
 919        radeon_ttm_debugfs_fini(rdev);
 920        if (rdev->stolen_vga_memory) {
 921                r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
 922                if (r == 0) {
 923                        radeon_bo_unpin(rdev->stolen_vga_memory);
 924                        radeon_bo_unreserve(rdev->stolen_vga_memory);
 925                }
 926                radeon_bo_unref(&rdev->stolen_vga_memory);
 927        }
 928        ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 929        ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
 930        ttm_bo_device_release(&rdev->mman.bdev);
 931        radeon_gart_fini(rdev);
 932        radeon_ttm_global_fini(rdev);
 933        rdev->mman.initialized = false;
 934        DRM_INFO("radeon: ttm finalized\n");
 935}
 936
 937/* this should only be called at bootup or when userspace
 938 * isn't running */
 939void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
 940{
 941        struct ttm_mem_type_manager *man;
 942
 943        if (!rdev->mman.initialized)
 944                return;
 945
 946        man = &rdev->mman.bdev.man[TTM_PL_VRAM];
 947        /* this just adjusts TTM size idea, which sets lpfn to the correct value */
 948        man->size = size >> PAGE_SHIFT;
 949}
 950
 951static struct vm_operations_struct radeon_ttm_vm_ops;
 952static const struct vm_operations_struct *ttm_vm_ops = NULL;
 953
 954static int radeon_ttm_fault(struct vm_fault *vmf)
 955{
 956        struct ttm_buffer_object *bo;
 957        struct radeon_device *rdev;
 958        int r;
 959
 960        bo = (struct ttm_buffer_object *)vmf->vma->vm_private_data;
 961        if (bo == NULL) {
 962                return VM_FAULT_NOPAGE;
 963        }
 964        rdev = radeon_get_rdev(bo->bdev);
 965        down_read(&rdev->pm.mclk_lock);
 966        r = ttm_vm_ops->fault(vmf);
 967        up_read(&rdev->pm.mclk_lock);
 968        return r;
 969}
 970
 971int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
 972{
 973        struct drm_file *file_priv;
 974        struct radeon_device *rdev;
 975        int r;
 976
 977        if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
 978                return -EINVAL;
 979        }
 980
 981        file_priv = filp->private_data;
 982        rdev = file_priv->minor->dev->dev_private;
 983        if (rdev == NULL) {
 984                return -EINVAL;
 985        }
 986        r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
 987        if (unlikely(r != 0)) {
 988                return r;
 989        }
 990        if (unlikely(ttm_vm_ops == NULL)) {
 991                ttm_vm_ops = vma->vm_ops;
 992                radeon_ttm_vm_ops = *ttm_vm_ops;
 993                radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
 994        }
 995        vma->vm_ops = &radeon_ttm_vm_ops;
 996        return 0;
 997}
 998
 999#if defined(CONFIG_DEBUG_FS)
1000
1001static int radeon_mm_dump_table(struct seq_file *m, void *data)
1002{
1003        struct drm_info_node *node = (struct drm_info_node *)m->private;
1004        unsigned ttm_pl = *(int*)node->info_ent->data;
1005        struct drm_device *dev = node->minor->dev;
1006        struct radeon_device *rdev = dev->dev_private;
1007        struct ttm_mem_type_manager *man = &rdev->mman.bdev.man[ttm_pl];
1008        struct drm_printer p = drm_seq_file_printer(m);
1009
1010        man->func->debug(man, &p);
1011        return 0;
1012}
1013
1014
1015static int ttm_pl_vram = TTM_PL_VRAM;
1016static int ttm_pl_tt = TTM_PL_TT;
1017
1018static struct drm_info_list radeon_ttm_debugfs_list[] = {
1019        {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram},
1020        {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt},
1021        {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
1022#ifdef CONFIG_SWIOTLB
1023        {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
1024#endif
1025};
1026
1027static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
1028{
1029        struct radeon_device *rdev = inode->i_private;
1030        i_size_write(inode, rdev->mc.mc_vram_size);
1031        filep->private_data = inode->i_private;
1032        return 0;
1033}
1034
1035static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
1036                                    size_t size, loff_t *pos)
1037{
1038        struct radeon_device *rdev = f->private_data;
1039        ssize_t result = 0;
1040        int r;
1041
1042        if (size & 0x3 || *pos & 0x3)
1043                return -EINVAL;
1044
1045        while (size) {
1046                unsigned long flags;
1047                uint32_t value;
1048
1049                if (*pos >= rdev->mc.mc_vram_size)
1050                        return result;
1051
1052                spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
1053                WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
1054                if (rdev->family >= CHIP_CEDAR)
1055                        WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
1056                value = RREG32(RADEON_MM_DATA);
1057                spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
1058
1059                r = put_user(value, (uint32_t *)buf);
1060                if (r)
1061                        return r;
1062
1063                result += 4;
1064                buf += 4;
1065                *pos += 4;
1066                size -= 4;
1067        }
1068
1069        return result;
1070}
1071
1072static const struct file_operations radeon_ttm_vram_fops = {
1073        .owner = THIS_MODULE,
1074        .open = radeon_ttm_vram_open,
1075        .read = radeon_ttm_vram_read,
1076        .llseek = default_llseek
1077};
1078
1079static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
1080{
1081        struct radeon_device *rdev = inode->i_private;
1082        i_size_write(inode, rdev->mc.gtt_size);
1083        filep->private_data = inode->i_private;
1084        return 0;
1085}
1086
1087static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
1088                                   size_t size, loff_t *pos)
1089{
1090        struct radeon_device *rdev = f->private_data;
1091        ssize_t result = 0;
1092        int r;
1093
1094        while (size) {
1095                loff_t p = *pos / PAGE_SIZE;
1096                unsigned off = *pos & ~PAGE_MASK;
1097                size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
1098                struct page *page;
1099                void *ptr;
1100
1101                if (p >= rdev->gart.num_cpu_pages)
1102                        return result;
1103
1104                page = rdev->gart.pages[p];
1105                if (page) {
1106                        ptr = kmap(page);
1107                        ptr += off;
1108
1109                        r = copy_to_user(buf, ptr, cur_size);
1110                        kunmap(rdev->gart.pages[p]);
1111                } else
1112                        r = clear_user(buf, cur_size);
1113
1114                if (r)
1115                        return -EFAULT;
1116
1117                result += cur_size;
1118                buf += cur_size;
1119                *pos += cur_size;
1120                size -= cur_size;
1121        }
1122
1123        return result;
1124}
1125
1126static const struct file_operations radeon_ttm_gtt_fops = {
1127        .owner = THIS_MODULE,
1128        .open = radeon_ttm_gtt_open,
1129        .read = radeon_ttm_gtt_read,
1130        .llseek = default_llseek
1131};
1132
1133#endif
1134
1135static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
1136{
1137#if defined(CONFIG_DEBUG_FS)
1138        unsigned count;
1139
1140        struct drm_minor *minor = rdev->ddev->primary;
1141        struct dentry *ent, *root = minor->debugfs_root;
1142
1143        ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root,
1144                                  rdev, &radeon_ttm_vram_fops);
1145        if (IS_ERR(ent))
1146                return PTR_ERR(ent);
1147        rdev->mman.vram = ent;
1148
1149        ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root,
1150                                  rdev, &radeon_ttm_gtt_fops);
1151        if (IS_ERR(ent))
1152                return PTR_ERR(ent);
1153        rdev->mman.gtt = ent;
1154
1155        count = ARRAY_SIZE(radeon_ttm_debugfs_list);
1156
1157#ifdef CONFIG_SWIOTLB
1158        if (!swiotlb_nr_tbl())
1159                --count;
1160#endif
1161
1162        return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count);
1163#else
1164
1165        return 0;
1166#endif
1167}
1168
1169static void radeon_ttm_debugfs_fini(struct radeon_device *rdev)
1170{
1171#if defined(CONFIG_DEBUG_FS)
1172
1173        debugfs_remove(rdev->mman.vram);
1174        rdev->mman.vram = NULL;
1175
1176        debugfs_remove(rdev->mman.gtt);
1177        rdev->mman.gtt = NULL;
1178#endif
1179}
1180