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35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/netdevice.h>
38#include <linux/etherdevice.h>
39#include <linux/ip.h>
40#include <linux/tcp.h>
41#include <linux/if_vlan.h>
42#include <net/addrconf.h>
43
44#include "i40iw.h"
45#include "i40iw_register.h"
46#include <net/netevent.h>
47#define CLIENT_IW_INTERFACE_VERSION_MAJOR 0
48#define CLIENT_IW_INTERFACE_VERSION_MINOR 01
49#define CLIENT_IW_INTERFACE_VERSION_BUILD 00
50
51#define DRV_VERSION_MAJOR 0
52#define DRV_VERSION_MINOR 5
53#define DRV_VERSION_BUILD 123
54#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
55 __stringify(DRV_VERSION_MINOR) "." __stringify(DRV_VERSION_BUILD)
56
57static int push_mode;
58module_param(push_mode, int, 0644);
59MODULE_PARM_DESC(push_mode, "Low latency mode: 0=disabled (default), 1=enabled)");
60
61static int debug;
62module_param(debug, int, 0644);
63MODULE_PARM_DESC(debug, "debug flags: 0=disabled (default), 0x7fffffff=all");
64
65static int resource_profile;
66module_param(resource_profile, int, 0644);
67MODULE_PARM_DESC(resource_profile,
68 "Resource Profile: 0=no VF RDMA support (default), 1=Weighted VF, 2=Even Distribution");
69
70static int max_rdma_vfs = 32;
71module_param(max_rdma_vfs, int, 0644);
72MODULE_PARM_DESC(max_rdma_vfs, "Maximum VF count: 0-32 32=default");
73static int mpa_version = 2;
74module_param(mpa_version, int, 0644);
75MODULE_PARM_DESC(mpa_version, "MPA version to be used in MPA Req/Resp 1 or 2");
76
77MODULE_AUTHOR("Intel Corporation, <e1000-rdma@lists.sourceforge.net>");
78MODULE_DESCRIPTION("Intel(R) Ethernet Connection X722 iWARP RDMA Driver");
79MODULE_LICENSE("Dual BSD/GPL");
80
81static struct i40e_client i40iw_client;
82static char i40iw_client_name[I40E_CLIENT_STR_LENGTH] = "i40iw";
83
84static LIST_HEAD(i40iw_handlers);
85static spinlock_t i40iw_handler_lock;
86
87static enum i40iw_status_code i40iw_virtchnl_send(struct i40iw_sc_dev *dev,
88 u32 vf_id, u8 *msg, u16 len);
89
90static struct notifier_block i40iw_inetaddr_notifier = {
91 .notifier_call = i40iw_inetaddr_event
92};
93
94static struct notifier_block i40iw_inetaddr6_notifier = {
95 .notifier_call = i40iw_inet6addr_event
96};
97
98static struct notifier_block i40iw_net_notifier = {
99 .notifier_call = i40iw_net_event
100};
101
102static struct notifier_block i40iw_netdevice_notifier = {
103 .notifier_call = i40iw_netdevice_event
104};
105
106
107
108
109
110static struct i40iw_handler *i40iw_find_i40e_handler(struct i40e_info *ldev)
111{
112 struct i40iw_handler *hdl;
113 unsigned long flags;
114
115 spin_lock_irqsave(&i40iw_handler_lock, flags);
116 list_for_each_entry(hdl, &i40iw_handlers, list) {
117 if (hdl->ldev.netdev == ldev->netdev) {
118 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
119 return hdl;
120 }
121 }
122 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
123 return NULL;
124}
125
126
127
128
129
130struct i40iw_handler *i40iw_find_netdev(struct net_device *netdev)
131{
132 struct i40iw_handler *hdl;
133 unsigned long flags;
134
135 spin_lock_irqsave(&i40iw_handler_lock, flags);
136 list_for_each_entry(hdl, &i40iw_handlers, list) {
137 if (hdl->ldev.netdev == netdev) {
138 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
139 return hdl;
140 }
141 }
142 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
143 return NULL;
144}
145
146
147
148
149
150static void i40iw_add_handler(struct i40iw_handler *hdl)
151{
152 unsigned long flags;
153
154 spin_lock_irqsave(&i40iw_handler_lock, flags);
155 list_add(&hdl->list, &i40iw_handlers);
156 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
157}
158
159
160
161
162
163static int i40iw_del_handler(struct i40iw_handler *hdl)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&i40iw_handler_lock, flags);
168 list_del(&hdl->list);
169 spin_unlock_irqrestore(&i40iw_handler_lock, flags);
170 return 0;
171}
172
173
174
175
176
177
178static void i40iw_enable_intr(struct i40iw_sc_dev *dev, u32 msix_id)
179{
180 u32 val;
181
182 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
183 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
184 (3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
185 if (dev->is_pf)
186 i40iw_wr32(dev->hw, I40E_PFINT_DYN_CTLN(msix_id - 1), val);
187 else
188 i40iw_wr32(dev->hw, I40E_VFINT_DYN_CTLN1(msix_id - 1), val);
189}
190
191
192
193
194
195static void i40iw_dpc(unsigned long data)
196{
197 struct i40iw_device *iwdev = (struct i40iw_device *)data;
198
199 if (iwdev->msix_shared)
200 i40iw_process_ceq(iwdev, iwdev->ceqlist);
201 i40iw_process_aeq(iwdev);
202 i40iw_enable_intr(&iwdev->sc_dev, iwdev->iw_msixtbl[0].idx);
203}
204
205
206
207
208
209static void i40iw_ceq_dpc(unsigned long data)
210{
211 struct i40iw_ceq *iwceq = (struct i40iw_ceq *)data;
212 struct i40iw_device *iwdev = iwceq->iwdev;
213
214 i40iw_process_ceq(iwdev, iwceq);
215 i40iw_enable_intr(&iwdev->sc_dev, iwceq->msix_idx);
216}
217
218
219
220
221
222
223static irqreturn_t i40iw_irq_handler(int irq, void *data)
224{
225 struct i40iw_device *iwdev = (struct i40iw_device *)data;
226
227 tasklet_schedule(&iwdev->dpc_tasklet);
228 return IRQ_HANDLED;
229}
230
231
232
233
234
235
236
237
238
239static void i40iw_destroy_cqp(struct i40iw_device *iwdev, bool free_hwcqp)
240{
241 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
242 struct i40iw_cqp *cqp = &iwdev->cqp;
243
244 if (free_hwcqp)
245 dev->cqp_ops->cqp_destroy(dev->cqp);
246
247 i40iw_cleanup_pending_cqp_op(iwdev);
248
249 i40iw_free_dma_mem(dev->hw, &cqp->sq);
250 kfree(cqp->scratch_array);
251 iwdev->cqp.scratch_array = NULL;
252
253 kfree(cqp->cqp_requests);
254 cqp->cqp_requests = NULL;
255}
256
257
258
259
260
261
262
263
264
265static void i40iw_disable_irq(struct i40iw_sc_dev *dev,
266 struct i40iw_msix_vector *msix_vec,
267 void *dev_id)
268{
269 if (dev->is_pf)
270 i40iw_wr32(dev->hw, I40E_PFINT_DYN_CTLN(msix_vec->idx - 1), 0);
271 else
272 i40iw_wr32(dev->hw, I40E_VFINT_DYN_CTLN1(msix_vec->idx - 1), 0);
273 irq_set_affinity_hint(msix_vec->irq, NULL);
274 free_irq(msix_vec->irq, dev_id);
275}
276
277
278
279
280
281
282
283
284
285static void i40iw_destroy_aeq(struct i40iw_device *iwdev)
286{
287 enum i40iw_status_code status = I40IW_ERR_NOT_READY;
288 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
289 struct i40iw_aeq *aeq = &iwdev->aeq;
290
291 if (!iwdev->msix_shared)
292 i40iw_disable_irq(dev, iwdev->iw_msixtbl, (void *)iwdev);
293 if (iwdev->reset)
294 goto exit;
295
296 if (!dev->aeq_ops->aeq_destroy(&aeq->sc_aeq, 0, 1))
297 status = dev->aeq_ops->aeq_destroy_done(&aeq->sc_aeq);
298 if (status)
299 i40iw_pr_err("destroy aeq failed %d\n", status);
300
301exit:
302 i40iw_free_dma_mem(dev->hw, &aeq->mem);
303}
304
305
306
307
308
309
310
311
312
313static void i40iw_destroy_ceq(struct i40iw_device *iwdev,
314 struct i40iw_ceq *iwceq)
315{
316 enum i40iw_status_code status;
317 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
318
319 if (iwdev->reset)
320 goto exit;
321
322 status = dev->ceq_ops->ceq_destroy(&iwceq->sc_ceq, 0, 1);
323 if (status) {
324 i40iw_pr_err("ceq destroy command failed %d\n", status);
325 goto exit;
326 }
327
328 status = dev->ceq_ops->cceq_destroy_done(&iwceq->sc_ceq);
329 if (status)
330 i40iw_pr_err("ceq destroy completion failed %d\n", status);
331exit:
332 i40iw_free_dma_mem(dev->hw, &iwceq->mem);
333}
334
335
336
337
338
339
340
341
342static void i40iw_dele_ceqs(struct i40iw_device *iwdev)
343{
344 u32 i = 0;
345 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
346 struct i40iw_ceq *iwceq = iwdev->ceqlist;
347 struct i40iw_msix_vector *msix_vec = iwdev->iw_msixtbl;
348
349 if (iwdev->msix_shared) {
350 i40iw_disable_irq(dev, msix_vec, (void *)iwdev);
351 i40iw_destroy_ceq(iwdev, iwceq);
352 iwceq++;
353 i++;
354 }
355
356 for (msix_vec++; i < iwdev->ceqs_count; i++, msix_vec++, iwceq++) {
357 i40iw_disable_irq(dev, msix_vec, (void *)iwceq);
358 i40iw_destroy_ceq(iwdev, iwceq);
359 }
360
361 iwdev->sc_dev.ceq_valid = false;
362}
363
364
365
366
367
368
369
370
371static void i40iw_destroy_ccq(struct i40iw_device *iwdev)
372{
373 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
374 struct i40iw_ccq *ccq = &iwdev->ccq;
375 enum i40iw_status_code status = 0;
376
377 if (!iwdev->reset)
378 status = dev->ccq_ops->ccq_destroy(dev->ccq, 0, true);
379 if (status)
380 i40iw_pr_err("ccq destroy failed %d\n", status);
381 i40iw_free_dma_mem(dev->hw, &ccq->mem_cq);
382}
383
384
385static enum i40iw_hmc_rsrc_type iw_hmc_obj_types[] = {
386 I40IW_HMC_IW_QP,
387 I40IW_HMC_IW_CQ,
388 I40IW_HMC_IW_HTE,
389 I40IW_HMC_IW_ARP,
390 I40IW_HMC_IW_APBVT_ENTRY,
391 I40IW_HMC_IW_MR,
392 I40IW_HMC_IW_XF,
393 I40IW_HMC_IW_XFFL,
394 I40IW_HMC_IW_Q1,
395 I40IW_HMC_IW_Q1FL,
396 I40IW_HMC_IW_TIMER,
397};
398
399
400
401
402
403
404
405
406static void i40iw_close_hmc_objects_type(struct i40iw_sc_dev *dev,
407 enum i40iw_hmc_rsrc_type obj_type,
408 struct i40iw_hmc_info *hmc_info,
409 bool is_pf,
410 bool reset)
411{
412 struct i40iw_hmc_del_obj_info info;
413
414 memset(&info, 0, sizeof(info));
415 info.hmc_info = hmc_info;
416 info.rsrc_type = obj_type;
417 info.count = hmc_info->hmc_obj[obj_type].cnt;
418 info.is_pf = is_pf;
419 if (dev->hmc_ops->del_hmc_object(dev, &info, reset))
420 i40iw_pr_err("del obj of type %d failed\n", obj_type);
421}
422
423
424
425
426
427
428
429
430
431static void i40iw_del_hmc_objects(struct i40iw_sc_dev *dev,
432 struct i40iw_hmc_info *hmc_info,
433 bool is_pf,
434 bool reset)
435{
436 unsigned int i;
437
438 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++)
439 i40iw_close_hmc_objects_type(dev, iw_hmc_obj_types[i], hmc_info, is_pf, reset);
440}
441
442
443
444
445
446static irqreturn_t i40iw_ceq_handler(int irq, void *data)
447{
448 struct i40iw_ceq *iwceq = (struct i40iw_ceq *)data;
449
450 if (iwceq->irq != irq)
451 i40iw_pr_err("expected irq = %d received irq = %d\n", iwceq->irq, irq);
452 tasklet_schedule(&iwceq->dpc_tasklet);
453 return IRQ_HANDLED;
454}
455
456
457
458
459
460
461static enum i40iw_status_code i40iw_create_hmc_obj_type(struct i40iw_sc_dev *dev,
462 struct i40iw_hmc_create_obj_info *info)
463{
464 return dev->hmc_ops->create_hmc_object(dev, info);
465}
466
467
468
469
470
471
472
473
474
475static enum i40iw_status_code i40iw_create_hmc_objs(struct i40iw_device *iwdev,
476 bool is_pf)
477{
478 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
479 struct i40iw_hmc_create_obj_info info;
480 enum i40iw_status_code status;
481 int i;
482
483 memset(&info, 0, sizeof(info));
484 info.hmc_info = dev->hmc_info;
485 info.is_pf = is_pf;
486 info.entry_type = iwdev->sd_type;
487 for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) {
488 info.rsrc_type = iw_hmc_obj_types[i];
489 info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt;
490 info.add_sd_cnt = 0;
491 status = i40iw_create_hmc_obj_type(dev, &info);
492 if (status) {
493 i40iw_pr_err("create obj type %d status = %d\n",
494 iw_hmc_obj_types[i], status);
495 break;
496 }
497 }
498 if (!status)
499 return (dev->cqp_misc_ops->static_hmc_pages_allocated(dev->cqp, 0,
500 dev->hmc_fn_id,
501 true, true));
502
503 while (i) {
504 i--;
505
506 i40iw_close_hmc_objects_type(dev,
507 iw_hmc_obj_types[i],
508 dev->hmc_info,
509 is_pf,
510 false);
511 }
512 return status;
513}
514
515
516
517
518
519
520
521
522
523
524
525
526enum i40iw_status_code i40iw_obj_aligned_mem(struct i40iw_device *iwdev,
527 struct i40iw_dma_mem *memptr,
528 u32 size,
529 u32 mask)
530{
531 unsigned long va, newva;
532 unsigned long extra;
533
534 va = (unsigned long)iwdev->obj_next.va;
535 newva = va;
536 if (mask)
537 newva = ALIGN(va, (mask + 1));
538 extra = newva - va;
539 memptr->va = (u8 *)va + extra;
540 memptr->pa = iwdev->obj_next.pa + extra;
541 memptr->size = size;
542 if ((memptr->va + size) > (iwdev->obj_mem.va + iwdev->obj_mem.size))
543 return I40IW_ERR_NO_MEMORY;
544
545 iwdev->obj_next.va = memptr->va + size;
546 iwdev->obj_next.pa = memptr->pa + size;
547 return 0;
548}
549
550
551
552
553
554
555
556
557static enum i40iw_status_code i40iw_create_cqp(struct i40iw_device *iwdev)
558{
559 enum i40iw_status_code status;
560 u32 sqsize = I40IW_CQP_SW_SQSIZE_2048;
561 struct i40iw_dma_mem mem;
562 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
563 struct i40iw_cqp_init_info cqp_init_info;
564 struct i40iw_cqp *cqp = &iwdev->cqp;
565 u16 maj_err, min_err;
566 int i;
567
568 cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), GFP_KERNEL);
569 if (!cqp->cqp_requests)
570 return I40IW_ERR_NO_MEMORY;
571 cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), GFP_KERNEL);
572 if (!cqp->scratch_array) {
573 kfree(cqp->cqp_requests);
574 return I40IW_ERR_NO_MEMORY;
575 }
576 dev->cqp = &cqp->sc_cqp;
577 dev->cqp->dev = dev;
578 memset(&cqp_init_info, 0, sizeof(cqp_init_info));
579 status = i40iw_allocate_dma_mem(dev->hw, &cqp->sq,
580 (sizeof(struct i40iw_cqp_sq_wqe) * sqsize),
581 I40IW_CQP_ALIGNMENT);
582 if (status)
583 goto exit;
584 status = i40iw_obj_aligned_mem(iwdev, &mem, sizeof(struct i40iw_cqp_ctx),
585 I40IW_HOST_CTX_ALIGNMENT_MASK);
586 if (status)
587 goto exit;
588 dev->cqp->host_ctx_pa = mem.pa;
589 dev->cqp->host_ctx = mem.va;
590
591 cqp_init_info.dev = dev;
592 cqp_init_info.sq_size = sqsize;
593 cqp_init_info.sq = cqp->sq.va;
594 cqp_init_info.sq_pa = cqp->sq.pa;
595 cqp_init_info.host_ctx_pa = mem.pa;
596 cqp_init_info.host_ctx = mem.va;
597 cqp_init_info.hmc_profile = iwdev->resource_profile;
598 cqp_init_info.enabled_vf_count = iwdev->max_rdma_vfs;
599 cqp_init_info.scratch_array = cqp->scratch_array;
600 status = dev->cqp_ops->cqp_init(dev->cqp, &cqp_init_info);
601 if (status) {
602 i40iw_pr_err("cqp init status %d\n", status);
603 goto exit;
604 }
605 status = dev->cqp_ops->cqp_create(dev->cqp, &maj_err, &min_err);
606 if (status) {
607 i40iw_pr_err("cqp create status %d maj_err %d min_err %d\n",
608 status, maj_err, min_err);
609 goto exit;
610 }
611 spin_lock_init(&cqp->req_lock);
612 INIT_LIST_HEAD(&cqp->cqp_avail_reqs);
613 INIT_LIST_HEAD(&cqp->cqp_pending_reqs);
614
615 for (i = 0; i < sqsize; i++) {
616 init_waitqueue_head(&cqp->cqp_requests[i].waitq);
617 list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs);
618 }
619 return 0;
620exit:
621
622 i40iw_destroy_cqp(iwdev, false);
623 return status;
624}
625
626
627
628
629
630
631
632
633static enum i40iw_status_code i40iw_create_ccq(struct i40iw_device *iwdev)
634{
635 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
636 struct i40iw_dma_mem mem;
637 enum i40iw_status_code status;
638 struct i40iw_ccq_init_info info;
639 struct i40iw_ccq *ccq = &iwdev->ccq;
640
641 memset(&info, 0, sizeof(info));
642 dev->ccq = &ccq->sc_cq;
643 dev->ccq->dev = dev;
644 info.dev = dev;
645 ccq->shadow_area.size = sizeof(struct i40iw_cq_shadow_area);
646 ccq->mem_cq.size = sizeof(struct i40iw_cqe) * IW_CCQ_SIZE;
647 status = i40iw_allocate_dma_mem(dev->hw, &ccq->mem_cq,
648 ccq->mem_cq.size, I40IW_CQ0_ALIGNMENT);
649 if (status)
650 goto exit;
651 status = i40iw_obj_aligned_mem(iwdev, &mem, ccq->shadow_area.size,
652 I40IW_SHADOWAREA_MASK);
653 if (status)
654 goto exit;
655 ccq->sc_cq.back_cq = (void *)ccq;
656
657 info.cq_base = ccq->mem_cq.va;
658 info.cq_pa = ccq->mem_cq.pa;
659 info.num_elem = IW_CCQ_SIZE;
660 info.shadow_area = mem.va;
661 info.shadow_area_pa = mem.pa;
662 info.ceqe_mask = false;
663 info.ceq_id_valid = true;
664 info.shadow_read_threshold = 16;
665 status = dev->ccq_ops->ccq_init(dev->ccq, &info);
666 if (!status)
667 status = dev->ccq_ops->ccq_create(dev->ccq, 0, true, true);
668exit:
669 if (status)
670 i40iw_free_dma_mem(dev->hw, &ccq->mem_cq);
671 return status;
672}
673
674
675
676
677
678
679
680
681
682
683
684static enum i40iw_status_code i40iw_configure_ceq_vector(struct i40iw_device *iwdev,
685 struct i40iw_ceq *iwceq,
686 u32 ceq_id,
687 struct i40iw_msix_vector *msix_vec)
688{
689 enum i40iw_status_code status;
690 cpumask_t mask;
691
692 if (iwdev->msix_shared && !ceq_id) {
693 tasklet_init(&iwdev->dpc_tasklet, i40iw_dpc, (unsigned long)iwdev);
694 status = request_irq(msix_vec->irq, i40iw_irq_handler, 0, "AEQCEQ", iwdev);
695 } else {
696 tasklet_init(&iwceq->dpc_tasklet, i40iw_ceq_dpc, (unsigned long)iwceq);
697 status = request_irq(msix_vec->irq, i40iw_ceq_handler, 0, "CEQ", iwceq);
698 }
699
700 cpumask_clear(&mask);
701 cpumask_set_cpu(msix_vec->cpu_affinity, &mask);
702 irq_set_affinity_hint(msix_vec->irq, &mask);
703
704 if (status) {
705 i40iw_pr_err("ceq irq config fail\n");
706 return I40IW_ERR_CONFIG;
707 }
708 msix_vec->ceq_id = ceq_id;
709
710 return 0;
711}
712
713
714
715
716
717
718
719
720
721
722static enum i40iw_status_code i40iw_create_ceq(struct i40iw_device *iwdev,
723 struct i40iw_ceq *iwceq,
724 u32 ceq_id)
725{
726 enum i40iw_status_code status;
727 struct i40iw_ceq_init_info info;
728 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
729 u64 scratch;
730
731 memset(&info, 0, sizeof(info));
732 info.ceq_id = ceq_id;
733 iwceq->iwdev = iwdev;
734 iwceq->mem.size = sizeof(struct i40iw_ceqe) *
735 iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
736 status = i40iw_allocate_dma_mem(dev->hw, &iwceq->mem, iwceq->mem.size,
737 I40IW_CEQ_ALIGNMENT);
738 if (status)
739 goto exit;
740 info.ceq_id = ceq_id;
741 info.ceqe_base = iwceq->mem.va;
742 info.ceqe_pa = iwceq->mem.pa;
743
744 info.elem_cnt = iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
745 iwceq->sc_ceq.ceq_id = ceq_id;
746 info.dev = dev;
747 scratch = (uintptr_t)&iwdev->cqp.sc_cqp;
748 status = dev->ceq_ops->ceq_init(&iwceq->sc_ceq, &info);
749 if (!status)
750 status = dev->ceq_ops->cceq_create(&iwceq->sc_ceq, scratch);
751
752exit:
753 if (status)
754 i40iw_free_dma_mem(dev->hw, &iwceq->mem);
755 return status;
756}
757
758void i40iw_request_reset(struct i40iw_device *iwdev)
759{
760 struct i40e_info *ldev = iwdev->ldev;
761
762 ldev->ops->request_reset(ldev, iwdev->client, 1);
763}
764
765
766
767
768
769
770
771
772
773
774static enum i40iw_status_code i40iw_setup_ceqs(struct i40iw_device *iwdev,
775 struct i40e_info *ldev)
776{
777 u32 i;
778 u32 ceq_id;
779 struct i40iw_ceq *iwceq;
780 struct i40iw_msix_vector *msix_vec;
781 enum i40iw_status_code status = 0;
782 u32 num_ceqs;
783
784 if (ldev && ldev->ops && ldev->ops->setup_qvlist) {
785 status = ldev->ops->setup_qvlist(ldev, &i40iw_client,
786 iwdev->iw_qvlist);
787 if (status)
788 goto exit;
789 } else {
790 status = I40IW_ERR_BAD_PTR;
791 goto exit;
792 }
793
794 num_ceqs = min(iwdev->msix_count, iwdev->sc_dev.hmc_fpm_misc.max_ceqs);
795 iwdev->ceqlist = kcalloc(num_ceqs, sizeof(*iwdev->ceqlist), GFP_KERNEL);
796 if (!iwdev->ceqlist) {
797 status = I40IW_ERR_NO_MEMORY;
798 goto exit;
799 }
800 i = (iwdev->msix_shared) ? 0 : 1;
801 for (ceq_id = 0; i < num_ceqs; i++, ceq_id++) {
802 iwceq = &iwdev->ceqlist[ceq_id];
803 status = i40iw_create_ceq(iwdev, iwceq, ceq_id);
804 if (status) {
805 i40iw_pr_err("create ceq status = %d\n", status);
806 break;
807 }
808
809 msix_vec = &iwdev->iw_msixtbl[i];
810 iwceq->irq = msix_vec->irq;
811 iwceq->msix_idx = msix_vec->idx;
812 status = i40iw_configure_ceq_vector(iwdev, iwceq, ceq_id, msix_vec);
813 if (status) {
814 i40iw_destroy_ceq(iwdev, iwceq);
815 break;
816 }
817 i40iw_enable_intr(&iwdev->sc_dev, msix_vec->idx);
818 iwdev->ceqs_count++;
819 }
820exit:
821 if (status && !iwdev->ceqs_count) {
822 kfree(iwdev->ceqlist);
823 iwdev->ceqlist = NULL;
824 return status;
825 } else {
826 iwdev->sc_dev.ceq_valid = true;
827 return 0;
828 }
829
830}
831
832
833
834
835
836
837
838
839static enum i40iw_status_code i40iw_configure_aeq_vector(struct i40iw_device *iwdev)
840{
841 struct i40iw_msix_vector *msix_vec = iwdev->iw_msixtbl;
842 u32 ret = 0;
843
844 if (!iwdev->msix_shared) {
845 tasklet_init(&iwdev->dpc_tasklet, i40iw_dpc, (unsigned long)iwdev);
846 ret = request_irq(msix_vec->irq, i40iw_irq_handler, 0, "i40iw", iwdev);
847 }
848 if (ret) {
849 i40iw_pr_err("aeq irq config fail\n");
850 return I40IW_ERR_CONFIG;
851 }
852
853 return 0;
854}
855
856
857
858
859
860
861
862
863static enum i40iw_status_code i40iw_create_aeq(struct i40iw_device *iwdev)
864{
865 enum i40iw_status_code status;
866 struct i40iw_aeq_init_info info;
867 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
868 struct i40iw_aeq *aeq = &iwdev->aeq;
869 u64 scratch = 0;
870 u32 aeq_size;
871
872 aeq_size = 2 * iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_QP].cnt +
873 iwdev->sc_dev.hmc_info->hmc_obj[I40IW_HMC_IW_CQ].cnt;
874 memset(&info, 0, sizeof(info));
875 aeq->mem.size = sizeof(struct i40iw_sc_aeqe) * aeq_size;
876 status = i40iw_allocate_dma_mem(dev->hw, &aeq->mem, aeq->mem.size,
877 I40IW_AEQ_ALIGNMENT);
878 if (status)
879 goto exit;
880
881 info.aeqe_base = aeq->mem.va;
882 info.aeq_elem_pa = aeq->mem.pa;
883 info.elem_cnt = aeq_size;
884 info.dev = dev;
885 status = dev->aeq_ops->aeq_init(&aeq->sc_aeq, &info);
886 if (status)
887 goto exit;
888 status = dev->aeq_ops->aeq_create(&aeq->sc_aeq, scratch, 1);
889 if (!status)
890 status = dev->aeq_ops->aeq_create_done(&aeq->sc_aeq);
891exit:
892 if (status)
893 i40iw_free_dma_mem(dev->hw, &aeq->mem);
894 return status;
895}
896
897
898
899
900
901
902
903
904static enum i40iw_status_code i40iw_setup_aeq(struct i40iw_device *iwdev)
905{
906 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
907 enum i40iw_status_code status;
908
909 status = i40iw_create_aeq(iwdev);
910 if (status)
911 return status;
912
913 status = i40iw_configure_aeq_vector(iwdev);
914 if (status) {
915 i40iw_destroy_aeq(iwdev);
916 return status;
917 }
918
919 if (!iwdev->msix_shared)
920 i40iw_enable_intr(dev, iwdev->iw_msixtbl[0].idx);
921 return 0;
922}
923
924
925
926
927
928
929
930static enum i40iw_status_code i40iw_initialize_ilq(struct i40iw_device *iwdev)
931{
932 struct i40iw_puda_rsrc_info info;
933 enum i40iw_status_code status;
934
935 memset(&info, 0, sizeof(info));
936 info.type = I40IW_PUDA_RSRC_TYPE_ILQ;
937 info.cq_id = 1;
938 info.qp_id = 0;
939 info.count = 1;
940 info.pd_id = 1;
941 info.sq_size = 8192;
942 info.rq_size = 8192;
943 info.buf_size = 1024;
944 info.tx_buf_cnt = 16384;
945 info.receive = i40iw_receive_ilq;
946 info.xmit_complete = i40iw_free_sqbuf;
947 status = i40iw_puda_create_rsrc(&iwdev->vsi, &info);
948 if (status)
949 i40iw_pr_err("ilq create fail\n");
950 return status;
951}
952
953
954
955
956
957
958
959static enum i40iw_status_code i40iw_initialize_ieq(struct i40iw_device *iwdev)
960{
961 struct i40iw_puda_rsrc_info info;
962 enum i40iw_status_code status;
963
964 memset(&info, 0, sizeof(info));
965 info.type = I40IW_PUDA_RSRC_TYPE_IEQ;
966 info.cq_id = 2;
967 info.qp_id = iwdev->vsi.exception_lan_queue;
968 info.count = 1;
969 info.pd_id = 2;
970 info.sq_size = 8192;
971 info.rq_size = 8192;
972 info.buf_size = iwdev->vsi.mtu + VLAN_ETH_HLEN;
973 info.tx_buf_cnt = 4096;
974 status = i40iw_puda_create_rsrc(&iwdev->vsi, &info);
975 if (status)
976 i40iw_pr_err("ieq create fail\n");
977 return status;
978}
979
980
981
982
983
984void i40iw_reinitialize_ieq(struct i40iw_sc_dev *dev)
985{
986 struct i40iw_device *iwdev = (struct i40iw_device *)dev->back_dev;
987
988 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_IEQ, false);
989 if (i40iw_initialize_ieq(iwdev)) {
990 iwdev->reset = true;
991 i40iw_request_reset(iwdev);
992 }
993}
994
995
996
997
998
999
1000
1001
1002
1003static enum i40iw_status_code i40iw_hmc_setup(struct i40iw_device *iwdev)
1004{
1005 enum i40iw_status_code status;
1006
1007 iwdev->sd_type = I40IW_SD_TYPE_DIRECT;
1008 status = i40iw_config_fpm_values(&iwdev->sc_dev, IW_CFG_FPM_QP_COUNT);
1009 if (status)
1010 goto exit;
1011 status = i40iw_create_hmc_objs(iwdev, true);
1012 if (status)
1013 goto exit;
1014 iwdev->init_state = HMC_OBJS_CREATED;
1015exit:
1016 return status;
1017}
1018
1019
1020
1021
1022
1023static void i40iw_del_init_mem(struct i40iw_device *iwdev)
1024{
1025 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1026
1027 i40iw_free_dma_mem(&iwdev->hw, &iwdev->obj_mem);
1028 kfree(dev->hmc_info->sd_table.sd_entry);
1029 dev->hmc_info->sd_table.sd_entry = NULL;
1030 kfree(iwdev->mem_resources);
1031 iwdev->mem_resources = NULL;
1032 kfree(iwdev->ceqlist);
1033 iwdev->ceqlist = NULL;
1034 kfree(iwdev->iw_msixtbl);
1035 iwdev->iw_msixtbl = NULL;
1036 kfree(iwdev->hmc_info_mem);
1037 iwdev->hmc_info_mem = NULL;
1038}
1039
1040
1041
1042
1043
1044
1045static void i40iw_del_macip_entry(struct i40iw_device *iwdev, u8 idx)
1046{
1047 struct i40iw_cqp *iwcqp = &iwdev->cqp;
1048 struct i40iw_cqp_request *cqp_request;
1049 struct cqp_commands_info *cqp_info;
1050 enum i40iw_status_code status = 0;
1051
1052 cqp_request = i40iw_get_cqp_request(iwcqp, true);
1053 if (!cqp_request) {
1054 i40iw_pr_err("cqp_request memory failed\n");
1055 return;
1056 }
1057 cqp_info = &cqp_request->info;
1058 cqp_info->cqp_cmd = OP_DELETE_LOCAL_MAC_IPADDR_ENTRY;
1059 cqp_info->post_sq = 1;
1060 cqp_info->in.u.del_local_mac_ipaddr_entry.cqp = &iwcqp->sc_cqp;
1061 cqp_info->in.u.del_local_mac_ipaddr_entry.scratch = (uintptr_t)cqp_request;
1062 cqp_info->in.u.del_local_mac_ipaddr_entry.entry_idx = idx;
1063 cqp_info->in.u.del_local_mac_ipaddr_entry.ignore_ref_count = 0;
1064 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1065 if (status)
1066 i40iw_pr_err("CQP-OP Del MAC Ip entry fail");
1067}
1068
1069
1070
1071
1072
1073
1074
1075static enum i40iw_status_code i40iw_add_mac_ipaddr_entry(struct i40iw_device *iwdev,
1076 u8 *mac_addr,
1077 u8 idx)
1078{
1079 struct i40iw_local_mac_ipaddr_entry_info *info;
1080 struct i40iw_cqp *iwcqp = &iwdev->cqp;
1081 struct i40iw_cqp_request *cqp_request;
1082 struct cqp_commands_info *cqp_info;
1083 enum i40iw_status_code status = 0;
1084
1085 cqp_request = i40iw_get_cqp_request(iwcqp, true);
1086 if (!cqp_request) {
1087 i40iw_pr_err("cqp_request memory failed\n");
1088 return I40IW_ERR_NO_MEMORY;
1089 }
1090
1091 cqp_info = &cqp_request->info;
1092
1093 cqp_info->post_sq = 1;
1094 info = &cqp_info->in.u.add_local_mac_ipaddr_entry.info;
1095 ether_addr_copy(info->mac_addr, mac_addr);
1096 info->entry_idx = idx;
1097 cqp_info->in.u.add_local_mac_ipaddr_entry.scratch = (uintptr_t)cqp_request;
1098 cqp_info->cqp_cmd = OP_ADD_LOCAL_MAC_IPADDR_ENTRY;
1099 cqp_info->in.u.add_local_mac_ipaddr_entry.cqp = &iwcqp->sc_cqp;
1100 cqp_info->in.u.add_local_mac_ipaddr_entry.scratch = (uintptr_t)cqp_request;
1101 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1102 if (status)
1103 i40iw_pr_err("CQP-OP Add MAC Ip entry fail");
1104 return status;
1105}
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116static enum i40iw_status_code i40iw_alloc_local_mac_ipaddr_entry(struct i40iw_device *iwdev,
1117 u16 *mac_ip_tbl_idx)
1118{
1119 struct i40iw_cqp *iwcqp = &iwdev->cqp;
1120 struct i40iw_cqp_request *cqp_request;
1121 struct cqp_commands_info *cqp_info;
1122 enum i40iw_status_code status = 0;
1123
1124 cqp_request = i40iw_get_cqp_request(iwcqp, true);
1125 if (!cqp_request) {
1126 i40iw_pr_err("cqp_request memory failed\n");
1127 return I40IW_ERR_NO_MEMORY;
1128 }
1129
1130
1131 atomic_inc(&cqp_request->refcount);
1132
1133 cqp_info = &cqp_request->info;
1134 cqp_info->cqp_cmd = OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY;
1135 cqp_info->post_sq = 1;
1136 cqp_info->in.u.alloc_local_mac_ipaddr_entry.cqp = &iwcqp->sc_cqp;
1137 cqp_info->in.u.alloc_local_mac_ipaddr_entry.scratch = (uintptr_t)cqp_request;
1138 status = i40iw_handle_cqp_op(iwdev, cqp_request);
1139 if (!status)
1140 *mac_ip_tbl_idx = cqp_request->compl_info.op_ret_val;
1141 else
1142 i40iw_pr_err("CQP-OP Alloc MAC Ip entry fail");
1143
1144 i40iw_put_cqp_request(iwcqp, cqp_request);
1145 return status;
1146}
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156static enum i40iw_status_code i40iw_alloc_set_mac_ipaddr(struct i40iw_device *iwdev,
1157 u8 *macaddr)
1158{
1159 enum i40iw_status_code status;
1160
1161 status = i40iw_alloc_local_mac_ipaddr_entry(iwdev, &iwdev->mac_ip_table_idx);
1162 if (!status) {
1163 status = i40iw_add_mac_ipaddr_entry(iwdev, macaddr,
1164 (u8)iwdev->mac_ip_table_idx);
1165 if (status)
1166 i40iw_del_macip_entry(iwdev, (u8)iwdev->mac_ip_table_idx);
1167 }
1168 return status;
1169}
1170
1171
1172
1173
1174
1175static void i40iw_add_ipv6_addr(struct i40iw_device *iwdev)
1176{
1177 struct net_device *ip_dev;
1178 struct inet6_dev *idev;
1179 struct inet6_ifaddr *ifp, *tmp;
1180 u32 local_ipaddr6[4];
1181
1182 rcu_read_lock();
1183 for_each_netdev_rcu(&init_net, ip_dev) {
1184 if ((((rdma_vlan_dev_vlan_id(ip_dev) < 0xFFFF) &&
1185 (rdma_vlan_dev_real_dev(ip_dev) == iwdev->netdev)) ||
1186 (ip_dev == iwdev->netdev)) && (ip_dev->flags & IFF_UP)) {
1187 idev = __in6_dev_get(ip_dev);
1188 if (!idev) {
1189 i40iw_pr_err("ipv6 inet device not found\n");
1190 break;
1191 }
1192 list_for_each_entry_safe(ifp, tmp, &idev->addr_list, if_list) {
1193 i40iw_pr_info("IP=%pI6, vlan_id=%d, MAC=%pM\n", &ifp->addr,
1194 rdma_vlan_dev_vlan_id(ip_dev), ip_dev->dev_addr);
1195 i40iw_copy_ip_ntohl(local_ipaddr6,
1196 ifp->addr.in6_u.u6_addr32);
1197 i40iw_manage_arp_cache(iwdev,
1198 ip_dev->dev_addr,
1199 local_ipaddr6,
1200 false,
1201 I40IW_ARP_ADD);
1202 }
1203 }
1204 }
1205 rcu_read_unlock();
1206}
1207
1208
1209
1210
1211
1212static void i40iw_add_ipv4_addr(struct i40iw_device *iwdev)
1213{
1214 struct net_device *dev;
1215 struct in_device *idev;
1216 bool got_lock = true;
1217 u32 ip_addr;
1218
1219 if (!rtnl_trylock())
1220 got_lock = false;
1221
1222 for_each_netdev(&init_net, dev) {
1223 if ((((rdma_vlan_dev_vlan_id(dev) < 0xFFFF) &&
1224 (rdma_vlan_dev_real_dev(dev) == iwdev->netdev)) ||
1225 (dev == iwdev->netdev)) && (dev->flags & IFF_UP)) {
1226 idev = in_dev_get(dev);
1227 for_ifa(idev) {
1228 i40iw_debug(&iwdev->sc_dev, I40IW_DEBUG_CM,
1229 "IP=%pI4, vlan_id=%d, MAC=%pM\n", &ifa->ifa_address,
1230 rdma_vlan_dev_vlan_id(dev), dev->dev_addr);
1231
1232 ip_addr = ntohl(ifa->ifa_address);
1233 i40iw_manage_arp_cache(iwdev,
1234 dev->dev_addr,
1235 &ip_addr,
1236 true,
1237 I40IW_ARP_ADD);
1238 }
1239 endfor_ifa(idev);
1240 in_dev_put(idev);
1241 }
1242 }
1243 if (got_lock)
1244 rtnl_unlock();
1245}
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255static enum i40iw_status_code i40iw_add_mac_ip(struct i40iw_device *iwdev)
1256{
1257 struct net_device *netdev = iwdev->netdev;
1258 enum i40iw_status_code status;
1259
1260 status = i40iw_alloc_set_mac_ipaddr(iwdev, (u8 *)netdev->dev_addr);
1261 if (status)
1262 return status;
1263 i40iw_add_ipv4_addr(iwdev);
1264 i40iw_add_ipv6_addr(iwdev);
1265 return 0;
1266}
1267
1268
1269
1270
1271
1272static void i40iw_wait_pe_ready(struct i40iw_hw *hw)
1273{
1274 u32 statusfw;
1275 u32 statuscpu0;
1276 u32 statuscpu1;
1277 u32 statuscpu2;
1278 u32 retrycount = 0;
1279
1280 do {
1281 statusfw = i40iw_rd32(hw, I40E_GLPE_FWLDSTATUS);
1282 i40iw_pr_info("[%04d] fm load status[x%04X]\n", __LINE__, statusfw);
1283 statuscpu0 = i40iw_rd32(hw, I40E_GLPE_CPUSTATUS0);
1284 i40iw_pr_info("[%04d] CSR_CQP status[x%04X]\n", __LINE__, statuscpu0);
1285 statuscpu1 = i40iw_rd32(hw, I40E_GLPE_CPUSTATUS1);
1286 i40iw_pr_info("[%04d] I40E_GLPE_CPUSTATUS1 status[x%04X]\n",
1287 __LINE__, statuscpu1);
1288 statuscpu2 = i40iw_rd32(hw, I40E_GLPE_CPUSTATUS2);
1289 i40iw_pr_info("[%04d] I40E_GLPE_CPUSTATUS2 status[x%04X]\n",
1290 __LINE__, statuscpu2);
1291 if ((statuscpu0 == 0x80) && (statuscpu1 == 0x80) && (statuscpu2 == 0x80))
1292 break;
1293 msleep(1000);
1294 retrycount++;
1295 } while (retrycount < 14);
1296 i40iw_wr32(hw, 0xb4040, 0x4C104C5);
1297}
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308static enum i40iw_status_code i40iw_initialize_dev(struct i40iw_device *iwdev,
1309 struct i40e_info *ldev)
1310{
1311 enum i40iw_status_code status;
1312 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1313 struct i40iw_device_init_info info;
1314 struct i40iw_vsi_init_info vsi_info;
1315 struct i40iw_dma_mem mem;
1316 struct i40iw_l2params l2params;
1317 u32 size;
1318 struct i40iw_vsi_stats_info stats_info;
1319 u16 last_qset = I40IW_NO_QSET;
1320 u16 qset;
1321 u32 i;
1322
1323 memset(&l2params, 0, sizeof(l2params));
1324 memset(&info, 0, sizeof(info));
1325 size = sizeof(struct i40iw_hmc_pble_rsrc) + sizeof(struct i40iw_hmc_info) +
1326 (sizeof(struct i40iw_hmc_obj_info) * I40IW_HMC_IW_MAX);
1327 iwdev->hmc_info_mem = kzalloc(size, GFP_KERNEL);
1328 if (!iwdev->hmc_info_mem)
1329 return I40IW_ERR_NO_MEMORY;
1330
1331 iwdev->pble_rsrc = (struct i40iw_hmc_pble_rsrc *)iwdev->hmc_info_mem;
1332 dev->hmc_info = &iwdev->hw.hmc;
1333 dev->hmc_info->hmc_obj = (struct i40iw_hmc_obj_info *)(iwdev->pble_rsrc + 1);
1334 status = i40iw_obj_aligned_mem(iwdev, &mem, I40IW_QUERY_FPM_BUF_SIZE,
1335 I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK);
1336 if (status)
1337 goto error;
1338 info.fpm_query_buf_pa = mem.pa;
1339 info.fpm_query_buf = mem.va;
1340 status = i40iw_obj_aligned_mem(iwdev, &mem, I40IW_COMMIT_FPM_BUF_SIZE,
1341 I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK);
1342 if (status)
1343 goto error;
1344 info.fpm_commit_buf_pa = mem.pa;
1345 info.fpm_commit_buf = mem.va;
1346 info.hmc_fn_id = ldev->fid;
1347 info.is_pf = (ldev->ftype) ? false : true;
1348 info.bar0 = ldev->hw_addr;
1349 info.hw = &iwdev->hw;
1350 info.debug_mask = debug;
1351 l2params.mtu =
1352 (ldev->params.mtu) ? ldev->params.mtu : I40IW_DEFAULT_MTU;
1353 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++) {
1354 qset = ldev->params.qos.prio_qos[i].qs_handle;
1355 l2params.qs_handle_list[i] = qset;
1356 if (last_qset == I40IW_NO_QSET)
1357 last_qset = qset;
1358 else if ((qset != last_qset) && (qset != I40IW_NO_QSET))
1359 iwdev->dcb = true;
1360 }
1361 i40iw_pr_info("DCB is set/clear = %d\n", iwdev->dcb);
1362 info.vchnl_send = i40iw_virtchnl_send;
1363 status = i40iw_device_init(&iwdev->sc_dev, &info);
1364
1365 if (status)
1366 goto error;
1367 memset(&vsi_info, 0, sizeof(vsi_info));
1368 vsi_info.dev = &iwdev->sc_dev;
1369 vsi_info.back_vsi = (void *)iwdev;
1370 vsi_info.params = &l2params;
1371 vsi_info.exception_lan_queue = 1;
1372 i40iw_sc_vsi_init(&iwdev->vsi, &vsi_info);
1373
1374 if (dev->is_pf) {
1375 memset(&stats_info, 0, sizeof(stats_info));
1376 stats_info.fcn_id = ldev->fid;
1377 stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL);
1378 if (!stats_info.pestat) {
1379 status = I40IW_ERR_NO_MEMORY;
1380 goto error;
1381 }
1382 stats_info.stats_initialize = true;
1383 if (stats_info.pestat)
1384 i40iw_vsi_stats_init(&iwdev->vsi, &stats_info);
1385 }
1386 return status;
1387error:
1388 kfree(iwdev->hmc_info_mem);
1389 iwdev->hmc_info_mem = NULL;
1390 return status;
1391}
1392
1393
1394
1395
1396static void i40iw_register_notifiers(void)
1397{
1398 register_inetaddr_notifier(&i40iw_inetaddr_notifier);
1399 register_inet6addr_notifier(&i40iw_inetaddr6_notifier);
1400 register_netevent_notifier(&i40iw_net_notifier);
1401 register_netdevice_notifier(&i40iw_netdevice_notifier);
1402}
1403
1404
1405
1406
1407
1408static void i40iw_unregister_notifiers(void)
1409{
1410 unregister_netevent_notifier(&i40iw_net_notifier);
1411 unregister_inetaddr_notifier(&i40iw_inetaddr_notifier);
1412 unregister_inet6addr_notifier(&i40iw_inetaddr6_notifier);
1413 unregister_netdevice_notifier(&i40iw_netdevice_notifier);
1414}
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424static enum i40iw_status_code i40iw_save_msix_info(struct i40iw_device *iwdev,
1425 struct i40e_info *ldev)
1426{
1427 struct i40e_qvlist_info *iw_qvlist;
1428 struct i40e_qv_info *iw_qvinfo;
1429 u32 ceq_idx;
1430 u32 i;
1431 u32 size;
1432
1433 if (!ldev->msix_count) {
1434 i40iw_pr_err("No MSI-X vectors\n");
1435 return I40IW_ERR_CONFIG;
1436 }
1437
1438 iwdev->msix_count = ldev->msix_count;
1439
1440 size = sizeof(struct i40iw_msix_vector) * iwdev->msix_count;
1441 size += sizeof(struct i40e_qvlist_info);
1442 size += sizeof(struct i40e_qv_info) * iwdev->msix_count - 1;
1443 iwdev->iw_msixtbl = kzalloc(size, GFP_KERNEL);
1444
1445 if (!iwdev->iw_msixtbl)
1446 return I40IW_ERR_NO_MEMORY;
1447 iwdev->iw_qvlist = (struct i40e_qvlist_info *)(&iwdev->iw_msixtbl[iwdev->msix_count]);
1448 iw_qvlist = iwdev->iw_qvlist;
1449 iw_qvinfo = iw_qvlist->qv_info;
1450 iw_qvlist->num_vectors = iwdev->msix_count;
1451 if (iwdev->msix_count <= num_online_cpus())
1452 iwdev->msix_shared = true;
1453 for (i = 0, ceq_idx = 0; i < iwdev->msix_count; i++, iw_qvinfo++) {
1454 iwdev->iw_msixtbl[i].idx = ldev->msix_entries[i].entry;
1455 iwdev->iw_msixtbl[i].irq = ldev->msix_entries[i].vector;
1456 iwdev->iw_msixtbl[i].cpu_affinity = ceq_idx;
1457 if (i == 0) {
1458 iw_qvinfo->aeq_idx = 0;
1459 if (iwdev->msix_shared)
1460 iw_qvinfo->ceq_idx = ceq_idx++;
1461 else
1462 iw_qvinfo->ceq_idx = I40E_QUEUE_INVALID_IDX;
1463 } else {
1464 iw_qvinfo->aeq_idx = I40E_QUEUE_INVALID_IDX;
1465 iw_qvinfo->ceq_idx = ceq_idx++;
1466 }
1467 iw_qvinfo->itr_idx = 3;
1468 iw_qvinfo->v_idx = iwdev->iw_msixtbl[i].idx;
1469 }
1470 return 0;
1471}
1472
1473
1474
1475
1476
1477
1478
1479
1480static void i40iw_deinit_device(struct i40iw_device *iwdev)
1481{
1482 struct i40e_info *ldev = iwdev->ldev;
1483
1484 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1485
1486 i40iw_pr_info("state = %d\n", iwdev->init_state);
1487 if (iwdev->param_wq)
1488 destroy_workqueue(iwdev->param_wq);
1489
1490 switch (iwdev->init_state) {
1491 case RDMA_DEV_REGISTERED:
1492 iwdev->iw_status = 0;
1493 i40iw_port_ibevent(iwdev);
1494 i40iw_destroy_rdma_device(iwdev->iwibdev);
1495
1496 case IP_ADDR_REGISTERED:
1497 if (!iwdev->reset)
1498 i40iw_del_macip_entry(iwdev, (u8)iwdev->mac_ip_table_idx);
1499
1500
1501 case PBLE_CHUNK_MEM:
1502 i40iw_destroy_pble_pool(dev, iwdev->pble_rsrc);
1503
1504 case CEQ_CREATED:
1505 i40iw_dele_ceqs(iwdev);
1506
1507 case AEQ_CREATED:
1508 i40iw_destroy_aeq(iwdev);
1509
1510 case IEQ_CREATED:
1511 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_IEQ, iwdev->reset);
1512
1513 case ILQ_CREATED:
1514 i40iw_puda_dele_resources(&iwdev->vsi, I40IW_PUDA_RSRC_TYPE_ILQ, iwdev->reset);
1515
1516 case CCQ_CREATED:
1517 i40iw_destroy_ccq(iwdev);
1518
1519 case HMC_OBJS_CREATED:
1520 i40iw_del_hmc_objects(dev, dev->hmc_info, true, iwdev->reset);
1521
1522 case CQP_CREATED:
1523 i40iw_destroy_cqp(iwdev, true);
1524
1525 case INITIAL_STATE:
1526 i40iw_cleanup_cm_core(&iwdev->cm_core);
1527 if (iwdev->vsi.pestat) {
1528 i40iw_vsi_stats_free(&iwdev->vsi);
1529 kfree(iwdev->vsi.pestat);
1530 }
1531 i40iw_del_init_mem(iwdev);
1532 break;
1533 case INVALID_STATE:
1534
1535 default:
1536 i40iw_pr_err("bad init_state = %d\n", iwdev->init_state);
1537 break;
1538 }
1539
1540 i40iw_del_handler(i40iw_find_i40e_handler(ldev));
1541 kfree(iwdev->hdl);
1542}
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554static enum i40iw_status_code i40iw_setup_init_state(struct i40iw_handler *hdl,
1555 struct i40e_info *ldev,
1556 struct i40e_client *client)
1557{
1558 struct i40iw_device *iwdev = &hdl->device;
1559 struct i40iw_sc_dev *dev = &iwdev->sc_dev;
1560 enum i40iw_status_code status;
1561
1562 memcpy(&hdl->ldev, ldev, sizeof(*ldev));
1563 if (resource_profile == 1)
1564 resource_profile = 2;
1565
1566 iwdev->mpa_version = mpa_version;
1567 iwdev->resource_profile = (resource_profile < I40IW_HMC_PROFILE_EQUAL) ?
1568 (u8)resource_profile + I40IW_HMC_PROFILE_DEFAULT :
1569 I40IW_HMC_PROFILE_DEFAULT;
1570 iwdev->max_rdma_vfs =
1571 (iwdev->resource_profile != I40IW_HMC_PROFILE_DEFAULT) ? max_rdma_vfs : 0;
1572 iwdev->max_enabled_vfs = iwdev->max_rdma_vfs;
1573 iwdev->netdev = ldev->netdev;
1574 hdl->client = client;
1575 if (!ldev->ftype)
1576 iwdev->db_start = pci_resource_start(ldev->pcidev, 0) + I40IW_DB_ADDR_OFFSET;
1577 else
1578 iwdev->db_start = pci_resource_start(ldev->pcidev, 0) + I40IW_VF_DB_ADDR_OFFSET;
1579
1580 status = i40iw_save_msix_info(iwdev, ldev);
1581 if (status)
1582 return status;
1583 iwdev->hw.dev_context = (void *)ldev->pcidev;
1584 iwdev->hw.hw_addr = ldev->hw_addr;
1585 status = i40iw_allocate_dma_mem(&iwdev->hw,
1586 &iwdev->obj_mem, 8192, 4096);
1587 if (status)
1588 goto exit;
1589 iwdev->obj_next = iwdev->obj_mem;
1590 iwdev->push_mode = push_mode;
1591
1592 init_waitqueue_head(&iwdev->vchnl_waitq);
1593 init_waitqueue_head(&dev->vf_reqs);
1594 init_waitqueue_head(&iwdev->close_wq);
1595
1596 status = i40iw_initialize_dev(iwdev, ldev);
1597exit:
1598 if (status) {
1599 kfree(iwdev->iw_msixtbl);
1600 i40iw_free_dma_mem(dev->hw, &iwdev->obj_mem);
1601 iwdev->iw_msixtbl = NULL;
1602 }
1603 return status;
1604}
1605
1606
1607
1608
1609
1610
1611
1612static void i40iw_get_used_rsrc(struct i40iw_device *iwdev)
1613{
1614 iwdev->used_pds = find_next_zero_bit(iwdev->allocated_pds, iwdev->max_pd, 0);
1615 iwdev->used_qps = find_next_zero_bit(iwdev->allocated_qps, iwdev->max_qp, 0);
1616 iwdev->used_cqs = find_next_zero_bit(iwdev->allocated_cqs, iwdev->max_cq, 0);
1617 iwdev->used_mrs = find_next_zero_bit(iwdev->allocated_mrs, iwdev->max_mr, 0);
1618}
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630static int i40iw_open(struct i40e_info *ldev, struct i40e_client *client)
1631{
1632 struct i40iw_device *iwdev;
1633 struct i40iw_sc_dev *dev;
1634 enum i40iw_status_code status;
1635 struct i40iw_handler *hdl;
1636
1637 hdl = i40iw_find_netdev(ldev->netdev);
1638 if (hdl)
1639 return 0;
1640
1641 hdl = kzalloc(sizeof(*hdl), GFP_KERNEL);
1642 if (!hdl)
1643 return -ENOMEM;
1644 iwdev = &hdl->device;
1645 iwdev->hdl = hdl;
1646 dev = &iwdev->sc_dev;
1647 i40iw_setup_cm_core(iwdev);
1648
1649 dev->back_dev = (void *)iwdev;
1650 iwdev->ldev = &hdl->ldev;
1651 iwdev->client = client;
1652 mutex_init(&iwdev->pbl_mutex);
1653 i40iw_add_handler(hdl);
1654
1655 do {
1656 status = i40iw_setup_init_state(hdl, ldev, client);
1657 if (status)
1658 break;
1659 iwdev->init_state = INITIAL_STATE;
1660 if (dev->is_pf)
1661 i40iw_wait_pe_ready(dev->hw);
1662 status = i40iw_create_cqp(iwdev);
1663 if (status)
1664 break;
1665 iwdev->init_state = CQP_CREATED;
1666 status = i40iw_hmc_setup(iwdev);
1667 if (status)
1668 break;
1669 status = i40iw_create_ccq(iwdev);
1670 if (status)
1671 break;
1672 iwdev->init_state = CCQ_CREATED;
1673 status = i40iw_initialize_ilq(iwdev);
1674 if (status)
1675 break;
1676 iwdev->init_state = ILQ_CREATED;
1677 status = i40iw_initialize_ieq(iwdev);
1678 if (status)
1679 break;
1680 iwdev->init_state = IEQ_CREATED;
1681 status = i40iw_setup_aeq(iwdev);
1682 if (status)
1683 break;
1684 iwdev->init_state = AEQ_CREATED;
1685 status = i40iw_setup_ceqs(iwdev, ldev);
1686 if (status)
1687 break;
1688 iwdev->init_state = CEQ_CREATED;
1689 status = i40iw_initialize_hw_resources(iwdev);
1690 if (status)
1691 break;
1692 i40iw_get_used_rsrc(iwdev);
1693 dev->ccq_ops->ccq_arm(dev->ccq);
1694 status = i40iw_hmc_init_pble(&iwdev->sc_dev, iwdev->pble_rsrc);
1695 if (status)
1696 break;
1697 iwdev->init_state = PBLE_CHUNK_MEM;
1698 iwdev->virtchnl_wq = alloc_ordered_workqueue("iwvch", WQ_MEM_RECLAIM);
1699 status = i40iw_add_mac_ip(iwdev);
1700 if (status)
1701 break;
1702 iwdev->init_state = IP_ADDR_REGISTERED;
1703 if (i40iw_register_rdma_device(iwdev)) {
1704 i40iw_pr_err("register rdma device fail\n");
1705 break;
1706 };
1707
1708 iwdev->init_state = RDMA_DEV_REGISTERED;
1709 iwdev->iw_status = 1;
1710 i40iw_port_ibevent(iwdev);
1711 iwdev->param_wq = alloc_ordered_workqueue("l2params", WQ_MEM_RECLAIM);
1712 if(iwdev->param_wq == NULL)
1713 break;
1714 i40iw_pr_info("i40iw_open completed\n");
1715 return 0;
1716 } while (0);
1717
1718 i40iw_pr_err("status = %d last completion = %d\n", status, iwdev->init_state);
1719 i40iw_deinit_device(iwdev);
1720 return -ERESTART;
1721}
1722
1723
1724
1725
1726
1727static void i40iw_l2params_worker(struct work_struct *work)
1728{
1729 struct l2params_work *dwork =
1730 container_of(work, struct l2params_work, work);
1731 struct i40iw_device *iwdev = dwork->iwdev;
1732
1733 i40iw_change_l2params(&iwdev->vsi, &dwork->l2params);
1734 atomic_dec(&iwdev->params_busy);
1735 kfree(work);
1736}
1737
1738
1739
1740
1741
1742
1743
1744static void i40iw_l2param_change(struct i40e_info *ldev, struct i40e_client *client,
1745 struct i40e_params *params)
1746{
1747 struct i40iw_handler *hdl;
1748 struct i40iw_l2params *l2params;
1749 struct l2params_work *work;
1750 struct i40iw_device *iwdev;
1751 int i;
1752
1753 hdl = i40iw_find_i40e_handler(ldev);
1754 if (!hdl)
1755 return;
1756
1757 iwdev = &hdl->device;
1758
1759 if (atomic_read(&iwdev->params_busy))
1760 return;
1761
1762
1763 work = kzalloc(sizeof(*work), GFP_ATOMIC);
1764 if (!work)
1765 return;
1766
1767 atomic_inc(&iwdev->params_busy);
1768
1769 work->iwdev = iwdev;
1770 l2params = &work->l2params;
1771 for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++)
1772 l2params->qs_handle_list[i] = params->qos.prio_qos[i].qs_handle;
1773
1774 l2params->mtu = (params->mtu) ? params->mtu : iwdev->vsi.mtu;
1775
1776 INIT_WORK(&work->work, i40iw_l2params_worker);
1777 queue_work(iwdev->param_wq, &work->work);
1778}
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788static void i40iw_close(struct i40e_info *ldev, struct i40e_client *client, bool reset)
1789{
1790 struct i40iw_device *iwdev;
1791 struct i40iw_handler *hdl;
1792
1793 hdl = i40iw_find_i40e_handler(ldev);
1794 if (!hdl)
1795 return;
1796
1797 iwdev = &hdl->device;
1798 iwdev->closing = true;
1799
1800 if (reset)
1801 iwdev->reset = true;
1802
1803 i40iw_cm_teardown_connections(iwdev, NULL, NULL, true);
1804 destroy_workqueue(iwdev->virtchnl_wq);
1805 i40iw_deinit_device(iwdev);
1806}
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817static void i40iw_vf_reset(struct i40e_info *ldev, struct i40e_client *client, u32 vf_id)
1818{
1819 struct i40iw_handler *hdl;
1820 struct i40iw_sc_dev *dev;
1821 struct i40iw_hmc_fcn_info hmc_fcn_info;
1822 struct i40iw_virt_mem vf_dev_mem;
1823 struct i40iw_vfdev *tmp_vfdev;
1824 unsigned int i;
1825 unsigned long flags;
1826 struct i40iw_device *iwdev;
1827
1828 hdl = i40iw_find_i40e_handler(ldev);
1829 if (!hdl)
1830 return;
1831
1832 dev = &hdl->device.sc_dev;
1833 iwdev = (struct i40iw_device *)dev->back_dev;
1834
1835 for (i = 0; i < I40IW_MAX_PE_ENABLED_VF_COUNT; i++) {
1836 if (!dev->vf_dev[i] || (dev->vf_dev[i]->vf_id != vf_id))
1837 continue;
1838
1839 tmp_vfdev = dev->vf_dev[i];
1840 spin_lock_irqsave(&iwdev->vsi.pestat->lock, flags);
1841 dev->vf_dev[i] = NULL;
1842 spin_unlock_irqrestore(&iwdev->vsi.pestat->lock, flags);
1843 i40iw_del_hmc_objects(dev, &tmp_vfdev->hmc_info, false, false);
1844
1845 memset(&hmc_fcn_info, 0, sizeof(hmc_fcn_info));
1846 hmc_fcn_info.vf_id = vf_id;
1847 hmc_fcn_info.iw_vf_idx = tmp_vfdev->iw_vf_idx;
1848 hmc_fcn_info.free_fcn = true;
1849 i40iw_cqp_manage_hmc_fcn_cmd(dev, &hmc_fcn_info);
1850
1851 vf_dev_mem.va = tmp_vfdev;
1852 vf_dev_mem.size = sizeof(struct i40iw_vfdev) +
1853 sizeof(struct i40iw_hmc_obj_info) * I40IW_HMC_IW_MAX;
1854 i40iw_free_virt_mem(dev->hw, &vf_dev_mem);
1855 break;
1856 }
1857}
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867static void i40iw_vf_enable(struct i40e_info *ldev,
1868 struct i40e_client *client,
1869 u32 num_vfs)
1870{
1871 struct i40iw_handler *hdl;
1872
1873 hdl = i40iw_find_i40e_handler(ldev);
1874 if (!hdl)
1875 return;
1876
1877 if (num_vfs > I40IW_MAX_PE_ENABLED_VF_COUNT)
1878 hdl->device.max_enabled_vfs = I40IW_MAX_PE_ENABLED_VF_COUNT;
1879 else
1880 hdl->device.max_enabled_vfs = num_vfs;
1881}
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892static int i40iw_vf_capable(struct i40e_info *ldev,
1893 struct i40e_client *client,
1894 u32 vf_id)
1895{
1896 struct i40iw_handler *hdl;
1897 struct i40iw_sc_dev *dev;
1898 unsigned int i;
1899
1900 hdl = i40iw_find_i40e_handler(ldev);
1901 if (!hdl)
1902 return 0;
1903
1904 dev = &hdl->device.sc_dev;
1905
1906 for (i = 0; i < hdl->device.max_enabled_vfs; i++) {
1907 if (!dev->vf_dev[i] || (dev->vf_dev[i]->vf_id == vf_id))
1908 return 1;
1909 }
1910
1911 return 0;
1912}
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925static int i40iw_virtchnl_receive(struct i40e_info *ldev,
1926 struct i40e_client *client,
1927 u32 vf_id,
1928 u8 *msg,
1929 u16 len)
1930{
1931 struct i40iw_handler *hdl;
1932 struct i40iw_sc_dev *dev;
1933 struct i40iw_device *iwdev;
1934 int ret_code = I40IW_NOT_SUPPORTED;
1935
1936 if (!len || !msg)
1937 return I40IW_ERR_PARAM;
1938
1939 hdl = i40iw_find_i40e_handler(ldev);
1940 if (!hdl)
1941 return I40IW_ERR_PARAM;
1942
1943 dev = &hdl->device.sc_dev;
1944 iwdev = dev->back_dev;
1945
1946 if (dev->vchnl_if.vchnl_recv) {
1947 ret_code = dev->vchnl_if.vchnl_recv(dev, vf_id, msg, len);
1948 if (!dev->is_pf) {
1949 atomic_dec(&iwdev->vchnl_msgs);
1950 wake_up(&iwdev->vchnl_waitq);
1951 }
1952 }
1953 return ret_code;
1954}
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965bool i40iw_vf_clear_to_send(struct i40iw_sc_dev *dev)
1966{
1967 struct i40iw_device *iwdev;
1968 wait_queue_entry_t wait;
1969
1970 iwdev = dev->back_dev;
1971
1972 if (!wq_has_sleeper(&dev->vf_reqs) &&
1973 (atomic_read(&iwdev->vchnl_msgs) == 0))
1974 return true;
1975
1976 init_wait(&wait);
1977 add_wait_queue_exclusive(&dev->vf_reqs, &wait);
1978
1979 if (!wait_event_timeout(dev->vf_reqs,
1980 (atomic_read(&iwdev->vchnl_msgs) == 0),
1981 I40IW_VCHNL_EVENT_TIMEOUT))
1982 dev->vchnl_up = false;
1983
1984 remove_wait_queue(&dev->vf_reqs, &wait);
1985
1986 return dev->vchnl_up;
1987}
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999static enum i40iw_status_code i40iw_virtchnl_send(struct i40iw_sc_dev *dev,
2000 u32 vf_id,
2001 u8 *msg,
2002 u16 len)
2003{
2004 struct i40iw_device *iwdev;
2005 struct i40e_info *ldev;
2006
2007 if (!dev || !dev->back_dev)
2008 return I40IW_ERR_BAD_PTR;
2009
2010 iwdev = dev->back_dev;
2011 ldev = iwdev->ldev;
2012
2013 if (ldev && ldev->ops && ldev->ops->virtchnl_send)
2014 return ldev->ops->virtchnl_send(ldev, &i40iw_client, vf_id, msg, len);
2015 return I40IW_ERR_BAD_PTR;
2016}
2017
2018
2019static const struct i40e_client_ops i40e_ops = {
2020 .open = i40iw_open,
2021 .close = i40iw_close,
2022 .l2_param_change = i40iw_l2param_change,
2023 .virtchnl_receive = i40iw_virtchnl_receive,
2024 .vf_reset = i40iw_vf_reset,
2025 .vf_enable = i40iw_vf_enable,
2026 .vf_capable = i40iw_vf_capable
2027};
2028
2029
2030
2031
2032
2033
2034
2035static int __init i40iw_init_module(void)
2036{
2037 int ret;
2038
2039 memset(&i40iw_client, 0, sizeof(i40iw_client));
2040 i40iw_client.version.major = CLIENT_IW_INTERFACE_VERSION_MAJOR;
2041 i40iw_client.version.minor = CLIENT_IW_INTERFACE_VERSION_MINOR;
2042 i40iw_client.version.build = CLIENT_IW_INTERFACE_VERSION_BUILD;
2043 i40iw_client.ops = &i40e_ops;
2044 memcpy(i40iw_client.name, i40iw_client_name, I40E_CLIENT_STR_LENGTH);
2045 i40iw_client.type = I40E_CLIENT_IWARP;
2046 spin_lock_init(&i40iw_handler_lock);
2047 ret = i40e_register_client(&i40iw_client);
2048 i40iw_register_notifiers();
2049
2050 return ret;
2051}
2052
2053
2054
2055
2056
2057
2058
2059static void __exit i40iw_exit_module(void)
2060{
2061 i40iw_unregister_notifiers();
2062 i40e_unregister_client(&i40iw_client);
2063}
2064
2065module_init(i40iw_init_module);
2066module_exit(i40iw_exit_module);
2067