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33#include <linux/kref.h>
34#include <rdma/ib_umem.h>
35#include <rdma/ib_user_verbs.h>
36#include <rdma/ib_cache.h>
37#include "mlx5_ib.h"
38
39static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq)
40{
41 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
42
43 ibcq->comp_handler(ibcq, ibcq->cq_context);
44}
45
46static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
47{
48 struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
49 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
50 struct ib_cq *ibcq = &cq->ibcq;
51 struct ib_event event;
52
53 if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
54 mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
55 type, mcq->cqn);
56 return;
57 }
58
59 if (ibcq->event_handler) {
60 event.device = &dev->ib_dev;
61 event.event = IB_EVENT_CQ_ERR;
62 event.element.cq = ibcq;
63 ibcq->event_handler(&event, ibcq->cq_context);
64 }
65}
66
67static void *get_cqe_from_buf(struct mlx5_ib_cq_buf *buf, int n, int size)
68{
69 return mlx5_buf_offset(&buf->buf, n * size);
70}
71
72static void *get_cqe(struct mlx5_ib_cq *cq, int n)
73{
74 return get_cqe_from_buf(&cq->buf, n, cq->mcq.cqe_sz);
75}
76
77static u8 sw_ownership_bit(int n, int nent)
78{
79 return (n & nent) ? 1 : 0;
80}
81
82static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
83{
84 void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
85 struct mlx5_cqe64 *cqe64;
86
87 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
88
89 if (likely((cqe64->op_own) >> 4 != MLX5_CQE_INVALID) &&
90 !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
91 return cqe;
92 } else {
93 return NULL;
94 }
95}
96
97static void *next_cqe_sw(struct mlx5_ib_cq *cq)
98{
99 return get_sw_cqe(cq, cq->mcq.cons_index);
100}
101
102static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
103{
104 switch (wq->wr_data[idx]) {
105 case MLX5_IB_WR_UMR:
106 return 0;
107
108 case IB_WR_LOCAL_INV:
109 return IB_WC_LOCAL_INV;
110
111 case IB_WR_REG_MR:
112 return IB_WC_REG_MR;
113
114 default:
115 pr_warn("unknown completion status\n");
116 return 0;
117 }
118}
119
120static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
121 struct mlx5_ib_wq *wq, int idx)
122{
123 wc->wc_flags = 0;
124 switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
125 case MLX5_OPCODE_RDMA_WRITE_IMM:
126 wc->wc_flags |= IB_WC_WITH_IMM;
127
128 case MLX5_OPCODE_RDMA_WRITE:
129 wc->opcode = IB_WC_RDMA_WRITE;
130 break;
131 case MLX5_OPCODE_SEND_IMM:
132 wc->wc_flags |= IB_WC_WITH_IMM;
133
134 case MLX5_OPCODE_SEND:
135 case MLX5_OPCODE_SEND_INVAL:
136 wc->opcode = IB_WC_SEND;
137 break;
138 case MLX5_OPCODE_RDMA_READ:
139 wc->opcode = IB_WC_RDMA_READ;
140 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
141 break;
142 case MLX5_OPCODE_ATOMIC_CS:
143 wc->opcode = IB_WC_COMP_SWAP;
144 wc->byte_len = 8;
145 break;
146 case MLX5_OPCODE_ATOMIC_FA:
147 wc->opcode = IB_WC_FETCH_ADD;
148 wc->byte_len = 8;
149 break;
150 case MLX5_OPCODE_ATOMIC_MASKED_CS:
151 wc->opcode = IB_WC_MASKED_COMP_SWAP;
152 wc->byte_len = 8;
153 break;
154 case MLX5_OPCODE_ATOMIC_MASKED_FA:
155 wc->opcode = IB_WC_MASKED_FETCH_ADD;
156 wc->byte_len = 8;
157 break;
158 case MLX5_OPCODE_UMR:
159 wc->opcode = get_umr_comp(wq, idx);
160 break;
161 }
162}
163
164enum {
165 MLX5_GRH_IN_BUFFER = 1,
166 MLX5_GRH_IN_CQE = 2,
167};
168
169static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
170 struct mlx5_ib_qp *qp)
171{
172 enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
173 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
174 struct mlx5_ib_srq *srq;
175 struct mlx5_ib_wq *wq;
176 u16 wqe_ctr;
177 u8 roce_packet_type;
178 bool vlan_present;
179 u8 g;
180
181 if (qp->ibqp.srq || qp->ibqp.xrcd) {
182 struct mlx5_core_srq *msrq = NULL;
183
184 if (qp->ibqp.xrcd) {
185 msrq = mlx5_core_get_srq(dev->mdev,
186 be32_to_cpu(cqe->srqn));
187 srq = to_mibsrq(msrq);
188 } else {
189 srq = to_msrq(qp->ibqp.srq);
190 }
191 if (srq) {
192 wqe_ctr = be16_to_cpu(cqe->wqe_counter);
193 wc->wr_id = srq->wrid[wqe_ctr];
194 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
195 if (msrq && atomic_dec_and_test(&msrq->refcount))
196 complete(&msrq->free);
197 }
198 } else {
199 wq = &qp->rq;
200 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
201 ++wq->tail;
202 }
203 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
204
205 switch (cqe->op_own >> 4) {
206 case MLX5_CQE_RESP_WR_IMM:
207 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
208 wc->wc_flags = IB_WC_WITH_IMM;
209 wc->ex.imm_data = cqe->imm_inval_pkey;
210 break;
211 case MLX5_CQE_RESP_SEND:
212 wc->opcode = IB_WC_RECV;
213 wc->wc_flags = IB_WC_IP_CSUM_OK;
214 if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
215 (cqe->hds_ip_ext & CQE_L4_OK))))
216 wc->wc_flags = 0;
217 break;
218 case MLX5_CQE_RESP_SEND_IMM:
219 wc->opcode = IB_WC_RECV;
220 wc->wc_flags = IB_WC_WITH_IMM;
221 wc->ex.imm_data = cqe->imm_inval_pkey;
222 break;
223 case MLX5_CQE_RESP_SEND_INV:
224 wc->opcode = IB_WC_RECV;
225 wc->wc_flags = IB_WC_WITH_INVALIDATE;
226 wc->ex.invalidate_rkey = be32_to_cpu(cqe->imm_inval_pkey);
227 break;
228 }
229 wc->src_qp = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
230 wc->dlid_path_bits = cqe->ml_path;
231 g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
232 wc->wc_flags |= g ? IB_WC_GRH : 0;
233 if (unlikely(is_qp1(qp->ibqp.qp_type))) {
234 u16 pkey = be32_to_cpu(cqe->imm_inval_pkey) & 0xffff;
235
236 ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
237 &wc->pkey_index);
238 } else {
239 wc->pkey_index = 0;
240 }
241
242 if (ll != IB_LINK_LAYER_ETHERNET) {
243 wc->slid = be16_to_cpu(cqe->slid);
244 wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
245 return;
246 }
247
248 wc->slid = 0;
249 vlan_present = cqe->l4_l3_hdr_type & 0x1;
250 roce_packet_type = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
251 if (vlan_present) {
252 wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
253 wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
254 wc->wc_flags |= IB_WC_WITH_VLAN;
255 } else {
256 wc->sl = 0;
257 }
258
259 switch (roce_packet_type) {
260 case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
261 wc->network_hdr_type = RDMA_NETWORK_IB;
262 break;
263 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
264 wc->network_hdr_type = RDMA_NETWORK_IPV6;
265 break;
266 case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
267 wc->network_hdr_type = RDMA_NETWORK_IPV4;
268 break;
269 }
270 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
271}
272
273static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
274{
275 __be32 *p = (__be32 *)cqe;
276 int i;
277
278 mlx5_ib_warn(dev, "dump error cqe\n");
279 for (i = 0; i < sizeof(*cqe) / 16; i++, p += 4)
280 pr_info("%08x %08x %08x %08x\n", be32_to_cpu(p[0]),
281 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
282 be32_to_cpu(p[3]));
283}
284
285static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
286 struct mlx5_err_cqe *cqe,
287 struct ib_wc *wc)
288{
289 int dump = 1;
290
291 switch (cqe->syndrome) {
292 case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
293 wc->status = IB_WC_LOC_LEN_ERR;
294 break;
295 case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
296 wc->status = IB_WC_LOC_QP_OP_ERR;
297 break;
298 case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
299 wc->status = IB_WC_LOC_PROT_ERR;
300 break;
301 case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
302 dump = 0;
303 wc->status = IB_WC_WR_FLUSH_ERR;
304 break;
305 case MLX5_CQE_SYNDROME_MW_BIND_ERR:
306 wc->status = IB_WC_MW_BIND_ERR;
307 break;
308 case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
309 wc->status = IB_WC_BAD_RESP_ERR;
310 break;
311 case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
312 wc->status = IB_WC_LOC_ACCESS_ERR;
313 break;
314 case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
315 wc->status = IB_WC_REM_INV_REQ_ERR;
316 break;
317 case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
318 wc->status = IB_WC_REM_ACCESS_ERR;
319 break;
320 case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
321 wc->status = IB_WC_REM_OP_ERR;
322 break;
323 case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
324 wc->status = IB_WC_RETRY_EXC_ERR;
325 dump = 0;
326 break;
327 case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
328 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
329 dump = 0;
330 break;
331 case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
332 wc->status = IB_WC_REM_ABORT_ERR;
333 break;
334 default:
335 wc->status = IB_WC_GENERAL_ERR;
336 break;
337 }
338
339 wc->vendor_err = cqe->vendor_err_synd;
340 if (dump)
341 dump_cqe(dev, cqe);
342}
343
344static int is_atomic_response(struct mlx5_ib_qp *qp, uint16_t idx)
345{
346
347
348 return 0;
349}
350
351static void *mlx5_get_atomic_laddr(struct mlx5_ib_qp *qp, uint16_t idx)
352{
353 struct mlx5_wqe_data_seg *dpseg;
354 void *addr;
355
356 dpseg = mlx5_get_send_wqe(qp, idx) + sizeof(struct mlx5_wqe_ctrl_seg) +
357 sizeof(struct mlx5_wqe_raddr_seg) +
358 sizeof(struct mlx5_wqe_atomic_seg);
359 addr = (void *)(unsigned long)be64_to_cpu(dpseg->addr);
360 return addr;
361}
362
363static void handle_atomic(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
364 uint16_t idx)
365{
366 void *addr;
367 int byte_count;
368 int i;
369
370 if (!is_atomic_response(qp, idx))
371 return;
372
373 byte_count = be32_to_cpu(cqe64->byte_cnt);
374 addr = mlx5_get_atomic_laddr(qp, idx);
375
376 if (byte_count == 4) {
377 *(uint32_t *)addr = be32_to_cpu(*((__be32 *)addr));
378 } else {
379 for (i = 0; i < byte_count; i += 8) {
380 *(uint64_t *)addr = be64_to_cpu(*((__be64 *)addr));
381 addr += 8;
382 }
383 }
384
385 return;
386}
387
388static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
389 u16 tail, u16 head)
390{
391 u16 idx;
392
393 do {
394 idx = tail & (qp->sq.wqe_cnt - 1);
395 handle_atomic(qp, cqe64, idx);
396 if (idx == head)
397 break;
398
399 tail = qp->sq.w_list[idx].next;
400 } while (1);
401 tail = qp->sq.w_list[idx].next;
402 qp->sq.last_poll = tail;
403}
404
405static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
406{
407 mlx5_buf_free(dev->mdev, &buf->buf);
408}
409
410static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
411 struct ib_sig_err *item)
412{
413 u16 syndrome = be16_to_cpu(cqe->syndrome);
414
415#define GUARD_ERR (1 << 13)
416#define APPTAG_ERR (1 << 12)
417#define REFTAG_ERR (1 << 11)
418
419 if (syndrome & GUARD_ERR) {
420 item->err_type = IB_SIG_BAD_GUARD;
421 item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
422 item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
423 } else
424 if (syndrome & REFTAG_ERR) {
425 item->err_type = IB_SIG_BAD_REFTAG;
426 item->expected = be32_to_cpu(cqe->expected_reftag);
427 item->actual = be32_to_cpu(cqe->actual_reftag);
428 } else
429 if (syndrome & APPTAG_ERR) {
430 item->err_type = IB_SIG_BAD_APPTAG;
431 item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
432 item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
433 } else {
434 pr_err("Got signature completion error with bad syndrome %04x\n",
435 syndrome);
436 }
437
438 item->sig_err_offset = be64_to_cpu(cqe->err_offset);
439 item->key = be32_to_cpu(cqe->mkey);
440}
441
442static void sw_send_comp(struct mlx5_ib_qp *qp, int num_entries,
443 struct ib_wc *wc, int *npolled)
444{
445 struct mlx5_ib_wq *wq;
446 unsigned int cur;
447 unsigned int idx;
448 int np;
449 int i;
450
451 wq = &qp->sq;
452 cur = wq->head - wq->tail;
453 np = *npolled;
454
455 if (cur == 0)
456 return;
457
458 for (i = 0; i < cur && np < num_entries; i++) {
459 idx = wq->last_poll & (wq->wqe_cnt - 1);
460 wc->wr_id = wq->wrid[idx];
461 wc->status = IB_WC_WR_FLUSH_ERR;
462 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
463 wq->tail++;
464 np++;
465 wc->qp = &qp->ibqp;
466 wc++;
467 wq->last_poll = wq->w_list[idx].next;
468 }
469 *npolled = np;
470}
471
472static void sw_recv_comp(struct mlx5_ib_qp *qp, int num_entries,
473 struct ib_wc *wc, int *npolled)
474{
475 struct mlx5_ib_wq *wq;
476 unsigned int cur;
477 int np;
478 int i;
479
480 wq = &qp->rq;
481 cur = wq->head - wq->tail;
482 np = *npolled;
483
484 if (cur == 0)
485 return;
486
487 for (i = 0; i < cur && np < num_entries; i++) {
488 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
489 wc->status = IB_WC_WR_FLUSH_ERR;
490 wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
491 wq->tail++;
492 np++;
493 wc->qp = &qp->ibqp;
494 wc++;
495 }
496 *npolled = np;
497}
498
499static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
500 struct ib_wc *wc, int *npolled)
501{
502 struct mlx5_ib_qp *qp;
503
504 *npolled = 0;
505
506 list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
507 sw_send_comp(qp, num_entries, wc + *npolled, npolled);
508 if (*npolled >= num_entries)
509 return;
510 }
511
512 list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
513 sw_recv_comp(qp, num_entries, wc + *npolled, npolled);
514 if (*npolled >= num_entries)
515 return;
516 }
517}
518
519static int mlx5_poll_one(struct mlx5_ib_cq *cq,
520 struct mlx5_ib_qp **cur_qp,
521 struct ib_wc *wc)
522{
523 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
524 struct mlx5_err_cqe *err_cqe;
525 struct mlx5_cqe64 *cqe64;
526 struct mlx5_core_qp *mqp;
527 struct mlx5_ib_wq *wq;
528 struct mlx5_sig_err_cqe *sig_err_cqe;
529 struct mlx5_core_mkey *mmkey;
530 struct mlx5_ib_mr *mr;
531 uint8_t opcode;
532 uint32_t qpn;
533 u16 wqe_ctr;
534 void *cqe;
535 int idx;
536
537repoll:
538 cqe = next_cqe_sw(cq);
539 if (!cqe)
540 return -EAGAIN;
541
542 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
543
544 ++cq->mcq.cons_index;
545
546
547
548
549 rmb();
550
551 opcode = cqe64->op_own >> 4;
552 if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
553 if (likely(cq->resize_buf)) {
554 free_cq_buf(dev, &cq->buf);
555 cq->buf = *cq->resize_buf;
556 kfree(cq->resize_buf);
557 cq->resize_buf = NULL;
558 goto repoll;
559 } else {
560 mlx5_ib_warn(dev, "unexpected resize cqe\n");
561 }
562 }
563
564 qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
565 if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
566
567
568
569
570 mqp = __mlx5_qp_lookup(dev->mdev, qpn);
571 *cur_qp = to_mibqp(mqp);
572 }
573
574 wc->qp = &(*cur_qp)->ibqp;
575 switch (opcode) {
576 case MLX5_CQE_REQ:
577 wq = &(*cur_qp)->sq;
578 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
579 idx = wqe_ctr & (wq->wqe_cnt - 1);
580 handle_good_req(wc, cqe64, wq, idx);
581 handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
582 wc->wr_id = wq->wrid[idx];
583 wq->tail = wq->wqe_head[idx] + 1;
584 wc->status = IB_WC_SUCCESS;
585 break;
586 case MLX5_CQE_RESP_WR_IMM:
587 case MLX5_CQE_RESP_SEND:
588 case MLX5_CQE_RESP_SEND_IMM:
589 case MLX5_CQE_RESP_SEND_INV:
590 handle_responder(wc, cqe64, *cur_qp);
591 wc->status = IB_WC_SUCCESS;
592 break;
593 case MLX5_CQE_RESIZE_CQ:
594 break;
595 case MLX5_CQE_REQ_ERR:
596 case MLX5_CQE_RESP_ERR:
597 err_cqe = (struct mlx5_err_cqe *)cqe64;
598 mlx5_handle_error_cqe(dev, err_cqe, wc);
599 mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
600 opcode == MLX5_CQE_REQ_ERR ?
601 "Requestor" : "Responder", cq->mcq.cqn);
602 mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
603 err_cqe->syndrome, err_cqe->vendor_err_synd);
604 if (opcode == MLX5_CQE_REQ_ERR) {
605 wq = &(*cur_qp)->sq;
606 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
607 idx = wqe_ctr & (wq->wqe_cnt - 1);
608 wc->wr_id = wq->wrid[idx];
609 wq->tail = wq->wqe_head[idx] + 1;
610 } else {
611 struct mlx5_ib_srq *srq;
612
613 if ((*cur_qp)->ibqp.srq) {
614 srq = to_msrq((*cur_qp)->ibqp.srq);
615 wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
616 wc->wr_id = srq->wrid[wqe_ctr];
617 mlx5_ib_free_srq_wqe(srq, wqe_ctr);
618 } else {
619 wq = &(*cur_qp)->rq;
620 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
621 ++wq->tail;
622 }
623 }
624 break;
625 case MLX5_CQE_SIG_ERR:
626 sig_err_cqe = (struct mlx5_sig_err_cqe *)cqe64;
627
628 read_lock(&dev->mdev->priv.mkey_table.lock);
629 mmkey = __mlx5_mr_lookup(dev->mdev,
630 mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
631 mr = to_mibmr(mmkey);
632 get_sig_err_item(sig_err_cqe, &mr->sig->err_item);
633 mr->sig->sig_err_exists = true;
634 mr->sig->sigerr_count++;
635
636 mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
637 cq->mcq.cqn, mr->sig->err_item.key,
638 mr->sig->err_item.err_type,
639 mr->sig->err_item.sig_err_offset,
640 mr->sig->err_item.expected,
641 mr->sig->err_item.actual);
642
643 read_unlock(&dev->mdev->priv.mkey_table.lock);
644 goto repoll;
645 }
646
647 return 0;
648}
649
650static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
651 struct ib_wc *wc)
652{
653 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
654 struct mlx5_ib_wc *soft_wc, *next;
655 int npolled = 0;
656
657 list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
658 if (npolled >= num_entries)
659 break;
660
661 mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
662 cq->mcq.cqn);
663
664 wc[npolled++] = soft_wc->wc;
665 list_del(&soft_wc->list);
666 kfree(soft_wc);
667 }
668
669 return npolled;
670}
671
672int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
673{
674 struct mlx5_ib_cq *cq = to_mcq(ibcq);
675 struct mlx5_ib_qp *cur_qp = NULL;
676 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
677 struct mlx5_core_dev *mdev = dev->mdev;
678 unsigned long flags;
679 int soft_polled = 0;
680 int npolled;
681
682 spin_lock_irqsave(&cq->lock, flags);
683 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
684 mlx5_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
685 goto out;
686 }
687
688 if (unlikely(!list_empty(&cq->wc_list)))
689 soft_polled = poll_soft_wc(cq, num_entries, wc);
690
691 for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
692 if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
693 break;
694 }
695
696 if (npolled)
697 mlx5_cq_set_ci(&cq->mcq);
698out:
699 spin_unlock_irqrestore(&cq->lock, flags);
700
701 return soft_polled + npolled;
702}
703
704int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
705{
706 struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
707 struct mlx5_ib_cq *cq = to_mcq(ibcq);
708 void __iomem *uar_page = mdev->priv.uar->map;
709 unsigned long irq_flags;
710 int ret = 0;
711
712 spin_lock_irqsave(&cq->lock, irq_flags);
713 if (cq->notify_flags != IB_CQ_NEXT_COMP)
714 cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
715
716 if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
717 ret = 1;
718 spin_unlock_irqrestore(&cq->lock, irq_flags);
719
720 mlx5_cq_arm(&cq->mcq,
721 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
722 MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
723 uar_page, to_mcq(ibcq)->mcq.cons_index);
724
725 return ret;
726}
727
728static int alloc_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf,
729 int nent, int cqe_size)
730{
731 int err;
732
733 err = mlx5_buf_alloc(dev->mdev, nent * cqe_size, &buf->buf);
734 if (err)
735 return err;
736
737 buf->cqe_size = cqe_size;
738 buf->nent = nent;
739
740 return 0;
741}
742
743static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
744 struct ib_ucontext *context, struct mlx5_ib_cq *cq,
745 int entries, u32 **cqb,
746 int *cqe_size, int *index, int *inlen)
747{
748 struct mlx5_ib_create_cq ucmd = {};
749 size_t ucmdlen;
750 int page_shift;
751 __be64 *pas;
752 int npages;
753 int ncont;
754 void *cqc;
755 int err;
756
757 ucmdlen = udata->inlen < sizeof(ucmd) ?
758 (sizeof(ucmd) - sizeof(ucmd.flags)) : sizeof(ucmd);
759
760 if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
761 return -EFAULT;
762
763 if (ucmdlen == sizeof(ucmd) &&
764 (ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD)))
765 return -EINVAL;
766
767 if (ucmd.cqe_size != 64 && ucmd.cqe_size != 128)
768 return -EINVAL;
769
770 *cqe_size = ucmd.cqe_size;
771
772 cq->buf.umem = ib_umem_get(context, ucmd.buf_addr,
773 entries * ucmd.cqe_size,
774 IB_ACCESS_LOCAL_WRITE, 1);
775 if (IS_ERR(cq->buf.umem)) {
776 err = PTR_ERR(cq->buf.umem);
777 return err;
778 }
779
780 err = mlx5_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
781 &cq->db);
782 if (err)
783 goto err_umem;
784
785 mlx5_ib_cont_pages(cq->buf.umem, ucmd.buf_addr, 0, &npages, &page_shift,
786 &ncont, NULL);
787 mlx5_ib_dbg(dev, "addr 0x%llx, size %u, npages %d, page_shift %d, ncont %d\n",
788 ucmd.buf_addr, entries * ucmd.cqe_size, npages, page_shift, ncont);
789
790 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
791 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
792 *cqb = kvzalloc(*inlen, GFP_KERNEL);
793 if (!*cqb) {
794 err = -ENOMEM;
795 goto err_db;
796 }
797
798 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
799 mlx5_ib_populate_pas(dev, cq->buf.umem, page_shift, pas, 0);
800
801 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
802 MLX5_SET(cqc, cqc, log_page_size,
803 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
804
805 *index = to_mucontext(context)->bfregi.sys_pages[0];
806
807 if (ucmd.cqe_comp_en == 1) {
808 if (!((*cqe_size == 128 &&
809 MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
810 (*cqe_size == 64 &&
811 MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
812 err = -EOPNOTSUPP;
813 mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
814 *cqe_size);
815 goto err_cqb;
816 }
817
818 if (unlikely(!ucmd.cqe_comp_res_format ||
819 !(ucmd.cqe_comp_res_format <
820 MLX5_IB_CQE_RES_RESERVED) ||
821 (ucmd.cqe_comp_res_format &
822 (ucmd.cqe_comp_res_format - 1)))) {
823 err = -EOPNOTSUPP;
824 mlx5_ib_warn(dev, "CQE compression res format %d is not supported!\n",
825 ucmd.cqe_comp_res_format);
826 goto err_cqb;
827 }
828
829 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
830 MLX5_SET(cqc, cqc, mini_cqe_res_format,
831 ilog2(ucmd.cqe_comp_res_format));
832 }
833
834 if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
835 if (*cqe_size != 128 ||
836 !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
837 err = -EOPNOTSUPP;
838 mlx5_ib_warn(dev,
839 "CQE padding is not supported for CQE size of %dB!\n",
840 *cqe_size);
841 goto err_cqb;
842 }
843
844 cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
845 }
846
847 return 0;
848
849err_cqb:
850 kfree(*cqb);
851
852err_db:
853 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
854
855err_umem:
856 ib_umem_release(cq->buf.umem);
857 return err;
858}
859
860static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_ucontext *context)
861{
862 mlx5_ib_db_unmap_user(to_mucontext(context), &cq->db);
863 ib_umem_release(cq->buf.umem);
864}
865
866static void init_cq_buf(struct mlx5_ib_cq *cq, struct mlx5_ib_cq_buf *buf)
867{
868 int i;
869 void *cqe;
870 struct mlx5_cqe64 *cqe64;
871
872 for (i = 0; i < buf->nent; i++) {
873 cqe = get_cqe_from_buf(buf, i, buf->cqe_size);
874 cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
875 cqe64->op_own = MLX5_CQE_INVALID << 4;
876 }
877}
878
879static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
880 int entries, int cqe_size,
881 u32 **cqb, int *index, int *inlen)
882{
883 __be64 *pas;
884 void *cqc;
885 int err;
886
887 err = mlx5_db_alloc(dev->mdev, &cq->db);
888 if (err)
889 return err;
890
891 cq->mcq.set_ci_db = cq->db.db;
892 cq->mcq.arm_db = cq->db.db + 1;
893 cq->mcq.cqe_sz = cqe_size;
894
895 err = alloc_cq_buf(dev, &cq->buf, entries, cqe_size);
896 if (err)
897 goto err_db;
898
899 init_cq_buf(cq, &cq->buf);
900
901 *inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
902 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * cq->buf.buf.npages;
903 *cqb = kvzalloc(*inlen, GFP_KERNEL);
904 if (!*cqb) {
905 err = -ENOMEM;
906 goto err_buf;
907 }
908
909 pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
910 mlx5_fill_page_array(&cq->buf.buf, pas);
911
912 cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
913 MLX5_SET(cqc, cqc, log_page_size,
914 cq->buf.buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
915
916 *index = dev->mdev->priv.uar->index;
917
918 return 0;
919
920err_buf:
921 free_cq_buf(dev, &cq->buf);
922
923err_db:
924 mlx5_db_free(dev->mdev, &cq->db);
925 return err;
926}
927
928static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
929{
930 free_cq_buf(dev, &cq->buf);
931 mlx5_db_free(dev->mdev, &cq->db);
932}
933
934static void notify_soft_wc_handler(struct work_struct *work)
935{
936 struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
937 notify_work);
938
939 cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
940}
941
942struct ib_cq *mlx5_ib_create_cq(struct ib_device *ibdev,
943 const struct ib_cq_init_attr *attr,
944 struct ib_ucontext *context,
945 struct ib_udata *udata)
946{
947 int entries = attr->cqe;
948 int vector = attr->comp_vector;
949 struct mlx5_ib_dev *dev = to_mdev(ibdev);
950 struct mlx5_ib_cq *cq;
951 int uninitialized_var(index);
952 int uninitialized_var(inlen);
953 u32 *cqb = NULL;
954 void *cqc;
955 int cqe_size;
956 unsigned int irqn;
957 int eqn;
958 int err;
959
960 if (entries < 0 ||
961 (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
962 return ERR_PTR(-EINVAL);
963
964 if (check_cq_create_flags(attr->flags))
965 return ERR_PTR(-EOPNOTSUPP);
966
967 entries = roundup_pow_of_two(entries + 1);
968 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
969 return ERR_PTR(-EINVAL);
970
971 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
972 if (!cq)
973 return ERR_PTR(-ENOMEM);
974
975 cq->ibcq.cqe = entries - 1;
976 mutex_init(&cq->resize_mutex);
977 spin_lock_init(&cq->lock);
978 cq->resize_buf = NULL;
979 cq->resize_umem = NULL;
980 cq->create_flags = attr->flags;
981 INIT_LIST_HEAD(&cq->list_send_qp);
982 INIT_LIST_HEAD(&cq->list_recv_qp);
983
984 if (context) {
985 err = create_cq_user(dev, udata, context, cq, entries,
986 &cqb, &cqe_size, &index, &inlen);
987 if (err)
988 goto err_create;
989 } else {
990 cqe_size = cache_line_size() == 128 ? 128 : 64;
991 err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
992 &index, &inlen);
993 if (err)
994 goto err_create;
995
996 INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
997 }
998
999 err = mlx5_vector2eqn(dev->mdev, vector, &eqn, &irqn);
1000 if (err)
1001 goto err_cqb;
1002
1003 cq->cqe_size = cqe_size;
1004
1005 cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
1006 MLX5_SET(cqc, cqc, cqe_sz,
1007 cqe_sz_to_mlx_sz(cqe_size,
1008 cq->private_flags &
1009 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1010 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1011 MLX5_SET(cqc, cqc, uar_page, index);
1012 MLX5_SET(cqc, cqc, c_eqn, eqn);
1013 MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
1014 if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
1015 MLX5_SET(cqc, cqc, oi, 1);
1016
1017 err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen);
1018 if (err)
1019 goto err_cqb;
1020
1021 mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
1022 cq->mcq.irqn = irqn;
1023 if (context)
1024 cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
1025 else
1026 cq->mcq.comp = mlx5_ib_cq_comp;
1027 cq->mcq.event = mlx5_ib_cq_event;
1028
1029 INIT_LIST_HEAD(&cq->wc_list);
1030
1031 if (context)
1032 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
1033 err = -EFAULT;
1034 goto err_cmd;
1035 }
1036
1037
1038 kvfree(cqb);
1039 return &cq->ibcq;
1040
1041err_cmd:
1042 mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
1043
1044err_cqb:
1045 kvfree(cqb);
1046 if (context)
1047 destroy_cq_user(cq, context);
1048 else
1049 destroy_cq_kernel(dev, cq);
1050
1051err_create:
1052 kfree(cq);
1053
1054 return ERR_PTR(err);
1055}
1056
1057
1058int mlx5_ib_destroy_cq(struct ib_cq *cq)
1059{
1060 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1061 struct mlx5_ib_cq *mcq = to_mcq(cq);
1062 struct ib_ucontext *context = NULL;
1063
1064 if (cq->uobject)
1065 context = cq->uobject->context;
1066
1067 mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1068 if (context)
1069 destroy_cq_user(mcq, context);
1070 else
1071 destroy_cq_kernel(dev, mcq);
1072
1073 kfree(mcq);
1074
1075 return 0;
1076}
1077
1078static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1079{
1080 return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1081}
1082
1083void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1084{
1085 struct mlx5_cqe64 *cqe64, *dest64;
1086 void *cqe, *dest;
1087 u32 prod_index;
1088 int nfreed = 0;
1089 u8 owner_bit;
1090
1091 if (!cq)
1092 return;
1093
1094
1095
1096
1097
1098
1099
1100 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1101 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1102 break;
1103
1104
1105
1106
1107 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1108 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1109 cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1110 if (is_equal_rsn(cqe64, rsn)) {
1111 if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1112 mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1113 ++nfreed;
1114 } else if (nfreed) {
1115 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1116 dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1117 owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1118 memcpy(dest, cqe, cq->mcq.cqe_sz);
1119 dest64->op_own = owner_bit |
1120 (dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1121 }
1122 }
1123
1124 if (nfreed) {
1125 cq->mcq.cons_index += nfreed;
1126
1127
1128
1129 wmb();
1130 mlx5_cq_set_ci(&cq->mcq);
1131 }
1132}
1133
1134void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1135{
1136 if (!cq)
1137 return;
1138
1139 spin_lock_irq(&cq->lock);
1140 __mlx5_ib_cq_clean(cq, qpn, srq);
1141 spin_unlock_irq(&cq->lock);
1142}
1143
1144int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1145{
1146 struct mlx5_ib_dev *dev = to_mdev(cq->device);
1147 struct mlx5_ib_cq *mcq = to_mcq(cq);
1148 int err;
1149
1150 if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1151 return -ENOSYS;
1152
1153 if (cq_period > MLX5_MAX_CQ_PERIOD)
1154 return -EINVAL;
1155
1156 err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1157 cq_period, cq_count);
1158 if (err)
1159 mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1160
1161 return err;
1162}
1163
1164static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1165 int entries, struct ib_udata *udata, int *npas,
1166 int *page_shift, int *cqe_size)
1167{
1168 struct mlx5_ib_resize_cq ucmd;
1169 struct ib_umem *umem;
1170 int err;
1171 int npages;
1172 struct ib_ucontext *context = cq->buf.umem->context;
1173
1174 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1175 if (err)
1176 return err;
1177
1178 if (ucmd.reserved0 || ucmd.reserved1)
1179 return -EINVAL;
1180
1181
1182 if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1)
1183 return -EINVAL;
1184
1185 umem = ib_umem_get(context, ucmd.buf_addr,
1186 (size_t)ucmd.cqe_size * entries,
1187 IB_ACCESS_LOCAL_WRITE, 1);
1188 if (IS_ERR(umem)) {
1189 err = PTR_ERR(umem);
1190 return err;
1191 }
1192
1193 mlx5_ib_cont_pages(umem, ucmd.buf_addr, 0, &npages, page_shift,
1194 npas, NULL);
1195
1196 cq->resize_umem = umem;
1197 *cqe_size = ucmd.cqe_size;
1198
1199 return 0;
1200}
1201
1202static void un_resize_user(struct mlx5_ib_cq *cq)
1203{
1204 ib_umem_release(cq->resize_umem);
1205}
1206
1207static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1208 int entries, int cqe_size)
1209{
1210 int err;
1211
1212 cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1213 if (!cq->resize_buf)
1214 return -ENOMEM;
1215
1216 err = alloc_cq_buf(dev, cq->resize_buf, entries, cqe_size);
1217 if (err)
1218 goto ex;
1219
1220 init_cq_buf(cq, cq->resize_buf);
1221
1222 return 0;
1223
1224ex:
1225 kfree(cq->resize_buf);
1226 return err;
1227}
1228
1229static void un_resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
1230{
1231 free_cq_buf(dev, cq->resize_buf);
1232 cq->resize_buf = NULL;
1233}
1234
1235static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1236{
1237 struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1238 struct mlx5_cqe64 *scqe64;
1239 struct mlx5_cqe64 *dcqe64;
1240 void *start_cqe;
1241 void *scqe;
1242 void *dcqe;
1243 int ssize;
1244 int dsize;
1245 int i;
1246 u8 sw_own;
1247
1248 ssize = cq->buf.cqe_size;
1249 dsize = cq->resize_buf->cqe_size;
1250 if (ssize != dsize) {
1251 mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1252 return -EINVAL;
1253 }
1254
1255 i = cq->mcq.cons_index;
1256 scqe = get_sw_cqe(cq, i);
1257 scqe64 = ssize == 64 ? scqe : scqe + 64;
1258 start_cqe = scqe;
1259 if (!scqe) {
1260 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1261 return -EINVAL;
1262 }
1263
1264 while ((scqe64->op_own >> 4) != MLX5_CQE_RESIZE_CQ) {
1265 dcqe = get_cqe_from_buf(cq->resize_buf,
1266 (i + 1) & (cq->resize_buf->nent),
1267 dsize);
1268 dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1269 sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1270 memcpy(dcqe, scqe, dsize);
1271 dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1272
1273 ++i;
1274 scqe = get_sw_cqe(cq, i);
1275 scqe64 = ssize == 64 ? scqe : scqe + 64;
1276 if (!scqe) {
1277 mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1278 return -EINVAL;
1279 }
1280
1281 if (scqe == start_cqe) {
1282 pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1283 cq->mcq.cqn);
1284 return -ENOMEM;
1285 }
1286 }
1287 ++cq->mcq.cons_index;
1288 return 0;
1289}
1290
1291int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1292{
1293 struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1294 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1295 void *cqc;
1296 u32 *in;
1297 int err;
1298 int npas;
1299 __be64 *pas;
1300 int page_shift;
1301 int inlen;
1302 int uninitialized_var(cqe_size);
1303 unsigned long flags;
1304
1305 if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1306 pr_info("Firmware does not support resize CQ\n");
1307 return -ENOSYS;
1308 }
1309
1310 if (entries < 1 ||
1311 entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1312 mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1313 entries,
1314 1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1315 return -EINVAL;
1316 }
1317
1318 entries = roundup_pow_of_two(entries + 1);
1319 if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1320 return -EINVAL;
1321
1322 if (entries == ibcq->cqe + 1)
1323 return 0;
1324
1325 mutex_lock(&cq->resize_mutex);
1326 if (udata) {
1327 err = resize_user(dev, cq, entries, udata, &npas, &page_shift,
1328 &cqe_size);
1329 } else {
1330 cqe_size = 64;
1331 err = resize_kernel(dev, cq, entries, cqe_size);
1332 if (!err) {
1333 npas = cq->resize_buf->buf.npages;
1334 page_shift = cq->resize_buf->buf.page_shift;
1335 }
1336 }
1337
1338 if (err)
1339 goto ex;
1340
1341 inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1342 MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1343
1344 in = kvzalloc(inlen, GFP_KERNEL);
1345 if (!in) {
1346 err = -ENOMEM;
1347 goto ex_resize;
1348 }
1349
1350 pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1351 if (udata)
1352 mlx5_ib_populate_pas(dev, cq->resize_umem, page_shift,
1353 pas, 0);
1354 else
1355 mlx5_fill_page_array(&cq->resize_buf->buf, pas);
1356
1357 MLX5_SET(modify_cq_in, in,
1358 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1359 MLX5_MODIFY_CQ_MASK_LOG_SIZE |
1360 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1361 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1362
1363 cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1364
1365 MLX5_SET(cqc, cqc, log_page_size,
1366 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1367 MLX5_SET(cqc, cqc, cqe_sz,
1368 cqe_sz_to_mlx_sz(cqe_size,
1369 cq->private_flags &
1370 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1371 MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1372
1373 MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1374 MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1375
1376 err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1377 if (err)
1378 goto ex_alloc;
1379
1380 if (udata) {
1381 cq->ibcq.cqe = entries - 1;
1382 ib_umem_release(cq->buf.umem);
1383 cq->buf.umem = cq->resize_umem;
1384 cq->resize_umem = NULL;
1385 } else {
1386 struct mlx5_ib_cq_buf tbuf;
1387 int resized = 0;
1388
1389 spin_lock_irqsave(&cq->lock, flags);
1390 if (cq->resize_buf) {
1391 err = copy_resize_cqes(cq);
1392 if (!err) {
1393 tbuf = cq->buf;
1394 cq->buf = *cq->resize_buf;
1395 kfree(cq->resize_buf);
1396 cq->resize_buf = NULL;
1397 resized = 1;
1398 }
1399 }
1400 cq->ibcq.cqe = entries - 1;
1401 spin_unlock_irqrestore(&cq->lock, flags);
1402 if (resized)
1403 free_cq_buf(dev, &tbuf);
1404 }
1405 mutex_unlock(&cq->resize_mutex);
1406
1407 kvfree(in);
1408 return 0;
1409
1410ex_alloc:
1411 kvfree(in);
1412
1413ex_resize:
1414 if (udata)
1415 un_resize_user(cq);
1416 else
1417 un_resize_kernel(dev, cq);
1418ex:
1419 mutex_unlock(&cq->resize_mutex);
1420 return err;
1421}
1422
1423int mlx5_ib_get_cqe_size(struct mlx5_ib_dev *dev, struct ib_cq *ibcq)
1424{
1425 struct mlx5_ib_cq *cq;
1426
1427 if (!ibcq)
1428 return 128;
1429
1430 cq = to_mcq(ibcq);
1431 return cq->cqe_size;
1432}
1433
1434
1435int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1436{
1437 struct mlx5_ib_wc *soft_wc;
1438 struct mlx5_ib_cq *cq = to_mcq(ibcq);
1439 unsigned long flags;
1440
1441 soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1442 if (!soft_wc)
1443 return -ENOMEM;
1444
1445 soft_wc->wc = *wc;
1446 spin_lock_irqsave(&cq->lock, flags);
1447 list_add_tail(&soft_wc->list, &cq->wc_list);
1448 if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1449 wc->status != IB_WC_SUCCESS) {
1450 cq->notify_flags = 0;
1451 schedule_work(&cq->notify_work);
1452 }
1453 spin_unlock_irqrestore(&cq->lock, flags);
1454
1455 return 0;
1456}
1457
