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35#include <linux/pci.h>
36#include <linux/netdevice.h>
37#include <linux/vmalloc.h>
38#include <linux/delay.h>
39#include <linux/idr.h>
40#include <linux/module.h>
41#include <linux/printk.h>
42#ifdef CONFIG_INFINIBAND_QIB_DCA
43#include <linux/dca.h>
44#endif
45#include <rdma/rdma_vt.h>
46
47#include "qib.h"
48#include "qib_common.h"
49#include "qib_mad.h"
50#ifdef CONFIG_DEBUG_FS
51#include "qib_debugfs.h"
52#include "qib_verbs.h"
53#endif
54
55#undef pr_fmt
56#define pr_fmt(fmt) QIB_DRV_NAME ": " fmt
57
58
59
60
61#define QIB_MIN_USER_CTXT_BUFCNT 7
62
63#define QLOGIC_IB_R_SOFTWARE_MASK 0xFF
64#define QLOGIC_IB_R_SOFTWARE_SHIFT 24
65#define QLOGIC_IB_R_EMULATOR_MASK (1ULL<<62)
66
67
68
69
70
71ushort qib_cfgctxts;
72module_param_named(cfgctxts, qib_cfgctxts, ushort, S_IRUGO);
73MODULE_PARM_DESC(cfgctxts, "Set max number of contexts to use");
74
75unsigned qib_numa_aware;
76module_param_named(numa_aware, qib_numa_aware, uint, S_IRUGO);
77MODULE_PARM_DESC(numa_aware,
78 "0 -> PSM allocation close to HCA, 1 -> PSM allocation local to process");
79
80
81
82
83
84ushort qib_mini_init;
85module_param_named(mini_init, qib_mini_init, ushort, S_IRUGO);
86MODULE_PARM_DESC(mini_init, "If set, do minimal diag init");
87
88unsigned qib_n_krcv_queues;
89module_param_named(krcvqs, qib_n_krcv_queues, uint, S_IRUGO);
90MODULE_PARM_DESC(krcvqs, "number of kernel receive queues per IB port");
91
92unsigned qib_cc_table_size;
93module_param_named(cc_table_size, qib_cc_table_size, uint, S_IRUGO);
94MODULE_PARM_DESC(cc_table_size, "Congestion control table entries 0 (CCA disabled - default), min = 128, max = 1984");
95
96static void verify_interrupt(struct timer_list *);
97
98static struct idr qib_unit_table;
99u32 qib_cpulist_count;
100unsigned long *qib_cpulist;
101
102
103void qib_set_ctxtcnt(struct qib_devdata *dd)
104{
105 if (!qib_cfgctxts) {
106 dd->cfgctxts = dd->first_user_ctxt + num_online_cpus();
107 if (dd->cfgctxts > dd->ctxtcnt)
108 dd->cfgctxts = dd->ctxtcnt;
109 } else if (qib_cfgctxts < dd->num_pports)
110 dd->cfgctxts = dd->ctxtcnt;
111 else if (qib_cfgctxts <= dd->ctxtcnt)
112 dd->cfgctxts = qib_cfgctxts;
113 else
114 dd->cfgctxts = dd->ctxtcnt;
115 dd->freectxts = (dd->first_user_ctxt > dd->cfgctxts) ? 0 :
116 dd->cfgctxts - dd->first_user_ctxt;
117}
118
119
120
121
122int qib_create_ctxts(struct qib_devdata *dd)
123{
124 unsigned i;
125 int local_node_id = pcibus_to_node(dd->pcidev->bus);
126
127 if (local_node_id < 0)
128 local_node_id = numa_node_id();
129 dd->assigned_node_id = local_node_id;
130
131
132
133
134
135 dd->rcd = kcalloc(dd->ctxtcnt, sizeof(*dd->rcd), GFP_KERNEL);
136 if (!dd->rcd)
137 return -ENOMEM;
138
139
140 for (i = 0; i < dd->first_user_ctxt; ++i) {
141 struct qib_pportdata *ppd;
142 struct qib_ctxtdata *rcd;
143
144 if (dd->skip_kctxt_mask & (1 << i))
145 continue;
146
147 ppd = dd->pport + (i % dd->num_pports);
148
149 rcd = qib_create_ctxtdata(ppd, i, dd->assigned_node_id);
150 if (!rcd) {
151 qib_dev_err(dd,
152 "Unable to allocate ctxtdata for Kernel ctxt, failing\n");
153 kfree(dd->rcd);
154 dd->rcd = NULL;
155 return -ENOMEM;
156 }
157 rcd->pkeys[0] = QIB_DEFAULT_P_KEY;
158 rcd->seq_cnt = 1;
159 }
160 return 0;
161}
162
163
164
165
166struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *ppd, u32 ctxt,
167 int node_id)
168{
169 struct qib_devdata *dd = ppd->dd;
170 struct qib_ctxtdata *rcd;
171
172 rcd = kzalloc_node(sizeof(*rcd), GFP_KERNEL, node_id);
173 if (rcd) {
174 INIT_LIST_HEAD(&rcd->qp_wait_list);
175 rcd->node_id = node_id;
176 rcd->ppd = ppd;
177 rcd->dd = dd;
178 rcd->cnt = 1;
179 rcd->ctxt = ctxt;
180 dd->rcd[ctxt] = rcd;
181#ifdef CONFIG_DEBUG_FS
182 if (ctxt < dd->first_user_ctxt) {
183 rcd->opstats = kzalloc_node(sizeof(*rcd->opstats),
184 GFP_KERNEL, node_id);
185 if (!rcd->opstats) {
186 kfree(rcd);
187 qib_dev_err(dd,
188 "Unable to allocate per ctxt stats buffer\n");
189 return NULL;
190 }
191 }
192#endif
193 dd->f_init_ctxt(rcd);
194
195
196
197
198
199
200
201
202
203
204
205
206 rcd->rcvegrbuf_size = 0x8000;
207 rcd->rcvegrbufs_perchunk =
208 rcd->rcvegrbuf_size / dd->rcvegrbufsize;
209 rcd->rcvegrbuf_chunks = (rcd->rcvegrcnt +
210 rcd->rcvegrbufs_perchunk - 1) /
211 rcd->rcvegrbufs_perchunk;
212 BUG_ON(!is_power_of_2(rcd->rcvegrbufs_perchunk));
213 rcd->rcvegrbufs_perchunk_shift =
214 ilog2(rcd->rcvegrbufs_perchunk);
215 }
216 return rcd;
217}
218
219
220
221
222int qib_init_pportdata(struct qib_pportdata *ppd, struct qib_devdata *dd,
223 u8 hw_pidx, u8 port)
224{
225 int size;
226
227 ppd->dd = dd;
228 ppd->hw_pidx = hw_pidx;
229 ppd->port = port;
230
231 spin_lock_init(&ppd->sdma_lock);
232 spin_lock_init(&ppd->lflags_lock);
233 spin_lock_init(&ppd->cc_shadow_lock);
234 init_waitqueue_head(&ppd->state_wait);
235
236 timer_setup(&ppd->symerr_clear_timer, qib_clear_symerror_on_linkup, 0);
237
238 ppd->qib_wq = NULL;
239 ppd->ibport_data.pmastats =
240 alloc_percpu(struct qib_pma_counters);
241 if (!ppd->ibport_data.pmastats)
242 return -ENOMEM;
243 ppd->ibport_data.rvp.rc_acks = alloc_percpu(u64);
244 ppd->ibport_data.rvp.rc_qacks = alloc_percpu(u64);
245 ppd->ibport_data.rvp.rc_delayed_comp = alloc_percpu(u64);
246 if (!(ppd->ibport_data.rvp.rc_acks) ||
247 !(ppd->ibport_data.rvp.rc_qacks) ||
248 !(ppd->ibport_data.rvp.rc_delayed_comp))
249 return -ENOMEM;
250
251 if (qib_cc_table_size < IB_CCT_MIN_ENTRIES)
252 goto bail;
253
254 ppd->cc_supported_table_entries = min(max_t(int, qib_cc_table_size,
255 IB_CCT_MIN_ENTRIES), IB_CCT_ENTRIES*IB_CC_TABLE_CAP_DEFAULT);
256
257 ppd->cc_max_table_entries =
258 ppd->cc_supported_table_entries/IB_CCT_ENTRIES;
259
260 size = IB_CC_TABLE_CAP_DEFAULT * sizeof(struct ib_cc_table_entry)
261 * IB_CCT_ENTRIES;
262 ppd->ccti_entries = kzalloc(size, GFP_KERNEL);
263 if (!ppd->ccti_entries)
264 goto bail;
265
266 size = IB_CC_CCS_ENTRIES * sizeof(struct ib_cc_congestion_entry);
267 ppd->congestion_entries = kzalloc(size, GFP_KERNEL);
268 if (!ppd->congestion_entries)
269 goto bail_1;
270
271 size = sizeof(struct cc_table_shadow);
272 ppd->ccti_entries_shadow = kzalloc(size, GFP_KERNEL);
273 if (!ppd->ccti_entries_shadow)
274 goto bail_2;
275
276 size = sizeof(struct ib_cc_congestion_setting_attr);
277 ppd->congestion_entries_shadow = kzalloc(size, GFP_KERNEL);
278 if (!ppd->congestion_entries_shadow)
279 goto bail_3;
280
281 return 0;
282
283bail_3:
284 kfree(ppd->ccti_entries_shadow);
285 ppd->ccti_entries_shadow = NULL;
286bail_2:
287 kfree(ppd->congestion_entries);
288 ppd->congestion_entries = NULL;
289bail_1:
290 kfree(ppd->ccti_entries);
291 ppd->ccti_entries = NULL;
292bail:
293
294 if (!qib_cc_table_size)
295 return 0;
296
297 if (qib_cc_table_size < IB_CCT_MIN_ENTRIES) {
298 qib_cc_table_size = 0;
299 qib_dev_err(dd,
300 "Congestion Control table size %d less than minimum %d for port %d\n",
301 qib_cc_table_size, IB_CCT_MIN_ENTRIES, port);
302 }
303
304 qib_dev_err(dd, "Congestion Control Agent disabled for port %d\n",
305 port);
306 return 0;
307}
308
309static int init_pioavailregs(struct qib_devdata *dd)
310{
311 int ret, pidx;
312 u64 *status_page;
313
314 dd->pioavailregs_dma = dma_alloc_coherent(
315 &dd->pcidev->dev, PAGE_SIZE, &dd->pioavailregs_phys,
316 GFP_KERNEL);
317 if (!dd->pioavailregs_dma) {
318 qib_dev_err(dd,
319 "failed to allocate PIOavail reg area in memory\n");
320 ret = -ENOMEM;
321 goto done;
322 }
323
324
325
326
327
328 status_page = (u64 *)
329 ((char *) dd->pioavailregs_dma +
330 ((2 * L1_CACHE_BYTES +
331 dd->pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
332
333 dd->devstatusp = status_page;
334 *status_page++ = 0;
335 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
336 dd->pport[pidx].statusp = status_page;
337 *status_page++ = 0;
338 }
339
340
341
342
343
344 dd->freezemsg = (char *) status_page;
345 *dd->freezemsg = 0;
346
347 ret = (char *) status_page - (char *) dd->pioavailregs_dma;
348 dd->freezelen = PAGE_SIZE - ret;
349
350 ret = 0;
351
352done:
353 return ret;
354}
355
356
357
358
359
360
361
362
363
364
365
366
367static void init_shadow_tids(struct qib_devdata *dd)
368{
369 struct page **pages;
370 dma_addr_t *addrs;
371
372 pages = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(struct page *));
373 if (!pages)
374 goto bail;
375
376 addrs = vzalloc(dd->cfgctxts * dd->rcvtidcnt * sizeof(dma_addr_t));
377 if (!addrs)
378 goto bail_free;
379
380 dd->pageshadow = pages;
381 dd->physshadow = addrs;
382 return;
383
384bail_free:
385 vfree(pages);
386bail:
387 dd->pageshadow = NULL;
388}
389
390
391
392
393
394static int loadtime_init(struct qib_devdata *dd)
395{
396 int ret = 0;
397
398 if (((dd->revision >> QLOGIC_IB_R_SOFTWARE_SHIFT) &
399 QLOGIC_IB_R_SOFTWARE_MASK) != QIB_CHIP_SWVERSION) {
400 qib_dev_err(dd,
401 "Driver only handles version %d, chip swversion is %d (%llx), failing\n",
402 QIB_CHIP_SWVERSION,
403 (int)(dd->revision >>
404 QLOGIC_IB_R_SOFTWARE_SHIFT) &
405 QLOGIC_IB_R_SOFTWARE_MASK,
406 (unsigned long long) dd->revision);
407 ret = -ENOSYS;
408 goto done;
409 }
410
411 if (dd->revision & QLOGIC_IB_R_EMULATOR_MASK)
412 qib_devinfo(dd->pcidev, "%s", dd->boardversion);
413
414 spin_lock_init(&dd->pioavail_lock);
415 spin_lock_init(&dd->sendctrl_lock);
416 spin_lock_init(&dd->uctxt_lock);
417 spin_lock_init(&dd->qib_diag_trans_lock);
418 spin_lock_init(&dd->eep_st_lock);
419 mutex_init(&dd->eep_lock);
420
421 if (qib_mini_init)
422 goto done;
423
424 ret = init_pioavailregs(dd);
425 init_shadow_tids(dd);
426
427 qib_get_eeprom_info(dd);
428
429
430 timer_setup(&dd->intrchk_timer, verify_interrupt, 0);
431done:
432 return ret;
433}
434
435
436
437
438
439
440
441
442
443static int init_after_reset(struct qib_devdata *dd)
444{
445 int i;
446
447
448
449
450
451
452 for (i = 0; i < dd->num_pports; ++i) {
453
454
455
456
457 dd->f_rcvctrl(dd->pport + i, QIB_RCVCTRL_CTXT_DIS |
458 QIB_RCVCTRL_INTRAVAIL_DIS |
459 QIB_RCVCTRL_TAILUPD_DIS, -1);
460
461 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_DIS |
462 QIB_SENDCTRL_AVAIL_DIS);
463 }
464
465 return 0;
466}
467
468static void enable_chip(struct qib_devdata *dd)
469{
470 u64 rcvmask;
471 int i;
472
473
474
475
476 for (i = 0; i < dd->num_pports; ++i)
477 dd->f_sendctrl(dd->pport + i, QIB_SENDCTRL_SEND_ENB |
478 QIB_SENDCTRL_AVAIL_ENB);
479
480
481
482
483 rcvmask = QIB_RCVCTRL_CTXT_ENB | QIB_RCVCTRL_INTRAVAIL_ENB;
484 rcvmask |= (dd->flags & QIB_NODMA_RTAIL) ?
485 QIB_RCVCTRL_TAILUPD_DIS : QIB_RCVCTRL_TAILUPD_ENB;
486 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
487 struct qib_ctxtdata *rcd = dd->rcd[i];
488
489 if (rcd)
490 dd->f_rcvctrl(rcd->ppd, rcvmask, i);
491 }
492}
493
494static void verify_interrupt(struct timer_list *t)
495{
496 struct qib_devdata *dd = from_timer(dd, t, intrchk_timer);
497 u64 int_counter;
498
499 if (!dd)
500 return;
501
502
503
504
505
506 int_counter = qib_int_counter(dd) - dd->z_int_counter;
507 if (int_counter == 0) {
508 if (!dd->f_intr_fallback(dd))
509 dev_err(&dd->pcidev->dev,
510 "No interrupts detected, not usable.\n");
511 else
512 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
513 }
514}
515
516static void init_piobuf_state(struct qib_devdata *dd)
517{
518 int i, pidx;
519 u32 uctxts;
520
521
522
523
524
525
526
527
528
529 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_ALL);
530 for (pidx = 0; pidx < dd->num_pports; ++pidx)
531 dd->f_sendctrl(dd->pport + pidx, QIB_SENDCTRL_FLUSH);
532
533
534
535
536
537
538
539 uctxts = dd->cfgctxts - dd->first_user_ctxt;
540 dd->ctxts_extrabuf = dd->pbufsctxt ?
541 dd->lastctxt_piobuf - (dd->pbufsctxt * uctxts) : 0;
542
543
544
545
546
547
548
549
550
551
552 for (i = 0; i < dd->pioavregs; i++) {
553 __le64 tmp;
554
555 tmp = dd->pioavailregs_dma[i];
556
557
558
559
560
561 dd->pioavailshadow[i] = le64_to_cpu(tmp);
562 }
563 while (i < ARRAY_SIZE(dd->pioavailshadow))
564 dd->pioavailshadow[i++] = 0;
565
566
567 qib_chg_pioavailkernel(dd, 0, dd->piobcnt2k + dd->piobcnt4k,
568 TXCHK_CHG_TYPE_KERN, NULL);
569 dd->f_initvl15_bufs(dd);
570}
571
572
573
574
575
576static int qib_create_workqueues(struct qib_devdata *dd)
577{
578 int pidx;
579 struct qib_pportdata *ppd;
580
581 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
582 ppd = dd->pport + pidx;
583 if (!ppd->qib_wq) {
584 char wq_name[8];
585
586 snprintf(wq_name, sizeof(wq_name), "qib%d_%d",
587 dd->unit, pidx);
588 ppd->qib_wq = alloc_ordered_workqueue(wq_name,
589 WQ_MEM_RECLAIM);
590 if (!ppd->qib_wq)
591 goto wq_error;
592 }
593 }
594 return 0;
595wq_error:
596 pr_err("create_singlethread_workqueue failed for port %d\n",
597 pidx + 1);
598 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
599 ppd = dd->pport + pidx;
600 if (ppd->qib_wq) {
601 destroy_workqueue(ppd->qib_wq);
602 ppd->qib_wq = NULL;
603 }
604 }
605 return -ENOMEM;
606}
607
608static void qib_free_pportdata(struct qib_pportdata *ppd)
609{
610 free_percpu(ppd->ibport_data.pmastats);
611 free_percpu(ppd->ibport_data.rvp.rc_acks);
612 free_percpu(ppd->ibport_data.rvp.rc_qacks);
613 free_percpu(ppd->ibport_data.rvp.rc_delayed_comp);
614 ppd->ibport_data.pmastats = NULL;
615}
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632int qib_init(struct qib_devdata *dd, int reinit)
633{
634 int ret = 0, pidx, lastfail = 0;
635 u32 portok = 0;
636 unsigned i;
637 struct qib_ctxtdata *rcd;
638 struct qib_pportdata *ppd;
639 unsigned long flags;
640
641
642 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
643 ppd = dd->pport + pidx;
644 spin_lock_irqsave(&ppd->lflags_lock, flags);
645 ppd->lflags &= ~(QIBL_LINKACTIVE | QIBL_LINKARMED |
646 QIBL_LINKDOWN | QIBL_LINKINIT |
647 QIBL_LINKV);
648 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
649 }
650
651 if (reinit)
652 ret = init_after_reset(dd);
653 else
654 ret = loadtime_init(dd);
655 if (ret)
656 goto done;
657
658
659 if (qib_mini_init)
660 return 0;
661
662 ret = dd->f_late_initreg(dd);
663 if (ret)
664 goto done;
665
666
667 for (i = 0; dd->rcd && i < dd->first_user_ctxt; ++i) {
668
669
670
671
672
673
674 rcd = dd->rcd[i];
675 if (!rcd)
676 continue;
677
678 lastfail = qib_create_rcvhdrq(dd, rcd);
679 if (!lastfail)
680 lastfail = qib_setup_eagerbufs(rcd);
681 if (lastfail) {
682 qib_dev_err(dd,
683 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
684 continue;
685 }
686 }
687
688 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
689 int mtu;
690
691 if (lastfail)
692 ret = lastfail;
693 ppd = dd->pport + pidx;
694 mtu = ib_mtu_enum_to_int(qib_ibmtu);
695 if (mtu == -1) {
696 mtu = QIB_DEFAULT_MTU;
697 qib_ibmtu = 0;
698 }
699
700 ppd->init_ibmaxlen = min(mtu > 2048 ?
701 dd->piosize4k : dd->piosize2k,
702 dd->rcvegrbufsize +
703 (dd->rcvhdrentsize << 2));
704
705
706
707
708 ppd->ibmaxlen = ppd->init_ibmaxlen;
709 qib_set_mtu(ppd, mtu);
710
711 spin_lock_irqsave(&ppd->lflags_lock, flags);
712 ppd->lflags |= QIBL_IB_LINK_DISABLED;
713 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
714
715 lastfail = dd->f_bringup_serdes(ppd);
716 if (lastfail) {
717 qib_devinfo(dd->pcidev,
718 "Failed to bringup IB port %u\n", ppd->port);
719 lastfail = -ENETDOWN;
720 continue;
721 }
722
723 portok++;
724 }
725
726 if (!portok) {
727
728 if (!ret && lastfail)
729 ret = lastfail;
730 else if (!ret)
731 ret = -ENETDOWN;
732
733 }
734
735 enable_chip(dd);
736
737 init_piobuf_state(dd);
738
739done:
740 if (!ret) {
741
742 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
743 ppd = dd->pport + pidx;
744
745
746
747
748 *ppd->statusp |= QIB_STATUS_CHIP_PRESENT |
749 QIB_STATUS_INITTED;
750 if (!ppd->link_speed_enabled)
751 continue;
752 if (dd->flags & QIB_HAS_SEND_DMA)
753 ret = qib_setup_sdma(ppd);
754 timer_setup(&ppd->hol_timer, qib_hol_event, 0);
755 ppd->hol_state = QIB_HOL_UP;
756 }
757
758
759 dd->f_set_intr_state(dd, 1);
760
761
762
763
764
765 mod_timer(&dd->intrchk_timer, jiffies + HZ/2);
766
767 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
768 }
769
770
771 return ret;
772}
773
774
775
776
777
778
779
780int __attribute__((weak)) qib_enable_wc(struct qib_devdata *dd)
781{
782 return -EOPNOTSUPP;
783}
784
785void __attribute__((weak)) qib_disable_wc(struct qib_devdata *dd)
786{
787}
788
789static inline struct qib_devdata *__qib_lookup(int unit)
790{
791 return idr_find(&qib_unit_table, unit);
792}
793
794struct qib_devdata *qib_lookup(int unit)
795{
796 struct qib_devdata *dd;
797 unsigned long flags;
798
799 spin_lock_irqsave(&qib_devs_lock, flags);
800 dd = __qib_lookup(unit);
801 spin_unlock_irqrestore(&qib_devs_lock, flags);
802
803 return dd;
804}
805
806
807
808
809
810static void qib_stop_timers(struct qib_devdata *dd)
811{
812 struct qib_pportdata *ppd;
813 int pidx;
814
815 if (dd->stats_timer.function)
816 del_timer_sync(&dd->stats_timer);
817 if (dd->intrchk_timer.function)
818 del_timer_sync(&dd->intrchk_timer);
819 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
820 ppd = dd->pport + pidx;
821 if (ppd->hol_timer.function)
822 del_timer_sync(&ppd->hol_timer);
823 if (ppd->led_override_timer.function) {
824 del_timer_sync(&ppd->led_override_timer);
825 atomic_set(&ppd->led_override_timer_active, 0);
826 }
827 if (ppd->symerr_clear_timer.function)
828 del_timer_sync(&ppd->symerr_clear_timer);
829 }
830}
831
832
833
834
835
836
837
838
839
840
841static void qib_shutdown_device(struct qib_devdata *dd)
842{
843 struct qib_pportdata *ppd;
844 unsigned pidx;
845
846 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
847 ppd = dd->pport + pidx;
848
849 spin_lock_irq(&ppd->lflags_lock);
850 ppd->lflags &= ~(QIBL_LINKDOWN | QIBL_LINKINIT |
851 QIBL_LINKARMED | QIBL_LINKACTIVE |
852 QIBL_LINKV);
853 spin_unlock_irq(&ppd->lflags_lock);
854 *ppd->statusp &= ~(QIB_STATUS_IB_CONF | QIB_STATUS_IB_READY);
855 }
856 dd->flags &= ~QIB_INITTED;
857
858
859 dd->f_set_intr_state(dd, 0);
860
861 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
862 ppd = dd->pport + pidx;
863 dd->f_rcvctrl(ppd, QIB_RCVCTRL_TAILUPD_DIS |
864 QIB_RCVCTRL_CTXT_DIS |
865 QIB_RCVCTRL_INTRAVAIL_DIS |
866 QIB_RCVCTRL_PKEY_ENB, -1);
867
868
869
870
871 dd->f_sendctrl(ppd, QIB_SENDCTRL_CLEAR);
872 }
873
874
875
876
877
878 udelay(20);
879
880 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
881 ppd = dd->pport + pidx;
882 dd->f_setextled(ppd, 0);
883
884 if (dd->flags & QIB_HAS_SEND_DMA)
885 qib_teardown_sdma(ppd);
886
887 dd->f_sendctrl(ppd, QIB_SENDCTRL_AVAIL_DIS |
888 QIB_SENDCTRL_SEND_DIS);
889
890
891
892
893 dd->f_quiet_serdes(ppd);
894
895 if (ppd->qib_wq) {
896 destroy_workqueue(ppd->qib_wq);
897 ppd->qib_wq = NULL;
898 }
899 qib_free_pportdata(ppd);
900 }
901
902}
903
904
905
906
907
908
909
910
911
912
913
914
915void qib_free_ctxtdata(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
916{
917 if (!rcd)
918 return;
919
920 if (rcd->rcvhdrq) {
921 dma_free_coherent(&dd->pcidev->dev, rcd->rcvhdrq_size,
922 rcd->rcvhdrq, rcd->rcvhdrq_phys);
923 rcd->rcvhdrq = NULL;
924 if (rcd->rcvhdrtail_kvaddr) {
925 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
926 rcd->rcvhdrtail_kvaddr,
927 rcd->rcvhdrqtailaddr_phys);
928 rcd->rcvhdrtail_kvaddr = NULL;
929 }
930 }
931 if (rcd->rcvegrbuf) {
932 unsigned e;
933
934 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
935 void *base = rcd->rcvegrbuf[e];
936 size_t size = rcd->rcvegrbuf_size;
937
938 dma_free_coherent(&dd->pcidev->dev, size,
939 base, rcd->rcvegrbuf_phys[e]);
940 }
941 kfree(rcd->rcvegrbuf);
942 rcd->rcvegrbuf = NULL;
943 kfree(rcd->rcvegrbuf_phys);
944 rcd->rcvegrbuf_phys = NULL;
945 rcd->rcvegrbuf_chunks = 0;
946 }
947
948 kfree(rcd->tid_pg_list);
949 vfree(rcd->user_event_mask);
950 vfree(rcd->subctxt_uregbase);
951 vfree(rcd->subctxt_rcvegrbuf);
952 vfree(rcd->subctxt_rcvhdr_base);
953#ifdef CONFIG_DEBUG_FS
954 kfree(rcd->opstats);
955 rcd->opstats = NULL;
956#endif
957 kfree(rcd);
958}
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973static void qib_verify_pioperf(struct qib_devdata *dd)
974{
975 u32 pbnum, cnt, lcnt;
976 u32 __iomem *piobuf;
977 u32 *addr;
978 u64 msecs, emsecs;
979
980 piobuf = dd->f_getsendbuf(dd->pport, 0ULL, &pbnum);
981 if (!piobuf) {
982 qib_devinfo(dd->pcidev,
983 "No PIObufs for checking perf, skipping\n");
984 return;
985 }
986
987
988
989
990
991 cnt = 1024;
992
993 addr = vmalloc(cnt);
994 if (!addr)
995 goto done;
996
997 preempt_disable();
998 msecs = 1 + jiffies_to_msecs(jiffies);
999 for (lcnt = 0; lcnt < 10000U; lcnt++) {
1000
1001 if (jiffies_to_msecs(jiffies) >= msecs)
1002 break;
1003 udelay(1);
1004 }
1005
1006 dd->f_set_armlaunch(dd, 0);
1007
1008
1009
1010
1011 writeq(0, piobuf);
1012 qib_flush_wc();
1013
1014
1015
1016
1017
1018
1019 msecs = jiffies_to_msecs(jiffies);
1020 for (emsecs = lcnt = 0; emsecs <= 5UL; lcnt++) {
1021 qib_pio_copy(piobuf + 64, addr, cnt >> 2);
1022 emsecs = jiffies_to_msecs(jiffies) - msecs;
1023 }
1024
1025
1026 if (lcnt < (emsecs * 1024U))
1027 qib_dev_err(dd,
1028 "Performance problem: bandwidth to PIO buffers is only %u MiB/sec\n",
1029 lcnt / (u32) emsecs);
1030
1031 preempt_enable();
1032
1033 vfree(addr);
1034
1035done:
1036
1037 dd->f_sendctrl(dd->pport, QIB_SENDCTRL_DISARM_BUF(pbnum));
1038 qib_sendbuf_done(dd, pbnum);
1039 dd->f_set_armlaunch(dd, 1);
1040}
1041
1042void qib_free_devdata(struct qib_devdata *dd)
1043{
1044 unsigned long flags;
1045
1046 spin_lock_irqsave(&qib_devs_lock, flags);
1047 idr_remove(&qib_unit_table, dd->unit);
1048 list_del(&dd->list);
1049 spin_unlock_irqrestore(&qib_devs_lock, flags);
1050
1051#ifdef CONFIG_DEBUG_FS
1052 qib_dbg_ibdev_exit(&dd->verbs_dev);
1053#endif
1054 free_percpu(dd->int_counter);
1055 rvt_dealloc_device(&dd->verbs_dev.rdi);
1056}
1057
1058u64 qib_int_counter(struct qib_devdata *dd)
1059{
1060 int cpu;
1061 u64 int_counter = 0;
1062
1063 for_each_possible_cpu(cpu)
1064 int_counter += *per_cpu_ptr(dd->int_counter, cpu);
1065 return int_counter;
1066}
1067
1068u64 qib_sps_ints(void)
1069{
1070 unsigned long flags;
1071 struct qib_devdata *dd;
1072 u64 sps_ints = 0;
1073
1074 spin_lock_irqsave(&qib_devs_lock, flags);
1075 list_for_each_entry(dd, &qib_dev_list, list) {
1076 sps_ints += qib_int_counter(dd);
1077 }
1078 spin_unlock_irqrestore(&qib_devs_lock, flags);
1079 return sps_ints;
1080}
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra)
1091{
1092 unsigned long flags;
1093 struct qib_devdata *dd;
1094 int ret, nports;
1095
1096
1097 nports = extra / sizeof(struct qib_pportdata);
1098 dd = (struct qib_devdata *)rvt_alloc_device(sizeof(*dd) + extra,
1099 nports);
1100 if (!dd)
1101 return ERR_PTR(-ENOMEM);
1102
1103 INIT_LIST_HEAD(&dd->list);
1104
1105 idr_preload(GFP_KERNEL);
1106 spin_lock_irqsave(&qib_devs_lock, flags);
1107
1108 ret = idr_alloc(&qib_unit_table, dd, 0, 0, GFP_NOWAIT);
1109 if (ret >= 0) {
1110 dd->unit = ret;
1111 list_add(&dd->list, &qib_dev_list);
1112 }
1113
1114 spin_unlock_irqrestore(&qib_devs_lock, flags);
1115 idr_preload_end();
1116
1117 if (ret < 0) {
1118 qib_early_err(&pdev->dev,
1119 "Could not allocate unit ID: error %d\n", -ret);
1120 goto bail;
1121 }
1122 rvt_set_ibdev_name(&dd->verbs_dev.rdi, "%s%d", "qib", dd->unit);
1123
1124 dd->int_counter = alloc_percpu(u64);
1125 if (!dd->int_counter) {
1126 ret = -ENOMEM;
1127 qib_early_err(&pdev->dev,
1128 "Could not allocate per-cpu int_counter\n");
1129 goto bail;
1130 }
1131
1132 if (!qib_cpulist_count) {
1133 u32 count = num_online_cpus();
1134
1135 qib_cpulist = kzalloc(BITS_TO_LONGS(count) *
1136 sizeof(long), GFP_KERNEL);
1137 if (qib_cpulist)
1138 qib_cpulist_count = count;
1139 }
1140#ifdef CONFIG_DEBUG_FS
1141 qib_dbg_ibdev_init(&dd->verbs_dev);
1142#endif
1143 return dd;
1144bail:
1145 if (!list_empty(&dd->list))
1146 list_del_init(&dd->list);
1147 rvt_dealloc_device(&dd->verbs_dev.rdi);
1148 return ERR_PTR(ret);
1149}
1150
1151
1152
1153
1154
1155
1156void qib_disable_after_error(struct qib_devdata *dd)
1157{
1158 if (dd->flags & QIB_INITTED) {
1159 u32 pidx;
1160
1161 dd->flags &= ~QIB_INITTED;
1162 if (dd->pport)
1163 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1164 struct qib_pportdata *ppd;
1165
1166 ppd = dd->pport + pidx;
1167 if (dd->flags & QIB_PRESENT) {
1168 qib_set_linkstate(ppd,
1169 QIB_IB_LINKDOWN_DISABLE);
1170 dd->f_setextled(ppd, 0);
1171 }
1172 *ppd->statusp &= ~QIB_STATUS_IB_READY;
1173 }
1174 }
1175
1176
1177
1178
1179
1180
1181 if (dd->devstatusp)
1182 *dd->devstatusp |= QIB_STATUS_HWERROR;
1183}
1184
1185static void qib_remove_one(struct pci_dev *);
1186static int qib_init_one(struct pci_dev *, const struct pci_device_id *);
1187
1188#define DRIVER_LOAD_MSG "Intel " QIB_DRV_NAME " loaded: "
1189#define PFX QIB_DRV_NAME ": "
1190
1191static const struct pci_device_id qib_pci_tbl[] = {
1192 { PCI_DEVICE(PCI_VENDOR_ID_PATHSCALE, PCI_DEVICE_ID_QLOGIC_IB_6120) },
1193 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7220) },
1194 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_IB_7322) },
1195 { 0, }
1196};
1197
1198MODULE_DEVICE_TABLE(pci, qib_pci_tbl);
1199
1200static struct pci_driver qib_driver = {
1201 .name = QIB_DRV_NAME,
1202 .probe = qib_init_one,
1203 .remove = qib_remove_one,
1204 .id_table = qib_pci_tbl,
1205 .err_handler = &qib_pci_err_handler,
1206};
1207
1208#ifdef CONFIG_INFINIBAND_QIB_DCA
1209
1210static int qib_notify_dca(struct notifier_block *, unsigned long, void *);
1211static struct notifier_block dca_notifier = {
1212 .notifier_call = qib_notify_dca,
1213 .next = NULL,
1214 .priority = 0
1215};
1216
1217static int qib_notify_dca_device(struct device *device, void *data)
1218{
1219 struct qib_devdata *dd = dev_get_drvdata(device);
1220 unsigned long event = *(unsigned long *)data;
1221
1222 return dd->f_notify_dca(dd, event);
1223}
1224
1225static int qib_notify_dca(struct notifier_block *nb, unsigned long event,
1226 void *p)
1227{
1228 int rval;
1229
1230 rval = driver_for_each_device(&qib_driver.driver, NULL,
1231 &event, qib_notify_dca_device);
1232 return rval ? NOTIFY_BAD : NOTIFY_DONE;
1233}
1234
1235#endif
1236
1237
1238
1239
1240
1241static int __init qib_ib_init(void)
1242{
1243 int ret;
1244
1245 ret = qib_dev_init();
1246 if (ret)
1247 goto bail;
1248
1249
1250
1251
1252
1253 idr_init(&qib_unit_table);
1254
1255#ifdef CONFIG_INFINIBAND_QIB_DCA
1256 dca_register_notify(&dca_notifier);
1257#endif
1258#ifdef CONFIG_DEBUG_FS
1259 qib_dbg_init();
1260#endif
1261 ret = pci_register_driver(&qib_driver);
1262 if (ret < 0) {
1263 pr_err("Unable to register driver: error %d\n", -ret);
1264 goto bail_dev;
1265 }
1266
1267
1268 if (qib_init_qibfs())
1269 pr_err("Unable to register ipathfs\n");
1270 goto bail;
1271
1272bail_dev:
1273#ifdef CONFIG_INFINIBAND_QIB_DCA
1274 dca_unregister_notify(&dca_notifier);
1275#endif
1276#ifdef CONFIG_DEBUG_FS
1277 qib_dbg_exit();
1278#endif
1279 idr_destroy(&qib_unit_table);
1280 qib_dev_cleanup();
1281bail:
1282 return ret;
1283}
1284
1285module_init(qib_ib_init);
1286
1287
1288
1289
1290static void __exit qib_ib_cleanup(void)
1291{
1292 int ret;
1293
1294 ret = qib_exit_qibfs();
1295 if (ret)
1296 pr_err(
1297 "Unable to cleanup counter filesystem: error %d\n",
1298 -ret);
1299
1300#ifdef CONFIG_INFINIBAND_QIB_DCA
1301 dca_unregister_notify(&dca_notifier);
1302#endif
1303 pci_unregister_driver(&qib_driver);
1304#ifdef CONFIG_DEBUG_FS
1305 qib_dbg_exit();
1306#endif
1307
1308 qib_cpulist_count = 0;
1309 kfree(qib_cpulist);
1310
1311 idr_destroy(&qib_unit_table);
1312 qib_dev_cleanup();
1313}
1314
1315module_exit(qib_ib_cleanup);
1316
1317
1318static void cleanup_device_data(struct qib_devdata *dd)
1319{
1320 int ctxt;
1321 int pidx;
1322 struct qib_ctxtdata **tmp;
1323 unsigned long flags;
1324
1325
1326 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1327 if (dd->pport[pidx].statusp)
1328 *dd->pport[pidx].statusp &= ~QIB_STATUS_CHIP_PRESENT;
1329
1330 spin_lock(&dd->pport[pidx].cc_shadow_lock);
1331
1332 kfree(dd->pport[pidx].congestion_entries);
1333 dd->pport[pidx].congestion_entries = NULL;
1334 kfree(dd->pport[pidx].ccti_entries);
1335 dd->pport[pidx].ccti_entries = NULL;
1336 kfree(dd->pport[pidx].ccti_entries_shadow);
1337 dd->pport[pidx].ccti_entries_shadow = NULL;
1338 kfree(dd->pport[pidx].congestion_entries_shadow);
1339 dd->pport[pidx].congestion_entries_shadow = NULL;
1340
1341 spin_unlock(&dd->pport[pidx].cc_shadow_lock);
1342 }
1343
1344 qib_disable_wc(dd);
1345
1346 if (dd->pioavailregs_dma) {
1347 dma_free_coherent(&dd->pcidev->dev, PAGE_SIZE,
1348 (void *) dd->pioavailregs_dma,
1349 dd->pioavailregs_phys);
1350 dd->pioavailregs_dma = NULL;
1351 }
1352
1353 if (dd->pageshadow) {
1354 struct page **tmpp = dd->pageshadow;
1355 dma_addr_t *tmpd = dd->physshadow;
1356 int i;
1357
1358 for (ctxt = 0; ctxt < dd->cfgctxts; ctxt++) {
1359 int ctxt_tidbase = ctxt * dd->rcvtidcnt;
1360 int maxtid = ctxt_tidbase + dd->rcvtidcnt;
1361
1362 for (i = ctxt_tidbase; i < maxtid; i++) {
1363 if (!tmpp[i])
1364 continue;
1365 pci_unmap_page(dd->pcidev, tmpd[i],
1366 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1367 qib_release_user_pages(&tmpp[i], 1);
1368 tmpp[i] = NULL;
1369 }
1370 }
1371
1372 dd->pageshadow = NULL;
1373 vfree(tmpp);
1374 dd->physshadow = NULL;
1375 vfree(tmpd);
1376 }
1377
1378
1379
1380
1381
1382
1383
1384
1385 spin_lock_irqsave(&dd->uctxt_lock, flags);
1386 tmp = dd->rcd;
1387 dd->rcd = NULL;
1388 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
1389 for (ctxt = 0; tmp && ctxt < dd->ctxtcnt; ctxt++) {
1390 struct qib_ctxtdata *rcd = tmp[ctxt];
1391
1392 tmp[ctxt] = NULL;
1393 qib_free_ctxtdata(dd, rcd);
1394 }
1395 kfree(tmp);
1396}
1397
1398
1399
1400
1401
1402static void qib_postinit_cleanup(struct qib_devdata *dd)
1403{
1404
1405
1406
1407
1408
1409
1410
1411 if (dd->f_cleanup)
1412 dd->f_cleanup(dd);
1413
1414 qib_pcie_ddcleanup(dd);
1415
1416 cleanup_device_data(dd);
1417
1418 qib_free_devdata(dd);
1419}
1420
1421static int qib_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1422{
1423 int ret, j, pidx, initfail;
1424 struct qib_devdata *dd = NULL;
1425
1426 ret = qib_pcie_init(pdev, ent);
1427 if (ret)
1428 goto bail;
1429
1430
1431
1432
1433
1434 switch (ent->device) {
1435 case PCI_DEVICE_ID_QLOGIC_IB_6120:
1436#ifdef CONFIG_PCI_MSI
1437 dd = qib_init_iba6120_funcs(pdev, ent);
1438#else
1439 qib_early_err(&pdev->dev,
1440 "Intel PCIE device 0x%x cannot work if CONFIG_PCI_MSI is not enabled\n",
1441 ent->device);
1442 dd = ERR_PTR(-ENODEV);
1443#endif
1444 break;
1445
1446 case PCI_DEVICE_ID_QLOGIC_IB_7220:
1447 dd = qib_init_iba7220_funcs(pdev, ent);
1448 break;
1449
1450 case PCI_DEVICE_ID_QLOGIC_IB_7322:
1451 dd = qib_init_iba7322_funcs(pdev, ent);
1452 break;
1453
1454 default:
1455 qib_early_err(&pdev->dev,
1456 "Failing on unknown Intel deviceid 0x%x\n",
1457 ent->device);
1458 ret = -ENODEV;
1459 }
1460
1461 if (IS_ERR(dd))
1462 ret = PTR_ERR(dd);
1463 if (ret)
1464 goto bail;
1465
1466 ret = qib_create_workqueues(dd);
1467 if (ret)
1468 goto bail;
1469
1470
1471 initfail = qib_init(dd, 0);
1472
1473 ret = qib_register_ib_device(dd);
1474
1475
1476
1477
1478
1479
1480
1481 if (!qib_mini_init && !initfail && !ret)
1482 dd->flags |= QIB_INITTED;
1483
1484 j = qib_device_create(dd);
1485 if (j)
1486 qib_dev_err(dd, "Failed to create /dev devices: %d\n", -j);
1487 j = qibfs_add(dd);
1488 if (j)
1489 qib_dev_err(dd, "Failed filesystem setup for counters: %d\n",
1490 -j);
1491
1492 if (qib_mini_init || initfail || ret) {
1493 qib_stop_timers(dd);
1494 flush_workqueue(ib_wq);
1495 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1496 dd->f_quiet_serdes(dd->pport + pidx);
1497 if (qib_mini_init)
1498 goto bail;
1499 if (!j) {
1500 (void) qibfs_remove(dd);
1501 qib_device_remove(dd);
1502 }
1503 if (!ret)
1504 qib_unregister_ib_device(dd);
1505 qib_postinit_cleanup(dd);
1506 if (initfail)
1507 ret = initfail;
1508 goto bail;
1509 }
1510
1511 ret = qib_enable_wc(dd);
1512 if (ret) {
1513 qib_dev_err(dd,
1514 "Write combining not enabled (err %d): performance may be poor\n",
1515 -ret);
1516 ret = 0;
1517 }
1518
1519 qib_verify_pioperf(dd);
1520bail:
1521 return ret;
1522}
1523
1524static void qib_remove_one(struct pci_dev *pdev)
1525{
1526 struct qib_devdata *dd = pci_get_drvdata(pdev);
1527 int ret;
1528
1529
1530 qib_unregister_ib_device(dd);
1531
1532
1533
1534
1535
1536 if (!qib_mini_init)
1537 qib_shutdown_device(dd);
1538
1539 qib_stop_timers(dd);
1540
1541
1542 flush_workqueue(ib_wq);
1543
1544 ret = qibfs_remove(dd);
1545 if (ret)
1546 qib_dev_err(dd, "Failed counters filesystem cleanup: %d\n",
1547 -ret);
1548
1549 qib_device_remove(dd);
1550
1551 qib_postinit_cleanup(dd);
1552}
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563int qib_create_rcvhdrq(struct qib_devdata *dd, struct qib_ctxtdata *rcd)
1564{
1565 unsigned amt;
1566 int old_node_id;
1567
1568 if (!rcd->rcvhdrq) {
1569 dma_addr_t phys_hdrqtail;
1570 gfp_t gfp_flags;
1571
1572 amt = ALIGN(dd->rcvhdrcnt * dd->rcvhdrentsize *
1573 sizeof(u32), PAGE_SIZE);
1574 gfp_flags = (rcd->ctxt >= dd->first_user_ctxt) ?
1575 GFP_USER : GFP_KERNEL;
1576
1577 old_node_id = dev_to_node(&dd->pcidev->dev);
1578 set_dev_node(&dd->pcidev->dev, rcd->node_id);
1579 rcd->rcvhdrq = dma_alloc_coherent(
1580 &dd->pcidev->dev, amt, &rcd->rcvhdrq_phys,
1581 gfp_flags | __GFP_COMP);
1582 set_dev_node(&dd->pcidev->dev, old_node_id);
1583
1584 if (!rcd->rcvhdrq) {
1585 qib_dev_err(dd,
1586 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1587 amt, rcd->ctxt);
1588 goto bail;
1589 }
1590
1591 if (rcd->ctxt >= dd->first_user_ctxt) {
1592 rcd->user_event_mask = vmalloc_user(PAGE_SIZE);
1593 if (!rcd->user_event_mask)
1594 goto bail_free_hdrq;
1595 }
1596
1597 if (!(dd->flags & QIB_NODMA_RTAIL)) {
1598 set_dev_node(&dd->pcidev->dev, rcd->node_id);
1599 rcd->rcvhdrtail_kvaddr = dma_alloc_coherent(
1600 &dd->pcidev->dev, PAGE_SIZE, &phys_hdrqtail,
1601 gfp_flags);
1602 set_dev_node(&dd->pcidev->dev, old_node_id);
1603 if (!rcd->rcvhdrtail_kvaddr)
1604 goto bail_free;
1605 rcd->rcvhdrqtailaddr_phys = phys_hdrqtail;
1606 }
1607
1608 rcd->rcvhdrq_size = amt;
1609 }
1610
1611
1612 memset(rcd->rcvhdrq, 0, rcd->rcvhdrq_size);
1613 if (rcd->rcvhdrtail_kvaddr)
1614 memset(rcd->rcvhdrtail_kvaddr, 0, PAGE_SIZE);
1615 return 0;
1616
1617bail_free:
1618 qib_dev_err(dd,
1619 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1620 rcd->ctxt);
1621 vfree(rcd->user_event_mask);
1622 rcd->user_event_mask = NULL;
1623bail_free_hdrq:
1624 dma_free_coherent(&dd->pcidev->dev, amt, rcd->rcvhdrq,
1625 rcd->rcvhdrq_phys);
1626 rcd->rcvhdrq = NULL;
1627bail:
1628 return -ENOMEM;
1629}
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640int qib_setup_eagerbufs(struct qib_ctxtdata *rcd)
1641{
1642 struct qib_devdata *dd = rcd->dd;
1643 unsigned e, egrcnt, egrperchunk, chunk, egrsize, egroff;
1644 size_t size;
1645 gfp_t gfp_flags;
1646 int old_node_id;
1647
1648
1649
1650
1651
1652
1653
1654 gfp_flags = __GFP_RECLAIM | __GFP_IO | __GFP_COMP;
1655
1656 egrcnt = rcd->rcvegrcnt;
1657 egroff = rcd->rcvegr_tid_base;
1658 egrsize = dd->rcvegrbufsize;
1659
1660 chunk = rcd->rcvegrbuf_chunks;
1661 egrperchunk = rcd->rcvegrbufs_perchunk;
1662 size = rcd->rcvegrbuf_size;
1663 if (!rcd->rcvegrbuf) {
1664 rcd->rcvegrbuf =
1665 kzalloc_node(chunk * sizeof(rcd->rcvegrbuf[0]),
1666 GFP_KERNEL, rcd->node_id);
1667 if (!rcd->rcvegrbuf)
1668 goto bail;
1669 }
1670 if (!rcd->rcvegrbuf_phys) {
1671 rcd->rcvegrbuf_phys =
1672 kmalloc_array_node(chunk,
1673 sizeof(rcd->rcvegrbuf_phys[0]),
1674 GFP_KERNEL, rcd->node_id);
1675 if (!rcd->rcvegrbuf_phys)
1676 goto bail_rcvegrbuf;
1677 }
1678 for (e = 0; e < rcd->rcvegrbuf_chunks; e++) {
1679 if (rcd->rcvegrbuf[e])
1680 continue;
1681
1682 old_node_id = dev_to_node(&dd->pcidev->dev);
1683 set_dev_node(&dd->pcidev->dev, rcd->node_id);
1684 rcd->rcvegrbuf[e] =
1685 dma_alloc_coherent(&dd->pcidev->dev, size,
1686 &rcd->rcvegrbuf_phys[e],
1687 gfp_flags);
1688 set_dev_node(&dd->pcidev->dev, old_node_id);
1689 if (!rcd->rcvegrbuf[e])
1690 goto bail_rcvegrbuf_phys;
1691 }
1692
1693 rcd->rcvegr_phys = rcd->rcvegrbuf_phys[0];
1694
1695 for (e = chunk = 0; chunk < rcd->rcvegrbuf_chunks; chunk++) {
1696 dma_addr_t pa = rcd->rcvegrbuf_phys[chunk];
1697 unsigned i;
1698
1699
1700 memset(rcd->rcvegrbuf[chunk], 0, size);
1701
1702 for (i = 0; e < egrcnt && i < egrperchunk; e++, i++) {
1703 dd->f_put_tid(dd, e + egroff +
1704 (u64 __iomem *)
1705 ((char __iomem *)
1706 dd->kregbase +
1707 dd->rcvegrbase),
1708 RCVHQ_RCV_TYPE_EAGER, pa);
1709 pa += egrsize;
1710 }
1711 cond_resched();
1712 }
1713
1714 return 0;
1715
1716bail_rcvegrbuf_phys:
1717 for (e = 0; e < rcd->rcvegrbuf_chunks && rcd->rcvegrbuf[e]; e++)
1718 dma_free_coherent(&dd->pcidev->dev, size,
1719 rcd->rcvegrbuf[e], rcd->rcvegrbuf_phys[e]);
1720 kfree(rcd->rcvegrbuf_phys);
1721 rcd->rcvegrbuf_phys = NULL;
1722bail_rcvegrbuf:
1723 kfree(rcd->rcvegrbuf);
1724 rcd->rcvegrbuf = NULL;
1725bail:
1726 return -ENOMEM;
1727}
1728
1729
1730
1731
1732
1733
1734
1735int init_chip_wc_pat(struct qib_devdata *dd, u32 vl15buflen)
1736{
1737 u64 __iomem *qib_kregbase = NULL;
1738 void __iomem *qib_piobase = NULL;
1739 u64 __iomem *qib_userbase = NULL;
1740 u64 qib_kreglen;
1741 u64 qib_pio2koffset = dd->piobufbase & 0xffffffff;
1742 u64 qib_pio4koffset = dd->piobufbase >> 32;
1743 u64 qib_pio2klen = dd->piobcnt2k * dd->palign;
1744 u64 qib_pio4klen = dd->piobcnt4k * dd->align4k;
1745 u64 qib_physaddr = dd->physaddr;
1746 u64 qib_piolen;
1747 u64 qib_userlen = 0;
1748
1749
1750
1751
1752
1753
1754 iounmap(dd->kregbase);
1755 dd->kregbase = NULL;
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766 if (dd->piobcnt4k == 0) {
1767 qib_kreglen = qib_pio2koffset;
1768 qib_piolen = qib_pio2klen;
1769 } else if (qib_pio2koffset < qib_pio4koffset) {
1770 qib_kreglen = qib_pio2koffset;
1771 qib_piolen = qib_pio4koffset + qib_pio4klen - qib_kreglen;
1772 } else {
1773 qib_kreglen = qib_pio4koffset;
1774 qib_piolen = qib_pio2koffset + qib_pio2klen - qib_kreglen;
1775 }
1776 qib_piolen += vl15buflen;
1777
1778 if (dd->uregbase > qib_kreglen)
1779 qib_userlen = dd->ureg_align * dd->cfgctxts;
1780
1781
1782 qib_kregbase = ioremap_nocache(qib_physaddr, qib_kreglen);
1783 if (!qib_kregbase)
1784 goto bail;
1785
1786 qib_piobase = ioremap_wc(qib_physaddr + qib_kreglen, qib_piolen);
1787 if (!qib_piobase)
1788 goto bail_kregbase;
1789
1790 if (qib_userlen) {
1791 qib_userbase = ioremap_nocache(qib_physaddr + dd->uregbase,
1792 qib_userlen);
1793 if (!qib_userbase)
1794 goto bail_piobase;
1795 }
1796
1797 dd->kregbase = qib_kregbase;
1798 dd->kregend = (u64 __iomem *)
1799 ((char __iomem *) qib_kregbase + qib_kreglen);
1800 dd->piobase = qib_piobase;
1801 dd->pio2kbase = (void __iomem *)
1802 (((char __iomem *) dd->piobase) +
1803 qib_pio2koffset - qib_kreglen);
1804 if (dd->piobcnt4k)
1805 dd->pio4kbase = (void __iomem *)
1806 (((char __iomem *) dd->piobase) +
1807 qib_pio4koffset - qib_kreglen);
1808 if (qib_userlen)
1809
1810 dd->userbase = qib_userbase;
1811 return 0;
1812
1813bail_piobase:
1814 iounmap(qib_piobase);
1815bail_kregbase:
1816 iounmap(qib_kregbase);
1817bail:
1818 return -ENOMEM;
1819}
1820