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17#include "mn88472_priv.h"
18
19static int mn88472_get_tune_settings(struct dvb_frontend *fe,
20 struct dvb_frontend_tune_settings *s)
21{
22 s->min_delay_ms = 1000;
23 return 0;
24}
25
26static int mn88472_read_status(struct dvb_frontend *fe, enum fe_status *status)
27{
28 struct i2c_client *client = fe->demodulator_priv;
29 struct mn88472_dev *dev = i2c_get_clientdata(client);
30 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
31 int ret, i, stmp;
32 unsigned int utmp, utmp1, utmp2;
33 u8 buf[5];
34
35 if (!dev->active) {
36 ret = -EAGAIN;
37 goto err;
38 }
39
40 switch (c->delivery_system) {
41 case SYS_DVBT:
42 ret = regmap_read(dev->regmap[0], 0x7f, &utmp);
43 if (ret)
44 goto err;
45 if ((utmp & 0x0f) >= 0x09)
46 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
47 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
48 else
49 *status = 0;
50 break;
51 case SYS_DVBT2:
52 ret = regmap_read(dev->regmap[2], 0x92, &utmp);
53 if (ret)
54 goto err;
55 if ((utmp & 0x0f) >= 0x0d)
56 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
57 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
58 else if ((utmp & 0x0f) >= 0x0a)
59 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
60 FE_HAS_VITERBI;
61 else if ((utmp & 0x0f) >= 0x07)
62 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER;
63 else
64 *status = 0;
65 break;
66 case SYS_DVBC_ANNEX_A:
67 ret = regmap_read(dev->regmap[1], 0x84, &utmp);
68 if (ret)
69 goto err;
70 if ((utmp & 0x0f) >= 0x08)
71 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
72 FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
73 else
74 *status = 0;
75 break;
76 default:
77 ret = -EINVAL;
78 goto err;
79 }
80
81
82 if (*status & FE_HAS_SIGNAL) {
83 for (i = 0; i < 2; i++) {
84 ret = regmap_bulk_read(dev->regmap[2], 0x8e + i,
85 &buf[i], 1);
86 if (ret)
87 goto err;
88 }
89
90 utmp1 = buf[0] << 8 | buf[1] << 0 | buf[0] >> 2;
91 dev_dbg(&client->dev, "strength=%u\n", utmp1);
92
93 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
94 c->strength.stat[0].uvalue = utmp1;
95 } else {
96 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
97 }
98
99
100 if (*status & FE_HAS_VITERBI && c->delivery_system == SYS_DVBT) {
101
102 ret = regmap_bulk_read(dev->regmap[0], 0x9c, buf, 2);
103 if (ret)
104 goto err;
105
106 utmp = buf[0] << 8 | buf[1] << 0;
107 if (utmp) {
108
109
110 stmp = ((u64)80807124 - intlog10(utmp) + 3355443)
111 * 10000 >> 24;
112
113 dev_dbg(&client->dev, "cnr=%d value=%u\n", stmp, utmp);
114 } else {
115 stmp = 0;
116 }
117
118 c->cnr.stat[0].svalue = stmp;
119 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
120 } else if (*status & FE_HAS_VITERBI &&
121 c->delivery_system == SYS_DVBT2) {
122
123 for (i = 0; i < 3; i++) {
124 ret = regmap_bulk_read(dev->regmap[2], 0xbc + i,
125 &buf[i], 1);
126 if (ret)
127 goto err;
128 }
129
130 utmp = buf[1] << 8 | buf[2] << 0;
131 utmp1 = (buf[0] >> 2) & 0x01;
132 if (utmp) {
133 if (utmp1) {
134
135
136 stmp = ((u64)70706234 - intlog10(utmp)
137 - 10066330) * 10000 >> 24;
138 dev_dbg(&client->dev, "cnr=%d value=%u MISO\n",
139 stmp, utmp);
140 } else {
141
142
143 stmp = ((u64)80807124 - intlog10(utmp)
144 + 3355443) * 10000 >> 24;
145
146 dev_dbg(&client->dev, "cnr=%d value=%u SISO\n",
147 stmp, utmp);
148 }
149 } else {
150 stmp = 0;
151 }
152
153 c->cnr.stat[0].svalue = stmp;
154 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
155 } else if (*status & FE_HAS_VITERBI &&
156 c->delivery_system == SYS_DVBC_ANNEX_A) {
157
158 ret = regmap_bulk_read(dev->regmap[1], 0xa1, buf, 4);
159 if (ret)
160 goto err;
161
162 utmp1 = buf[0] << 8 | buf[1] << 0;
163 utmp2 = buf[2] << 8 | buf[3] << 0;
164 if (utmp1 && utmp2) {
165
166
167 stmp = ((u64)15151336 + intlog10(utmp1)
168 - intlog10(utmp2)) * 10000 >> 24;
169
170 dev_dbg(&client->dev, "cnr=%d signal=%u noise=%u\n",
171 stmp, utmp1, utmp2);
172 } else {
173 stmp = 0;
174 }
175
176 c->cnr.stat[0].svalue = stmp;
177 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
178 } else {
179 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
180 }
181
182
183 if (*status & FE_HAS_SYNC) {
184 ret = regmap_bulk_read(dev->regmap[0], 0xe1, buf, 4);
185 if (ret)
186 goto err;
187
188 utmp1 = buf[0] << 8 | buf[1] << 0;
189 utmp2 = buf[2] << 8 | buf[3] << 0;
190 dev_dbg(&client->dev, "block_error=%u block_count=%u\n",
191 utmp1, utmp2);
192
193 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
194 c->block_error.stat[0].uvalue += utmp1;
195 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
196 c->block_count.stat[0].uvalue += utmp2;
197 } else {
198 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
199 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
200 }
201
202 return 0;
203err:
204 dev_dbg(&client->dev, "failed=%d\n", ret);
205 return ret;
206}
207
208static int mn88472_set_frontend(struct dvb_frontend *fe)
209{
210 struct i2c_client *client = fe->demodulator_priv;
211 struct mn88472_dev *dev = i2c_get_clientdata(client);
212 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
213 int ret, i;
214 unsigned int utmp;
215 u32 if_frequency;
216 u8 buf[3], delivery_system_val, bandwidth_val, *bandwidth_vals_ptr;
217 u8 reg_bank0_b4_val, reg_bank0_cd_val, reg_bank0_d4_val;
218 u8 reg_bank0_d6_val;
219
220 dev_dbg(&client->dev,
221 "delivery_system=%u modulation=%u frequency=%u bandwidth_hz=%u symbol_rate=%u inversion=%d stream_id=%d\n",
222 c->delivery_system, c->modulation, c->frequency,
223 c->bandwidth_hz, c->symbol_rate, c->inversion, c->stream_id);
224
225 if (!dev->active) {
226 ret = -EAGAIN;
227 goto err;
228 }
229
230 switch (c->delivery_system) {
231 case SYS_DVBT:
232 delivery_system_val = 0x02;
233 reg_bank0_b4_val = 0x00;
234 reg_bank0_cd_val = 0x1f;
235 reg_bank0_d4_val = 0x0a;
236 reg_bank0_d6_val = 0x48;
237 break;
238 case SYS_DVBT2:
239 delivery_system_val = 0x03;
240 reg_bank0_b4_val = 0xf6;
241 reg_bank0_cd_val = 0x01;
242 reg_bank0_d4_val = 0x09;
243 reg_bank0_d6_val = 0x46;
244 break;
245 case SYS_DVBC_ANNEX_A:
246 delivery_system_val = 0x04;
247 reg_bank0_b4_val = 0x00;
248 reg_bank0_cd_val = 0x17;
249 reg_bank0_d4_val = 0x09;
250 reg_bank0_d6_val = 0x48;
251 break;
252 default:
253 ret = -EINVAL;
254 goto err;
255 }
256
257 switch (c->delivery_system) {
258 case SYS_DVBT:
259 case SYS_DVBT2:
260 switch (c->bandwidth_hz) {
261 case 5000000:
262 bandwidth_vals_ptr = "\xe5\x99\x9a\x1b\xa9\x1b\xa9";
263 bandwidth_val = 0x03;
264 break;
265 case 6000000:
266 bandwidth_vals_ptr = "\xbf\x55\x55\x15\x6b\x15\x6b";
267 bandwidth_val = 0x02;
268 break;
269 case 7000000:
270 bandwidth_vals_ptr = "\xa4\x00\x00\x0f\x2c\x0f\x2c";
271 bandwidth_val = 0x01;
272 break;
273 case 8000000:
274 bandwidth_vals_ptr = "\x8f\x80\x00\x08\xee\x08\xee";
275 bandwidth_val = 0x00;
276 break;
277 default:
278 ret = -EINVAL;
279 goto err;
280 }
281 break;
282 case SYS_DVBC_ANNEX_A:
283 bandwidth_vals_ptr = NULL;
284 bandwidth_val = 0x00;
285 break;
286 default:
287 break;
288 }
289
290
291 if (fe->ops.tuner_ops.set_params) {
292 ret = fe->ops.tuner_ops.set_params(fe);
293 if (ret)
294 goto err;
295 }
296
297 if (fe->ops.tuner_ops.get_if_frequency) {
298 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
299 if (ret)
300 goto err;
301
302 dev_dbg(&client->dev, "get_if_frequency=%d\n", if_frequency);
303 } else {
304 ret = -EINVAL;
305 goto err;
306 }
307
308 ret = regmap_write(dev->regmap[2], 0x00, 0x66);
309 if (ret)
310 goto err;
311 ret = regmap_write(dev->regmap[2], 0x01, 0x00);
312 if (ret)
313 goto err;
314 ret = regmap_write(dev->regmap[2], 0x02, 0x01);
315 if (ret)
316 goto err;
317 ret = regmap_write(dev->regmap[2], 0x03, delivery_system_val);
318 if (ret)
319 goto err;
320 ret = regmap_write(dev->regmap[2], 0x04, bandwidth_val);
321 if (ret)
322 goto err;
323
324
325 utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, dev->clk);
326 buf[0] = (utmp >> 16) & 0xff;
327 buf[1] = (utmp >> 8) & 0xff;
328 buf[2] = (utmp >> 0) & 0xff;
329 for (i = 0; i < 3; i++) {
330 ret = regmap_write(dev->regmap[2], 0x10 + i, buf[i]);
331 if (ret)
332 goto err;
333 }
334
335
336 if (bandwidth_vals_ptr) {
337 for (i = 0; i < 7; i++) {
338 ret = regmap_write(dev->regmap[2], 0x13 + i,
339 bandwidth_vals_ptr[i]);
340 if (ret)
341 goto err;
342 }
343 }
344
345 ret = regmap_write(dev->regmap[0], 0xb4, reg_bank0_b4_val);
346 if (ret)
347 goto err;
348 ret = regmap_write(dev->regmap[0], 0xcd, reg_bank0_cd_val);
349 if (ret)
350 goto err;
351 ret = regmap_write(dev->regmap[0], 0xd4, reg_bank0_d4_val);
352 if (ret)
353 goto err;
354 ret = regmap_write(dev->regmap[0], 0xd6, reg_bank0_d6_val);
355 if (ret)
356 goto err;
357
358 switch (c->delivery_system) {
359 case SYS_DVBT:
360 ret = regmap_write(dev->regmap[0], 0x07, 0x26);
361 if (ret)
362 goto err;
363 ret = regmap_write(dev->regmap[0], 0x00, 0xba);
364 if (ret)
365 goto err;
366 ret = regmap_write(dev->regmap[0], 0x01, 0x13);
367 if (ret)
368 goto err;
369 break;
370 case SYS_DVBT2:
371 ret = regmap_write(dev->regmap[2], 0x2b, 0x13);
372 if (ret)
373 goto err;
374 ret = regmap_write(dev->regmap[2], 0x4f, 0x05);
375 if (ret)
376 goto err;
377 ret = regmap_write(dev->regmap[1], 0xf6, 0x05);
378 if (ret)
379 goto err;
380 ret = regmap_write(dev->regmap[2], 0x32,
381 (c->stream_id == NO_STREAM_ID_FILTER) ? 0 :
382 c->stream_id );
383 if (ret)
384 goto err;
385 break;
386 case SYS_DVBC_ANNEX_A:
387 break;
388 default:
389 break;
390 }
391
392
393 ret = regmap_write(dev->regmap[2], 0xf8, 0x9f);
394 if (ret)
395 goto err;
396
397 return 0;
398err:
399 dev_dbg(&client->dev, "failed=%d\n", ret);
400 return ret;
401}
402
403static int mn88472_init(struct dvb_frontend *fe)
404{
405 struct i2c_client *client = fe->demodulator_priv;
406 struct mn88472_dev *dev = i2c_get_clientdata(client);
407 int ret, len, rem;
408 unsigned int utmp;
409 const struct firmware *firmware;
410 const char *name = MN88472_FIRMWARE;
411
412 dev_dbg(&client->dev, "\n");
413
414
415 ret = regmap_write(dev->regmap[2], 0x05, 0x00);
416 if (ret)
417 goto err;
418 ret = regmap_write(dev->regmap[2], 0x0b, 0x00);
419 if (ret)
420 goto err;
421 ret = regmap_write(dev->regmap[2], 0x0c, 0x00);
422 if (ret)
423 goto err;
424
425
426 ret = regmap_read(dev->regmap[0], 0xf5, &utmp);
427 if (ret)
428 goto err;
429 if (!(utmp & 0x01))
430 goto warm;
431
432 ret = request_firmware(&firmware, name, &client->dev);
433 if (ret) {
434 dev_err(&client->dev, "firmware file '%s' not found\n", name);
435 goto err;
436 }
437
438 dev_info(&client->dev, "downloading firmware from file '%s'\n", name);
439
440 ret = regmap_write(dev->regmap[0], 0xf5, 0x03);
441 if (ret)
442 goto err_release_firmware;
443
444 for (rem = firmware->size; rem > 0; rem -= (dev->i2c_write_max - 1)) {
445 len = min(dev->i2c_write_max - 1, rem);
446 ret = regmap_bulk_write(dev->regmap[0], 0xf6,
447 &firmware->data[firmware->size - rem],
448 len);
449 if (ret) {
450 dev_err(&client->dev, "firmware download failed %d\n",
451 ret);
452 goto err_release_firmware;
453 }
454 }
455
456
457 ret = regmap_read(dev->regmap[0], 0xf8, &utmp);
458 if (ret)
459 goto err_release_firmware;
460 if (utmp & 0x10) {
461 ret = -EINVAL;
462 dev_err(&client->dev, "firmware did not run\n");
463 goto err_release_firmware;
464 }
465
466 ret = regmap_write(dev->regmap[0], 0xf5, 0x00);
467 if (ret)
468 goto err_release_firmware;
469
470 release_firmware(firmware);
471warm:
472
473 switch (dev->ts_mode) {
474 case SERIAL_TS_MODE:
475 utmp = 0x1d;
476 break;
477 case PARALLEL_TS_MODE:
478 utmp = 0x00;
479 break;
480 default:
481 ret = -EINVAL;
482 goto err;
483 }
484 ret = regmap_write(dev->regmap[2], 0x08, utmp);
485 if (ret)
486 goto err;
487
488 switch (dev->ts_clk) {
489 case VARIABLE_TS_CLOCK:
490 utmp = 0xe3;
491 break;
492 case FIXED_TS_CLOCK:
493 utmp = 0xe1;
494 break;
495 default:
496 ret = -EINVAL;
497 goto err;
498 }
499 ret = regmap_write(dev->regmap[0], 0xd9, utmp);
500 if (ret)
501 goto err;
502
503 dev->active = true;
504
505 return 0;
506err_release_firmware:
507 release_firmware(firmware);
508err:
509 dev_dbg(&client->dev, "failed=%d\n", ret);
510 return ret;
511}
512
513static int mn88472_sleep(struct dvb_frontend *fe)
514{
515 struct i2c_client *client = fe->demodulator_priv;
516 struct mn88472_dev *dev = i2c_get_clientdata(client);
517 int ret;
518
519 dev_dbg(&client->dev, "\n");
520
521
522 ret = regmap_write(dev->regmap[2], 0x0c, 0x30);
523 if (ret)
524 goto err;
525 ret = regmap_write(dev->regmap[2], 0x0b, 0x30);
526 if (ret)
527 goto err;
528 ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
529 if (ret)
530 goto err;
531
532 return 0;
533err:
534 dev_dbg(&client->dev, "failed=%d\n", ret);
535 return ret;
536}
537
538static const struct dvb_frontend_ops mn88472_ops = {
539 .delsys = {SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A},
540 .info = {
541 .name = "Panasonic MN88472",
542 .symbol_rate_min = 1000000,
543 .symbol_rate_max = 7200000,
544 .caps = FE_CAN_FEC_1_2 |
545 FE_CAN_FEC_2_3 |
546 FE_CAN_FEC_3_4 |
547 FE_CAN_FEC_5_6 |
548 FE_CAN_FEC_7_8 |
549 FE_CAN_FEC_AUTO |
550 FE_CAN_QPSK |
551 FE_CAN_QAM_16 |
552 FE_CAN_QAM_32 |
553 FE_CAN_QAM_64 |
554 FE_CAN_QAM_128 |
555 FE_CAN_QAM_256 |
556 FE_CAN_QAM_AUTO |
557 FE_CAN_TRANSMISSION_MODE_AUTO |
558 FE_CAN_GUARD_INTERVAL_AUTO |
559 FE_CAN_HIERARCHY_AUTO |
560 FE_CAN_MUTE_TS |
561 FE_CAN_2G_MODULATION |
562 FE_CAN_MULTISTREAM
563 },
564
565 .get_tune_settings = mn88472_get_tune_settings,
566
567 .init = mn88472_init,
568 .sleep = mn88472_sleep,
569
570 .set_frontend = mn88472_set_frontend,
571
572 .read_status = mn88472_read_status,
573};
574
575static struct dvb_frontend *mn88472_get_dvb_frontend(struct i2c_client *client)
576{
577 struct mn88472_dev *dev = i2c_get_clientdata(client);
578
579 dev_dbg(&client->dev, "\n");
580
581 return &dev->fe;
582}
583
584static int mn88472_probe(struct i2c_client *client,
585 const struct i2c_device_id *id)
586{
587 struct mn88472_config *pdata = client->dev.platform_data;
588 struct mn88472_dev *dev;
589 struct dtv_frontend_properties *c;
590 int ret;
591 unsigned int utmp;
592 static const struct regmap_config regmap_config = {
593 .reg_bits = 8,
594 .val_bits = 8,
595 };
596
597 dev_dbg(&client->dev, "\n");
598
599 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
600 if (!dev) {
601 ret = -ENOMEM;
602 goto err;
603 }
604
605 dev->i2c_write_max = pdata->i2c_wr_max ? pdata->i2c_wr_max : ~0;
606 dev->clk = pdata->xtal;
607 dev->ts_mode = pdata->ts_mode;
608 dev->ts_clk = pdata->ts_clock;
609 dev->client[0] = client;
610 dev->regmap[0] = regmap_init_i2c(dev->client[0], ®map_config);
611 if (IS_ERR(dev->regmap[0])) {
612 ret = PTR_ERR(dev->regmap[0]);
613 goto err_kfree;
614 }
615
616
617
618
619
620
621
622
623
624 dev->client[1] = i2c_new_dummy(client->adapter, 0x1a);
625 if (!dev->client[1]) {
626 ret = -ENODEV;
627 dev_err(&client->dev, "I2C registration failed\n");
628 if (ret)
629 goto err_regmap_0_regmap_exit;
630 }
631 dev->regmap[1] = regmap_init_i2c(dev->client[1], ®map_config);
632 if (IS_ERR(dev->regmap[1])) {
633 ret = PTR_ERR(dev->regmap[1]);
634 goto err_client_1_i2c_unregister_device;
635 }
636 i2c_set_clientdata(dev->client[1], dev);
637
638 dev->client[2] = i2c_new_dummy(client->adapter, 0x1c);
639 if (!dev->client[2]) {
640 ret = -ENODEV;
641 dev_err(&client->dev, "2nd I2C registration failed\n");
642 if (ret)
643 goto err_regmap_1_regmap_exit;
644 }
645 dev->regmap[2] = regmap_init_i2c(dev->client[2], ®map_config);
646 if (IS_ERR(dev->regmap[2])) {
647 ret = PTR_ERR(dev->regmap[2]);
648 goto err_client_2_i2c_unregister_device;
649 }
650 i2c_set_clientdata(dev->client[2], dev);
651
652
653 ret = regmap_read(dev->regmap[2], 0xff, &utmp);
654 if (ret)
655 goto err_regmap_2_regmap_exit;
656
657 dev_dbg(&client->dev, "chip id=%02x\n", utmp);
658
659 if (utmp != 0x02) {
660 ret = -ENODEV;
661 goto err_regmap_2_regmap_exit;
662 }
663
664
665 ret = regmap_write(dev->regmap[2], 0x05, 0x3e);
666 if (ret)
667 goto err_regmap_2_regmap_exit;
668
669
670 memcpy(&dev->fe.ops, &mn88472_ops, sizeof(struct dvb_frontend_ops));
671 dev->fe.demodulator_priv = client;
672 *pdata->fe = &dev->fe;
673 i2c_set_clientdata(client, dev);
674
675
676 c = &dev->fe.dtv_property_cache;
677 c->strength.len = 1;
678 c->cnr.len = 1;
679 c->block_error.len = 1;
680 c->block_count.len = 1;
681
682
683 pdata->get_dvb_frontend = mn88472_get_dvb_frontend;
684
685 dev_info(&client->dev, "Panasonic MN88472 successfully identified\n");
686
687 return 0;
688err_regmap_2_regmap_exit:
689 regmap_exit(dev->regmap[2]);
690err_client_2_i2c_unregister_device:
691 i2c_unregister_device(dev->client[2]);
692err_regmap_1_regmap_exit:
693 regmap_exit(dev->regmap[1]);
694err_client_1_i2c_unregister_device:
695 i2c_unregister_device(dev->client[1]);
696err_regmap_0_regmap_exit:
697 regmap_exit(dev->regmap[0]);
698err_kfree:
699 kfree(dev);
700err:
701 dev_dbg(&client->dev, "failed=%d\n", ret);
702 return ret;
703}
704
705static int mn88472_remove(struct i2c_client *client)
706{
707 struct mn88472_dev *dev = i2c_get_clientdata(client);
708
709 dev_dbg(&client->dev, "\n");
710
711 regmap_exit(dev->regmap[2]);
712 i2c_unregister_device(dev->client[2]);
713
714 regmap_exit(dev->regmap[1]);
715 i2c_unregister_device(dev->client[1]);
716
717 regmap_exit(dev->regmap[0]);
718
719 kfree(dev);
720
721 return 0;
722}
723
724static const struct i2c_device_id mn88472_id_table[] = {
725 {"mn88472", 0},
726 {}
727};
728MODULE_DEVICE_TABLE(i2c, mn88472_id_table);
729
730static struct i2c_driver mn88472_driver = {
731 .driver = {
732 .name = "mn88472",
733 .suppress_bind_attrs = true,
734 },
735 .probe = mn88472_probe,
736 .remove = mn88472_remove,
737 .id_table = mn88472_id_table,
738};
739
740module_i2c_driver(mn88472_driver);
741
742MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
743MODULE_DESCRIPTION("Panasonic MN88472 DVB-T/T2/C demodulator driver");
744MODULE_LICENSE("GPL");
745MODULE_FIRMWARE(MN88472_FIRMWARE);
746
