linux/drivers/misc/mei/hw-txe.c
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   1/*
   2 *
   3 * Intel Management Engine Interface (Intel MEI) Linux driver
   4 * Copyright (c) 2013-2014, Intel Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2, as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope it will be useful, but WITHOUT
  11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13 * more details.
  14 *
  15 */
  16
  17#include <linux/pci.h>
  18#include <linux/jiffies.h>
  19#include <linux/ktime.h>
  20#include <linux/delay.h>
  21#include <linux/kthread.h>
  22#include <linux/interrupt.h>
  23#include <linux/pm_runtime.h>
  24
  25#include <linux/mei.h>
  26
  27#include "mei_dev.h"
  28#include "hw-txe.h"
  29#include "client.h"
  30#include "hbm.h"
  31
  32#include "mei-trace.h"
  33
  34
  35/**
  36 * mei_txe_reg_read - Reads 32bit data from the txe device
  37 *
  38 * @base_addr: registers base address
  39 * @offset: register offset
  40 *
  41 * Return: register value
  42 */
  43static inline u32 mei_txe_reg_read(void __iomem *base_addr,
  44                                        unsigned long offset)
  45{
  46        return ioread32(base_addr + offset);
  47}
  48
  49/**
  50 * mei_txe_reg_write - Writes 32bit data to the txe device
  51 *
  52 * @base_addr: registers base address
  53 * @offset: register offset
  54 * @value: the value to write
  55 */
  56static inline void mei_txe_reg_write(void __iomem *base_addr,
  57                                unsigned long offset, u32 value)
  58{
  59        iowrite32(value, base_addr + offset);
  60}
  61
  62/**
  63 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
  64 *
  65 * @hw: the txe hardware structure
  66 * @offset: register offset
  67 *
  68 * Doesn't check for aliveness while Reads 32bit data from the SeC BAR
  69 *
  70 * Return: register value
  71 */
  72static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
  73                                unsigned long offset)
  74{
  75        return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
  76}
  77
  78/**
  79 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
  80 *
  81 * @hw: the txe hardware structure
  82 * @offset: register offset
  83 *
  84 * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set
  85 *
  86 * Return: register value
  87 */
  88static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
  89                                unsigned long offset)
  90{
  91        WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
  92        return mei_txe_sec_reg_read_silent(hw, offset);
  93}
  94/**
  95 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
  96 *   doesn't check for aliveness
  97 *
  98 * @hw: the txe hardware structure
  99 * @offset: register offset
 100 * @value: value to write
 101 *
 102 * Doesn't check for aliveness while writes 32bit data from to the SeC BAR
 103 */
 104static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
 105                                unsigned long offset, u32 value)
 106{
 107        mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
 108}
 109
 110/**
 111 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
 112 *
 113 * @hw: the txe hardware structure
 114 * @offset: register offset
 115 * @value: value to write
 116 *
 117 * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set
 118 */
 119static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
 120                                unsigned long offset, u32 value)
 121{
 122        WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
 123        mei_txe_sec_reg_write_silent(hw, offset, value);
 124}
 125/**
 126 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
 127 *
 128 * @hw: the txe hardware structure
 129 * @offset: offset from which to read the data
 130 *
 131 * Return: the byte read.
 132 */
 133static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
 134                                unsigned long offset)
 135{
 136        return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
 137}
 138
 139/**
 140 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
 141 *
 142 * @hw: the txe hardware structure
 143 * @offset: offset from which to write the data
 144 * @value: the byte to write
 145 */
 146static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
 147                                unsigned long offset, u32 value)
 148{
 149        mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
 150}
 151
 152/**
 153 * mei_txe_aliveness_set - request for aliveness change
 154 *
 155 * @dev: the device structure
 156 * @req: requested aliveness value
 157 *
 158 * Request for aliveness change and returns true if the change is
 159 *   really needed and false if aliveness is already
 160 *   in the requested state
 161 *
 162 * Locking: called under "dev->device_lock" lock
 163 *
 164 * Return: true if request was send
 165 */
 166static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
 167{
 168
 169        struct mei_txe_hw *hw = to_txe_hw(dev);
 170        bool do_req = hw->aliveness != req;
 171
 172        dev_dbg(dev->dev, "Aliveness current=%d request=%d\n",
 173                                hw->aliveness, req);
 174        if (do_req) {
 175                dev->pg_event = MEI_PG_EVENT_WAIT;
 176                mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
 177        }
 178        return do_req;
 179}
 180
 181
 182/**
 183 * mei_txe_aliveness_req_get - get aliveness requested register value
 184 *
 185 * @dev: the device structure
 186 *
 187 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from
 188 * from HICR_HOST_ALIVENESS_REQ register value
 189 *
 190 * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value
 191 */
 192static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
 193{
 194        struct mei_txe_hw *hw = to_txe_hw(dev);
 195        u32 reg;
 196
 197        reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
 198        return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
 199}
 200
 201/**
 202 * mei_txe_aliveness_get - get aliveness response register value
 203 *
 204 * @dev: the device structure
 205 *
 206 * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP
 207 *         register
 208 */
 209static u32 mei_txe_aliveness_get(struct mei_device *dev)
 210{
 211        struct mei_txe_hw *hw = to_txe_hw(dev);
 212        u32 reg;
 213
 214        reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
 215        return reg & HICR_HOST_ALIVENESS_RESP_ACK;
 216}
 217
 218/**
 219 * mei_txe_aliveness_poll - waits for aliveness to settle
 220 *
 221 * @dev: the device structure
 222 * @expected: expected aliveness value
 223 *
 224 * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
 225 *
 226 * Return: 0 if the expected value was received, -ETIME otherwise
 227 */
 228static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
 229{
 230        struct mei_txe_hw *hw = to_txe_hw(dev);
 231        ktime_t stop, start;
 232
 233        start = ktime_get();
 234        stop = ktime_add(start, ms_to_ktime(SEC_ALIVENESS_WAIT_TIMEOUT));
 235        do {
 236                hw->aliveness = mei_txe_aliveness_get(dev);
 237                if (hw->aliveness == expected) {
 238                        dev->pg_event = MEI_PG_EVENT_IDLE;
 239                        dev_dbg(dev->dev, "aliveness settled after %lld usecs\n",
 240                                ktime_to_us(ktime_sub(ktime_get(), start)));
 241                        return 0;
 242                }
 243                usleep_range(20, 50);
 244        } while (ktime_before(ktime_get(), stop));
 245
 246        dev->pg_event = MEI_PG_EVENT_IDLE;
 247        dev_err(dev->dev, "aliveness timed out\n");
 248        return -ETIME;
 249}
 250
 251/**
 252 * mei_txe_aliveness_wait - waits for aliveness to settle
 253 *
 254 * @dev: the device structure
 255 * @expected: expected aliveness value
 256 *
 257 * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
 258 *
 259 * Return: 0 on success and < 0 otherwise
 260 */
 261static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
 262{
 263        struct mei_txe_hw *hw = to_txe_hw(dev);
 264        const unsigned long timeout =
 265                        msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
 266        long err;
 267        int ret;
 268
 269        hw->aliveness = mei_txe_aliveness_get(dev);
 270        if (hw->aliveness == expected)
 271                return 0;
 272
 273        mutex_unlock(&dev->device_lock);
 274        err = wait_event_timeout(hw->wait_aliveness_resp,
 275                        dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
 276        mutex_lock(&dev->device_lock);
 277
 278        hw->aliveness = mei_txe_aliveness_get(dev);
 279        ret = hw->aliveness == expected ? 0 : -ETIME;
 280
 281        if (ret)
 282                dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n",
 283                        err, hw->aliveness, dev->pg_event);
 284        else
 285                dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n",
 286                        jiffies_to_msecs(timeout - err),
 287                        hw->aliveness, dev->pg_event);
 288
 289        dev->pg_event = MEI_PG_EVENT_IDLE;
 290        return ret;
 291}
 292
 293/**
 294 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
 295 *
 296 * @dev: the device structure
 297 * @req: requested aliveness value
 298 *
 299 * Return: 0 on success and < 0 otherwise
 300 */
 301int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
 302{
 303        if (mei_txe_aliveness_set(dev, req))
 304                return mei_txe_aliveness_wait(dev, req);
 305        return 0;
 306}
 307
 308/**
 309 * mei_txe_pg_in_transition - is device now in pg transition
 310 *
 311 * @dev: the device structure
 312 *
 313 * Return: true if in pg transition, false otherwise
 314 */
 315static bool mei_txe_pg_in_transition(struct mei_device *dev)
 316{
 317        return dev->pg_event == MEI_PG_EVENT_WAIT;
 318}
 319
 320/**
 321 * mei_txe_pg_is_enabled - detect if PG is supported by HW
 322 *
 323 * @dev: the device structure
 324 *
 325 * Return: true is pg supported, false otherwise
 326 */
 327static bool mei_txe_pg_is_enabled(struct mei_device *dev)
 328{
 329        return true;
 330}
 331
 332/**
 333 * mei_txe_pg_state  - translate aliveness register value
 334 *   to the mei power gating state
 335 *
 336 * @dev: the device structure
 337 *
 338 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
 339 */
 340static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev)
 341{
 342        struct mei_txe_hw *hw = to_txe_hw(dev);
 343
 344        return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON;
 345}
 346
 347/**
 348 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
 349 *
 350 * @dev: the device structure
 351 */
 352static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
 353{
 354        struct mei_txe_hw *hw = to_txe_hw(dev);
 355        u32 hintmsk;
 356        /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */
 357        hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
 358        hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
 359        mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
 360}
 361
 362/**
 363 * mei_txe_input_doorbell_set - sets bit 0 in
 364 *    SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL.
 365 *
 366 * @hw: the txe hardware structure
 367 */
 368static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
 369{
 370        /* Clear the interrupt cause */
 371        clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
 372        mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
 373}
 374
 375/**
 376 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
 377 *
 378 * @hw: the txe hardware structure
 379 */
 380static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
 381{
 382        mei_txe_br_reg_write(hw,
 383                        SICR_SEC_IPC_OUTPUT_STATUS_REG,
 384                        SEC_IPC_OUTPUT_STATUS_RDY);
 385}
 386
 387/**
 388 * mei_txe_is_input_ready - check if TXE is ready for receiving data
 389 *
 390 * @dev: the device structure
 391 *
 392 * Return: true if INPUT STATUS READY bit is set
 393 */
 394static bool mei_txe_is_input_ready(struct mei_device *dev)
 395{
 396        struct mei_txe_hw *hw = to_txe_hw(dev);
 397        u32 status;
 398
 399        status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
 400        return !!(SEC_IPC_INPUT_STATUS_RDY & status);
 401}
 402
 403/**
 404 * mei_txe_intr_clear - clear all interrupts
 405 *
 406 * @dev: the device structure
 407 */
 408static inline void mei_txe_intr_clear(struct mei_device *dev)
 409{
 410        struct mei_txe_hw *hw = to_txe_hw(dev);
 411
 412        mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
 413                SEC_IPC_HOST_INT_STATUS_PENDING);
 414        mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
 415        mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
 416}
 417
 418/**
 419 * mei_txe_intr_disable - disable all interrupts
 420 *
 421 * @dev: the device structure
 422 */
 423static void mei_txe_intr_disable(struct mei_device *dev)
 424{
 425        struct mei_txe_hw *hw = to_txe_hw(dev);
 426
 427        mei_txe_br_reg_write(hw, HHIER_REG, 0);
 428        mei_txe_br_reg_write(hw, HIER_REG, 0);
 429}
 430/**
 431 * mei_txe_intr_enable - enable all interrupts
 432 *
 433 * @dev: the device structure
 434 */
 435static void mei_txe_intr_enable(struct mei_device *dev)
 436{
 437        struct mei_txe_hw *hw = to_txe_hw(dev);
 438
 439        mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
 440        mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
 441}
 442
 443/**
 444 * mei_txe_synchronize_irq - wait for pending IRQ handlers
 445 *
 446 * @dev: the device structure
 447 */
 448static void mei_txe_synchronize_irq(struct mei_device *dev)
 449{
 450        struct pci_dev *pdev = to_pci_dev(dev->dev);
 451
 452        synchronize_irq(pdev->irq);
 453}
 454
 455/**
 456 * mei_txe_pending_interrupts - check if there are pending interrupts
 457 *      only Aliveness, Input ready, and output doorbell are of relevance
 458 *
 459 * @dev: the device structure
 460 *
 461 * Checks if there are pending interrupts
 462 * only Aliveness, Readiness, Input ready, and Output doorbell are relevant
 463 *
 464 * Return: true if there are pending interrupts
 465 */
 466static bool mei_txe_pending_interrupts(struct mei_device *dev)
 467{
 468
 469        struct mei_txe_hw *hw = to_txe_hw(dev);
 470        bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
 471                                      TXE_INTR_ALIVENESS |
 472                                      TXE_INTR_IN_READY  |
 473                                      TXE_INTR_OUT_DB));
 474
 475        if (ret) {
 476                dev_dbg(dev->dev,
 477                        "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
 478                        !!(hw->intr_cause & TXE_INTR_IN_READY),
 479                        !!(hw->intr_cause & TXE_INTR_READINESS),
 480                        !!(hw->intr_cause & TXE_INTR_ALIVENESS),
 481                        !!(hw->intr_cause & TXE_INTR_OUT_DB));
 482        }
 483        return ret;
 484}
 485
 486/**
 487 * mei_txe_input_payload_write - write a dword to the host buffer
 488 *      at offset idx
 489 *
 490 * @dev: the device structure
 491 * @idx: index in the host buffer
 492 * @value: value
 493 */
 494static void mei_txe_input_payload_write(struct mei_device *dev,
 495                        unsigned long idx, u32 value)
 496{
 497        struct mei_txe_hw *hw = to_txe_hw(dev);
 498
 499        mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
 500                        (idx * sizeof(u32)), value);
 501}
 502
 503/**
 504 * mei_txe_out_data_read - read dword from the device buffer
 505 *      at offset idx
 506 *
 507 * @dev: the device structure
 508 * @idx: index in the device buffer
 509 *
 510 * Return: register value at index
 511 */
 512static u32 mei_txe_out_data_read(const struct mei_device *dev,
 513                                        unsigned long idx)
 514{
 515        struct mei_txe_hw *hw = to_txe_hw(dev);
 516
 517        return mei_txe_br_reg_read(hw,
 518                BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
 519}
 520
 521/* Readiness */
 522
 523/**
 524 * mei_txe_readiness_set_host_rdy - set host readiness bit
 525 *
 526 * @dev: the device structure
 527 */
 528static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
 529{
 530        struct mei_txe_hw *hw = to_txe_hw(dev);
 531
 532        mei_txe_br_reg_write(hw,
 533                SICR_HOST_IPC_READINESS_REQ_REG,
 534                SICR_HOST_IPC_READINESS_HOST_RDY);
 535}
 536
 537/**
 538 * mei_txe_readiness_clear - clear host readiness bit
 539 *
 540 * @dev: the device structure
 541 */
 542static void mei_txe_readiness_clear(struct mei_device *dev)
 543{
 544        struct mei_txe_hw *hw = to_txe_hw(dev);
 545
 546        mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
 547                                SICR_HOST_IPC_READINESS_RDY_CLR);
 548}
 549/**
 550 * mei_txe_readiness_get - Reads and returns
 551 *      the HICR_SEC_IPC_READINESS register value
 552 *
 553 * @dev: the device structure
 554 *
 555 * Return: the HICR_SEC_IPC_READINESS register value
 556 */
 557static u32 mei_txe_readiness_get(struct mei_device *dev)
 558{
 559        struct mei_txe_hw *hw = to_txe_hw(dev);
 560
 561        return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
 562}
 563
 564
 565/**
 566 * mei_txe_readiness_is_sec_rdy - check readiness
 567 *  for HICR_SEC_IPC_READINESS_SEC_RDY
 568 *
 569 * @readiness: cached readiness state
 570 *
 571 * Return: true if readiness bit is set
 572 */
 573static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
 574{
 575        return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
 576}
 577
 578/**
 579 * mei_txe_hw_is_ready - check if the hw is ready
 580 *
 581 * @dev: the device structure
 582 *
 583 * Return: true if sec is ready
 584 */
 585static bool mei_txe_hw_is_ready(struct mei_device *dev)
 586{
 587        u32 readiness =  mei_txe_readiness_get(dev);
 588
 589        return mei_txe_readiness_is_sec_rdy(readiness);
 590}
 591
 592/**
 593 * mei_txe_host_is_ready - check if the host is ready
 594 *
 595 * @dev: the device structure
 596 *
 597 * Return: true if host is ready
 598 */
 599static inline bool mei_txe_host_is_ready(struct mei_device *dev)
 600{
 601        struct mei_txe_hw *hw = to_txe_hw(dev);
 602        u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
 603
 604        return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
 605}
 606
 607/**
 608 * mei_txe_readiness_wait - wait till readiness settles
 609 *
 610 * @dev: the device structure
 611 *
 612 * Return: 0 on success and -ETIME on timeout
 613 */
 614static int mei_txe_readiness_wait(struct mei_device *dev)
 615{
 616        if (mei_txe_hw_is_ready(dev))
 617                return 0;
 618
 619        mutex_unlock(&dev->device_lock);
 620        wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
 621                        msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
 622        mutex_lock(&dev->device_lock);
 623        if (!dev->recvd_hw_ready) {
 624                dev_err(dev->dev, "wait for readiness failed\n");
 625                return -ETIME;
 626        }
 627
 628        dev->recvd_hw_ready = false;
 629        return 0;
 630}
 631
 632static const struct mei_fw_status mei_txe_fw_sts = {
 633        .count = 2,
 634        .status[0] = PCI_CFG_TXE_FW_STS0,
 635        .status[1] = PCI_CFG_TXE_FW_STS1
 636};
 637
 638/**
 639 * mei_txe_fw_status - read fw status register from pci config space
 640 *
 641 * @dev: mei device
 642 * @fw_status: fw status register values
 643 *
 644 * Return: 0 on success, error otherwise
 645 */
 646static int mei_txe_fw_status(struct mei_device *dev,
 647                             struct mei_fw_status *fw_status)
 648{
 649        const struct mei_fw_status *fw_src = &mei_txe_fw_sts;
 650        struct pci_dev *pdev = to_pci_dev(dev->dev);
 651        int ret;
 652        int i;
 653
 654        if (!fw_status)
 655                return -EINVAL;
 656
 657        fw_status->count = fw_src->count;
 658        for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
 659                ret = pci_read_config_dword(pdev, fw_src->status[i],
 660                                            &fw_status->status[i]);
 661                trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
 662                                       fw_src->status[i],
 663                                       fw_status->status[i]);
 664                if (ret)
 665                        return ret;
 666        }
 667
 668        return 0;
 669}
 670
 671/**
 672 *  mei_txe_hw_config - configure hardware at the start of the devices
 673 *
 674 * @dev: the device structure
 675 *
 676 * Configure hardware at the start of the device should be done only
 677 *   once at the device probe time
 678 */
 679static void mei_txe_hw_config(struct mei_device *dev)
 680{
 681
 682        struct mei_txe_hw *hw = to_txe_hw(dev);
 683
 684        /* Doesn't change in runtime */
 685        dev->hbuf_depth = PAYLOAD_SIZE / 4;
 686
 687        hw->aliveness = mei_txe_aliveness_get(dev);
 688        hw->readiness = mei_txe_readiness_get(dev);
 689
 690        dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
 691                hw->aliveness, hw->readiness);
 692}
 693
 694
 695/**
 696 * mei_txe_write - writes a message to device.
 697 *
 698 * @dev: the device structure
 699 * @header: header of message
 700 * @buf: message buffer will be written
 701 *
 702 * Return: 0 if success, <0 - otherwise.
 703 */
 704
 705static int mei_txe_write(struct mei_device *dev,
 706                         struct mei_msg_hdr *header,
 707                         const unsigned char *buf)
 708{
 709        struct mei_txe_hw *hw = to_txe_hw(dev);
 710        unsigned long rem;
 711        unsigned long length;
 712        int slots = dev->hbuf_depth;
 713        u32 *reg_buf = (u32 *)buf;
 714        u32 dw_cnt;
 715        int i;
 716
 717        if (WARN_ON(!header || !buf))
 718                return -EINVAL;
 719
 720        length = header->length;
 721
 722        dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
 723
 724        dw_cnt = mei_data2slots(length);
 725        if (dw_cnt > slots)
 726                return -EMSGSIZE;
 727
 728        if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
 729                return -EAGAIN;
 730
 731        /* Enable Input Ready Interrupt. */
 732        mei_txe_input_ready_interrupt_enable(dev);
 733
 734        if (!mei_txe_is_input_ready(dev)) {
 735                char fw_sts_str[MEI_FW_STATUS_STR_SZ];
 736
 737                mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ);
 738                dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str);
 739                return -EAGAIN;
 740        }
 741
 742        mei_txe_input_payload_write(dev, 0, *((u32 *)header));
 743
 744        for (i = 0; i < length / 4; i++)
 745                mei_txe_input_payload_write(dev, i + 1, reg_buf[i]);
 746
 747        rem = length & 0x3;
 748        if (rem > 0) {
 749                u32 reg = 0;
 750
 751                memcpy(&reg, &buf[length - rem], rem);
 752                mei_txe_input_payload_write(dev, i + 1, reg);
 753        }
 754
 755        /* after each write the whole buffer is consumed */
 756        hw->slots = 0;
 757
 758        /* Set Input-Doorbell */
 759        mei_txe_input_doorbell_set(hw);
 760
 761        return 0;
 762}
 763
 764/**
 765 * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer
 766 *
 767 * @dev: the device structure
 768 *
 769 * Return: the PAYLOAD_SIZE - 4
 770 */
 771static size_t mei_txe_hbuf_max_len(const struct mei_device *dev)
 772{
 773        return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr);
 774}
 775
 776/**
 777 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
 778 *
 779 * @dev: the device structure
 780 *
 781 * Return: always hbuf_depth
 782 */
 783static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
 784{
 785        struct mei_txe_hw *hw = to_txe_hw(dev);
 786
 787        return hw->slots;
 788}
 789
 790/**
 791 * mei_txe_count_full_read_slots - mimics the me device circular buffer
 792 *
 793 * @dev: the device structure
 794 *
 795 * Return: always buffer size in dwords count
 796 */
 797static int mei_txe_count_full_read_slots(struct mei_device *dev)
 798{
 799        /* read buffers has static size */
 800        return  PAYLOAD_SIZE / 4;
 801}
 802
 803/**
 804 * mei_txe_read_hdr - read message header which is always in 4 first bytes
 805 *
 806 * @dev: the device structure
 807 *
 808 * Return: mei message header
 809 */
 810
 811static u32 mei_txe_read_hdr(const struct mei_device *dev)
 812{
 813        return mei_txe_out_data_read(dev, 0);
 814}
 815/**
 816 * mei_txe_read - reads a message from the txe device.
 817 *
 818 * @dev: the device structure
 819 * @buf: message buffer will be written
 820 * @len: message size will be read
 821 *
 822 * Return: -EINVAL on error wrong argument and 0 on success
 823 */
 824static int mei_txe_read(struct mei_device *dev,
 825                unsigned char *buf, unsigned long len)
 826{
 827
 828        struct mei_txe_hw *hw = to_txe_hw(dev);
 829        u32 *reg_buf, reg;
 830        u32 rem;
 831        u32 i;
 832
 833        if (WARN_ON(!buf || !len))
 834                return -EINVAL;
 835
 836        reg_buf = (u32 *)buf;
 837        rem = len & 0x3;
 838
 839        dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n",
 840                len, mei_txe_out_data_read(dev, 0));
 841
 842        for (i = 0; i < len / 4; i++) {
 843                /* skip header: index starts from 1 */
 844                reg = mei_txe_out_data_read(dev, i + 1);
 845                dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg);
 846                *reg_buf++ = reg;
 847        }
 848
 849        if (rem) {
 850                reg = mei_txe_out_data_read(dev, i + 1);
 851                memcpy(reg_buf, &reg, rem);
 852        }
 853
 854        mei_txe_output_ready_set(hw);
 855        return 0;
 856}
 857
 858/**
 859 * mei_txe_hw_reset - resets host and fw.
 860 *
 861 * @dev: the device structure
 862 * @intr_enable: if interrupt should be enabled after reset.
 863 *
 864 * Return: 0 on success and < 0 in case of error
 865 */
 866static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
 867{
 868        struct mei_txe_hw *hw = to_txe_hw(dev);
 869
 870        u32 aliveness_req;
 871        /*
 872         * read input doorbell to ensure consistency between  Bridge and SeC
 873         * return value might be garbage return
 874         */
 875        (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
 876
 877        aliveness_req = mei_txe_aliveness_req_get(dev);
 878        hw->aliveness = mei_txe_aliveness_get(dev);
 879
 880        /* Disable interrupts in this stage we will poll */
 881        mei_txe_intr_disable(dev);
 882
 883        /*
 884         * If Aliveness Request and Aliveness Response are not equal then
 885         * wait for them to be equal
 886         * Since we might have interrupts disabled - poll for it
 887         */
 888        if (aliveness_req != hw->aliveness)
 889                if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
 890                        dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n");
 891                        return -EIO;
 892                }
 893
 894        /*
 895         * If Aliveness Request and Aliveness Response are set then clear them
 896         */
 897        if (aliveness_req) {
 898                mei_txe_aliveness_set(dev, 0);
 899                if (mei_txe_aliveness_poll(dev, 0) < 0) {
 900                        dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
 901                        return -EIO;
 902                }
 903        }
 904
 905        /*
 906         * Set readiness RDY_CLR bit
 907         */
 908        mei_txe_readiness_clear(dev);
 909
 910        return 0;
 911}
 912
 913/**
 914 * mei_txe_hw_start - start the hardware after reset
 915 *
 916 * @dev: the device structure
 917 *
 918 * Return: 0 on success an error code otherwise
 919 */
 920static int mei_txe_hw_start(struct mei_device *dev)
 921{
 922        struct mei_txe_hw *hw = to_txe_hw(dev);
 923        int ret;
 924
 925        u32 hisr;
 926
 927        /* bring back interrupts */
 928        mei_txe_intr_enable(dev);
 929
 930        ret = mei_txe_readiness_wait(dev);
 931        if (ret < 0) {
 932                dev_err(dev->dev, "waiting for readiness failed\n");
 933                return ret;
 934        }
 935
 936        /*
 937         * If HISR.INT2_STS interrupt status bit is set then clear it.
 938         */
 939        hisr = mei_txe_br_reg_read(hw, HISR_REG);
 940        if (hisr & HISR_INT_2_STS)
 941                mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
 942
 943        /* Clear the interrupt cause of OutputDoorbell */
 944        clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
 945
 946        ret = mei_txe_aliveness_set_sync(dev, 1);
 947        if (ret < 0) {
 948                dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
 949                return ret;
 950        }
 951
 952        pm_runtime_set_active(dev->dev);
 953
 954        /* enable input ready interrupts:
 955         * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK
 956         */
 957        mei_txe_input_ready_interrupt_enable(dev);
 958
 959
 960        /*  Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */
 961        mei_txe_output_ready_set(hw);
 962
 963        /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY
 964         */
 965        mei_txe_readiness_set_host_rdy(dev);
 966
 967        return 0;
 968}
 969
 970/**
 971 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
 972 *  single bit mask and acknowledge the interrupts
 973 *
 974 * @dev: the device structure
 975 * @do_ack: acknowledge interrupts
 976 *
 977 * Return: true if found interrupts to process.
 978 */
 979static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
 980{
 981        struct mei_txe_hw *hw = to_txe_hw(dev);
 982        u32 hisr;
 983        u32 hhisr;
 984        u32 ipc_isr;
 985        u32 aliveness;
 986        bool generated;
 987
 988        /* read interrupt registers */
 989        hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
 990        generated = (hhisr & IPC_HHIER_MSK);
 991        if (!generated)
 992                goto out;
 993
 994        hisr = mei_txe_br_reg_read(hw, HISR_REG);
 995
 996        aliveness = mei_txe_aliveness_get(dev);
 997        if (hhisr & IPC_HHIER_SEC && aliveness) {
 998                ipc_isr = mei_txe_sec_reg_read_silent(hw,
 999                                SEC_IPC_HOST_INT_STATUS_REG);
1000        } else {
1001                ipc_isr = 0;
1002                hhisr &= ~IPC_HHIER_SEC;
1003        }
1004
1005        generated = generated ||
1006                (hisr & HISR_INT_STS_MSK) ||
1007                (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING);
1008
1009        if (generated && do_ack) {
1010                /* Save the interrupt causes */
1011                hw->intr_cause |= hisr & HISR_INT_STS_MSK;
1012                if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
1013                        hw->intr_cause |= TXE_INTR_IN_READY;
1014
1015
1016                mei_txe_intr_disable(dev);
1017                /* Clear the interrupts in hierarchy:
1018                 * IPC and Bridge, than the High Level */
1019                mei_txe_sec_reg_write_silent(hw,
1020                        SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
1021                mei_txe_br_reg_write(hw, HISR_REG, hisr);
1022                mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
1023        }
1024
1025out:
1026        return generated;
1027}
1028
1029/**
1030 * mei_txe_irq_quick_handler - The ISR of the MEI device
1031 *
1032 * @irq: The irq number
1033 * @dev_id: pointer to the device structure
1034 *
1035 * Return: IRQ_WAKE_THREAD if interrupt is designed for the device
1036 *         IRQ_NONE otherwise
1037 */
1038irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
1039{
1040        struct mei_device *dev = dev_id;
1041
1042        if (mei_txe_check_and_ack_intrs(dev, true))
1043                return IRQ_WAKE_THREAD;
1044        return IRQ_NONE;
1045}
1046
1047
1048/**
1049 * mei_txe_irq_thread_handler - txe interrupt thread
1050 *
1051 * @irq: The irq number
1052 * @dev_id: pointer to the device structure
1053 *
1054 * Return: IRQ_HANDLED
1055 */
1056irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
1057{
1058        struct mei_device *dev = (struct mei_device *) dev_id;
1059        struct mei_txe_hw *hw = to_txe_hw(dev);
1060        struct list_head cmpl_list;
1061        s32 slots;
1062        int rets = 0;
1063
1064        dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
1065                mei_txe_br_reg_read(hw, HHISR_REG),
1066                mei_txe_br_reg_read(hw, HISR_REG),
1067                mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
1068
1069
1070        /* initialize our complete list */
1071        mutex_lock(&dev->device_lock);
1072        INIT_LIST_HEAD(&cmpl_list);
1073
1074        if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
1075                mei_txe_check_and_ack_intrs(dev, true);
1076
1077        /* show irq events */
1078        mei_txe_pending_interrupts(dev);
1079
1080        hw->aliveness = mei_txe_aliveness_get(dev);
1081        hw->readiness = mei_txe_readiness_get(dev);
1082
1083        /* Readiness:
1084         * Detection of TXE driver going through reset
1085         * or TXE driver resetting the HECI interface.
1086         */
1087        if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
1088                dev_dbg(dev->dev, "Readiness Interrupt was received...\n");
1089
1090                /* Check if SeC is going through reset */
1091                if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
1092                        dev_dbg(dev->dev, "we need to start the dev.\n");
1093                        dev->recvd_hw_ready = true;
1094                } else {
1095                        dev->recvd_hw_ready = false;
1096                        if (dev->dev_state != MEI_DEV_RESETTING) {
1097
1098                                dev_warn(dev->dev, "FW not ready: resetting.\n");
1099                                schedule_work(&dev->reset_work);
1100                                goto end;
1101
1102                        }
1103                }
1104                wake_up(&dev->wait_hw_ready);
1105        }
1106
1107        /************************************************************/
1108        /* Check interrupt cause:
1109         * Aliveness: Detection of SeC acknowledge of host request that
1110         * it remain alive or host cancellation of that request.
1111         */
1112
1113        if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
1114                /* Clear the interrupt cause */
1115                dev_dbg(dev->dev,
1116                        "Aliveness Interrupt: Status: %d\n", hw->aliveness);
1117                dev->pg_event = MEI_PG_EVENT_RECEIVED;
1118                if (waitqueue_active(&hw->wait_aliveness_resp))
1119                        wake_up(&hw->wait_aliveness_resp);
1120        }
1121
1122
1123        /* Output Doorbell:
1124         * Detection of SeC having sent output to host
1125         */
1126        slots = mei_count_full_read_slots(dev);
1127        if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
1128                /* Read from TXE */
1129                rets = mei_irq_read_handler(dev, &cmpl_list, &slots);
1130                if (rets &&
1131                    (dev->dev_state != MEI_DEV_RESETTING &&
1132                     dev->dev_state != MEI_DEV_POWER_DOWN)) {
1133                        dev_err(dev->dev,
1134                                "mei_irq_read_handler ret = %d.\n", rets);
1135
1136                        schedule_work(&dev->reset_work);
1137                        goto end;
1138                }
1139        }
1140        /* Input Ready: Detection if host can write to SeC */
1141        if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {
1142                dev->hbuf_is_ready = true;
1143                hw->slots = dev->hbuf_depth;
1144        }
1145
1146        if (hw->aliveness && dev->hbuf_is_ready) {
1147                /* get the real register value */
1148                dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1149                rets = mei_irq_write_handler(dev, &cmpl_list);
1150                if (rets && rets != -EMSGSIZE)
1151                        dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n",
1152                                rets);
1153                dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1154        }
1155
1156        mei_irq_compl_handler(dev, &cmpl_list);
1157
1158end:
1159        dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1160
1161        mutex_unlock(&dev->device_lock);
1162
1163        mei_enable_interrupts(dev);
1164        return IRQ_HANDLED;
1165}
1166
1167static const struct mei_hw_ops mei_txe_hw_ops = {
1168
1169        .host_is_ready = mei_txe_host_is_ready,
1170
1171        .fw_status = mei_txe_fw_status,
1172        .pg_state = mei_txe_pg_state,
1173
1174        .hw_is_ready = mei_txe_hw_is_ready,
1175        .hw_reset = mei_txe_hw_reset,
1176        .hw_config = mei_txe_hw_config,
1177        .hw_start = mei_txe_hw_start,
1178
1179        .pg_in_transition = mei_txe_pg_in_transition,
1180        .pg_is_enabled = mei_txe_pg_is_enabled,
1181
1182        .intr_clear = mei_txe_intr_clear,
1183        .intr_enable = mei_txe_intr_enable,
1184        .intr_disable = mei_txe_intr_disable,
1185        .synchronize_irq = mei_txe_synchronize_irq,
1186
1187        .hbuf_free_slots = mei_txe_hbuf_empty_slots,
1188        .hbuf_is_ready = mei_txe_is_input_ready,
1189        .hbuf_max_len = mei_txe_hbuf_max_len,
1190
1191        .write = mei_txe_write,
1192
1193        .rdbuf_full_slots = mei_txe_count_full_read_slots,
1194        .read_hdr = mei_txe_read_hdr,
1195
1196        .read = mei_txe_read,
1197
1198};
1199
1200/**
1201 * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1202 *
1203 * @pdev: pci device
1204 *
1205 * Return: struct mei_device * on success or NULL
1206 */
1207struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
1208{
1209        struct mei_device *dev;
1210        struct mei_txe_hw *hw;
1211
1212        dev = devm_kzalloc(&pdev->dev, sizeof(struct mei_device) +
1213                           sizeof(struct mei_txe_hw), GFP_KERNEL);
1214        if (!dev)
1215                return NULL;
1216
1217        mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
1218
1219        hw = to_txe_hw(dev);
1220
1221        init_waitqueue_head(&hw->wait_aliveness_resp);
1222
1223        return dev;
1224}
1225
1226/**
1227 * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1228 *
1229 * @dev:   the device structure
1230 * @addr:  physical address start of the range
1231 * @range: physical range size
1232 *
1233 * Return: 0 on success an error code otherwise
1234 */
1235int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
1236{
1237        struct mei_txe_hw *hw = to_txe_hw(dev);
1238
1239        u32 lo32 = lower_32_bits(addr);
1240        u32 hi32 = upper_32_bits(addr);
1241        u32 ctrl;
1242
1243        /* SATT is limited to 36 Bits */
1244        if (hi32 & ~0xF)
1245                return -EINVAL;
1246
1247        /* SATT has to be 16Byte aligned */
1248        if (lo32 & 0xF)
1249                return -EINVAL;
1250
1251        /* SATT range has to be 4Bytes aligned */
1252        if (range & 0x4)
1253                return -EINVAL;
1254
1255        /* SATT is limited to 32 MB range*/
1256        if (range > SATT_RANGE_MAX)
1257                return -EINVAL;
1258
1259        ctrl = SATT2_CTRL_VALID_MSK;
1260        ctrl |= hi32  << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
1261
1262        mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
1263        mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
1264        mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
1265        dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",
1266                range, lo32, ctrl);
1267
1268        return 0;
1269}
1270