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19#include <linux/clk.h>
20#include <linux/completion.h>
21#include <linux/dmaengine.h>
22#include <linux/dma-direction.h>
23#include <linux/dma-mapping.h>
24#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/resource.h>
28#include <linux/sched.h>
29#include <linux/types.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/rawnand.h>
32#include <linux/mtd/nand_ecc.h>
33#include <linux/platform_device.h>
34#include <linux/of.h>
35#include <linux/mtd/partitions.h>
36#include <linux/io.h>
37#include <linux/slab.h>
38#include <linux/amba/bus.h>
39#include <mtd/mtd-abi.h>
40
41
42#define CTRL 0x0
43
44 #define BANK_ENABLE (1 << 0)
45 #define MUXED (1 << 1)
46 #define NOR_DEV (2 << 2)
47 #define WIDTH_8 (0 << 4)
48 #define WIDTH_16 (1 << 4)
49 #define RSTPWRDWN (1 << 6)
50 #define WPROT (1 << 7)
51 #define WRT_ENABLE (1 << 12)
52 #define WAIT_ENB (1 << 13)
53
54#define CTRL_TIM 0x4
55
56
57#define FSMC_NOR_BANK_SZ 0x8
58#define FSMC_NOR_REG_SIZE 0x40
59
60#define FSMC_NOR_REG(base, bank, reg) (base + \
61 FSMC_NOR_BANK_SZ * (bank) + \
62 reg)
63
64
65#define PC 0x00
66
67 #define FSMC_RESET (1 << 0)
68 #define FSMC_WAITON (1 << 1)
69 #define FSMC_ENABLE (1 << 2)
70 #define FSMC_DEVTYPE_NAND (1 << 3)
71 #define FSMC_DEVWID_8 (0 << 4)
72 #define FSMC_DEVWID_16 (1 << 4)
73 #define FSMC_ECCEN (1 << 6)
74 #define FSMC_ECCPLEN_512 (0 << 7)
75 #define FSMC_ECCPLEN_256 (1 << 7)
76 #define FSMC_TCLR_1 (1)
77 #define FSMC_TCLR_SHIFT (9)
78 #define FSMC_TCLR_MASK (0xF)
79 #define FSMC_TAR_1 (1)
80 #define FSMC_TAR_SHIFT (13)
81 #define FSMC_TAR_MASK (0xF)
82#define STS 0x04
83
84 #define FSMC_CODE_RDY (1 << 15)
85#define COMM 0x08
86
87 #define FSMC_TSET_0 0
88 #define FSMC_TSET_SHIFT 0
89 #define FSMC_TSET_MASK 0xFF
90 #define FSMC_TWAIT_6 6
91 #define FSMC_TWAIT_SHIFT 8
92 #define FSMC_TWAIT_MASK 0xFF
93 #define FSMC_THOLD_4 4
94 #define FSMC_THOLD_SHIFT 16
95 #define FSMC_THOLD_MASK 0xFF
96 #define FSMC_THIZ_1 1
97 #define FSMC_THIZ_SHIFT 24
98 #define FSMC_THIZ_MASK 0xFF
99#define ATTRIB 0x0C
100#define IOATA 0x10
101#define ECC1 0x14
102#define ECC2 0x18
103#define ECC3 0x1C
104#define FSMC_NAND_BANK_SZ 0x20
105
106#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
107 (FSMC_NAND_BANK_SZ * (bank)) + \
108 reg)
109
110#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
111
112struct fsmc_nand_timings {
113 uint8_t tclr;
114 uint8_t tar;
115 uint8_t thiz;
116 uint8_t thold;
117 uint8_t twait;
118 uint8_t tset;
119};
120
121enum access_mode {
122 USE_DMA_ACCESS = 1,
123 USE_WORD_ACCESS,
124};
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148struct fsmc_nand_data {
149 u32 pid;
150 struct nand_chip nand;
151
152 unsigned int bank;
153 struct device *dev;
154 enum access_mode mode;
155 struct clk *clk;
156
157
158 struct dma_chan *read_dma_chan;
159 struct dma_chan *write_dma_chan;
160 struct completion dma_access_complete;
161
162 struct fsmc_nand_timings *dev_timings;
163
164 dma_addr_t data_pa;
165 void __iomem *data_va;
166 void __iomem *cmd_va;
167 void __iomem *addr_va;
168 void __iomem *regs_va;
169};
170
171static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
172 struct mtd_oob_region *oobregion)
173{
174 struct nand_chip *chip = mtd_to_nand(mtd);
175
176 if (section >= chip->ecc.steps)
177 return -ERANGE;
178
179 oobregion->offset = (section * 16) + 2;
180 oobregion->length = 3;
181
182 return 0;
183}
184
185static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
186 struct mtd_oob_region *oobregion)
187{
188 struct nand_chip *chip = mtd_to_nand(mtd);
189
190 if (section >= chip->ecc.steps)
191 return -ERANGE;
192
193 oobregion->offset = (section * 16) + 8;
194
195 if (section < chip->ecc.steps - 1)
196 oobregion->length = 8;
197 else
198 oobregion->length = mtd->oobsize - oobregion->offset;
199
200 return 0;
201}
202
203static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
204 .ecc = fsmc_ecc1_ooblayout_ecc,
205 .free = fsmc_ecc1_ooblayout_free,
206};
207
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212
213
214static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
215 struct mtd_oob_region *oobregion)
216{
217 struct nand_chip *chip = mtd_to_nand(mtd);
218
219 if (section >= chip->ecc.steps)
220 return -ERANGE;
221
222 oobregion->length = chip->ecc.bytes;
223
224 if (!section && mtd->writesize <= 512)
225 oobregion->offset = 0;
226 else
227 oobregion->offset = (section * 16) + 2;
228
229 return 0;
230}
231
232static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
233 struct mtd_oob_region *oobregion)
234{
235 struct nand_chip *chip = mtd_to_nand(mtd);
236
237 if (section >= chip->ecc.steps)
238 return -ERANGE;
239
240 oobregion->offset = (section * 16) + 15;
241
242 if (section < chip->ecc.steps - 1)
243 oobregion->length = 3;
244 else
245 oobregion->length = mtd->oobsize - oobregion->offset;
246
247 return 0;
248}
249
250static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
251 .ecc = fsmc_ecc4_ooblayout_ecc,
252 .free = fsmc_ecc4_ooblayout_free,
253};
254
255static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
256{
257 return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
258}
259
260
261
262
263
264static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
265{
266 struct nand_chip *this = mtd_to_nand(mtd);
267 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
268 void __iomem *regs = host->regs_va;
269 unsigned int bank = host->bank;
270
271 if (ctrl & NAND_CTRL_CHANGE) {
272 u32 pc;
273
274 if (ctrl & NAND_CLE) {
275 this->IO_ADDR_R = host->cmd_va;
276 this->IO_ADDR_W = host->cmd_va;
277 } else if (ctrl & NAND_ALE) {
278 this->IO_ADDR_R = host->addr_va;
279 this->IO_ADDR_W = host->addr_va;
280 } else {
281 this->IO_ADDR_R = host->data_va;
282 this->IO_ADDR_W = host->data_va;
283 }
284
285 pc = readl(FSMC_NAND_REG(regs, bank, PC));
286 if (ctrl & NAND_NCE)
287 pc |= FSMC_ENABLE;
288 else
289 pc &= ~FSMC_ENABLE;
290 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
291 }
292
293 mb();
294
295 if (cmd != NAND_CMD_NONE)
296 writeb_relaxed(cmd, this->IO_ADDR_W);
297}
298
299
300
301
302
303
304
305static void fsmc_nand_setup(struct fsmc_nand_data *host,
306 struct fsmc_nand_timings *tims)
307{
308 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
309 uint32_t tclr, tar, thiz, thold, twait, tset;
310 unsigned int bank = host->bank;
311 void __iomem *regs = host->regs_va;
312
313 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
314 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
315 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
316 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
317 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
318 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
319
320 if (host->nand.options & NAND_BUSWIDTH_16)
321 writel_relaxed(value | FSMC_DEVWID_16,
322 FSMC_NAND_REG(regs, bank, PC));
323 else
324 writel_relaxed(value | FSMC_DEVWID_8,
325 FSMC_NAND_REG(regs, bank, PC));
326
327 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
328 FSMC_NAND_REG(regs, bank, PC));
329 writel_relaxed(thiz | thold | twait | tset,
330 FSMC_NAND_REG(regs, bank, COMM));
331 writel_relaxed(thiz | thold | twait | tset,
332 FSMC_NAND_REG(regs, bank, ATTRIB));
333}
334
335static int fsmc_calc_timings(struct fsmc_nand_data *host,
336 const struct nand_sdr_timings *sdrt,
337 struct fsmc_nand_timings *tims)
338{
339 unsigned long hclk = clk_get_rate(host->clk);
340 unsigned long hclkn = NSEC_PER_SEC / hclk;
341 uint32_t thiz, thold, twait, tset;
342
343 if (sdrt->tRC_min < 30000)
344 return -EOPNOTSUPP;
345
346 tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
347 if (tims->tar > FSMC_TAR_MASK)
348 tims->tar = FSMC_TAR_MASK;
349 tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
350 if (tims->tclr > FSMC_TCLR_MASK)
351 tims->tclr = FSMC_TCLR_MASK;
352
353 thiz = sdrt->tCS_min - sdrt->tWP_min;
354 tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
355
356 thold = sdrt->tDH_min;
357 if (thold < sdrt->tCH_min)
358 thold = sdrt->tCH_min;
359 if (thold < sdrt->tCLH_min)
360 thold = sdrt->tCLH_min;
361 if (thold < sdrt->tWH_min)
362 thold = sdrt->tWH_min;
363 if (thold < sdrt->tALH_min)
364 thold = sdrt->tALH_min;
365 if (thold < sdrt->tREH_min)
366 thold = sdrt->tREH_min;
367 tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
368 if (tims->thold == 0)
369 tims->thold = 1;
370 else if (tims->thold > FSMC_THOLD_MASK)
371 tims->thold = FSMC_THOLD_MASK;
372
373 twait = max(sdrt->tRP_min, sdrt->tWP_min);
374 tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
375 if (tims->twait == 0)
376 tims->twait = 1;
377 else if (tims->twait > FSMC_TWAIT_MASK)
378 tims->twait = FSMC_TWAIT_MASK;
379
380 tset = max(sdrt->tCS_min - sdrt->tWP_min,
381 sdrt->tCEA_max - sdrt->tREA_max);
382 tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
383 if (tims->tset == 0)
384 tims->tset = 1;
385 else if (tims->tset > FSMC_TSET_MASK)
386 tims->tset = FSMC_TSET_MASK;
387
388 return 0;
389}
390
391static int fsmc_setup_data_interface(struct mtd_info *mtd, int csline,
392 const struct nand_data_interface *conf)
393{
394 struct nand_chip *nand = mtd_to_nand(mtd);
395 struct fsmc_nand_data *host = nand_get_controller_data(nand);
396 struct fsmc_nand_timings tims;
397 const struct nand_sdr_timings *sdrt;
398 int ret;
399
400 sdrt = nand_get_sdr_timings(conf);
401 if (IS_ERR(sdrt))
402 return PTR_ERR(sdrt);
403
404 ret = fsmc_calc_timings(host, sdrt, &tims);
405 if (ret)
406 return ret;
407
408 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
409 return 0;
410
411 fsmc_nand_setup(host, &tims);
412
413 return 0;
414}
415
416
417
418
419static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
420{
421 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
422 void __iomem *regs = host->regs_va;
423 uint32_t bank = host->bank;
424
425 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
426 FSMC_NAND_REG(regs, bank, PC));
427 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
428 FSMC_NAND_REG(regs, bank, PC));
429 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
430 FSMC_NAND_REG(regs, bank, PC));
431}
432
433
434
435
436
437
438static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
439 uint8_t *ecc)
440{
441 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
442 void __iomem *regs = host->regs_va;
443 uint32_t bank = host->bank;
444 uint32_t ecc_tmp;
445 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
446
447 do {
448 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
449 break;
450 else
451 cond_resched();
452 } while (!time_after_eq(jiffies, deadline));
453
454 if (time_after_eq(jiffies, deadline)) {
455 dev_err(host->dev, "calculate ecc timed out\n");
456 return -ETIMEDOUT;
457 }
458
459 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
460 ecc[0] = (uint8_t) (ecc_tmp >> 0);
461 ecc[1] = (uint8_t) (ecc_tmp >> 8);
462 ecc[2] = (uint8_t) (ecc_tmp >> 16);
463 ecc[3] = (uint8_t) (ecc_tmp >> 24);
464
465 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
466 ecc[4] = (uint8_t) (ecc_tmp >> 0);
467 ecc[5] = (uint8_t) (ecc_tmp >> 8);
468 ecc[6] = (uint8_t) (ecc_tmp >> 16);
469 ecc[7] = (uint8_t) (ecc_tmp >> 24);
470
471 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
472 ecc[8] = (uint8_t) (ecc_tmp >> 0);
473 ecc[9] = (uint8_t) (ecc_tmp >> 8);
474 ecc[10] = (uint8_t) (ecc_tmp >> 16);
475 ecc[11] = (uint8_t) (ecc_tmp >> 24);
476
477 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
478 ecc[12] = (uint8_t) (ecc_tmp >> 16);
479
480 return 0;
481}
482
483
484
485
486
487
488static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
489 uint8_t *ecc)
490{
491 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
492 void __iomem *regs = host->regs_va;
493 uint32_t bank = host->bank;
494 uint32_t ecc_tmp;
495
496 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
497 ecc[0] = (uint8_t) (ecc_tmp >> 0);
498 ecc[1] = (uint8_t) (ecc_tmp >> 8);
499 ecc[2] = (uint8_t) (ecc_tmp >> 16);
500
501 return 0;
502}
503
504
505static int count_written_bits(uint8_t *buff, int size, int max_bits)
506{
507 int k, written_bits = 0;
508
509 for (k = 0; k < size; k++) {
510 written_bits += hweight8(~buff[k]);
511 if (written_bits > max_bits)
512 break;
513 }
514
515 return written_bits;
516}
517
518static void dma_complete(void *param)
519{
520 struct fsmc_nand_data *host = param;
521
522 complete(&host->dma_access_complete);
523}
524
525static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
526 enum dma_data_direction direction)
527{
528 struct dma_chan *chan;
529 struct dma_device *dma_dev;
530 struct dma_async_tx_descriptor *tx;
531 dma_addr_t dma_dst, dma_src, dma_addr;
532 dma_cookie_t cookie;
533 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
534 int ret;
535 unsigned long time_left;
536
537 if (direction == DMA_TO_DEVICE)
538 chan = host->write_dma_chan;
539 else if (direction == DMA_FROM_DEVICE)
540 chan = host->read_dma_chan;
541 else
542 return -EINVAL;
543
544 dma_dev = chan->device;
545 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
546
547 if (direction == DMA_TO_DEVICE) {
548 dma_src = dma_addr;
549 dma_dst = host->data_pa;
550 } else {
551 dma_src = host->data_pa;
552 dma_dst = dma_addr;
553 }
554
555 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
556 len, flags);
557 if (!tx) {
558 dev_err(host->dev, "device_prep_dma_memcpy error\n");
559 ret = -EIO;
560 goto unmap_dma;
561 }
562
563 tx->callback = dma_complete;
564 tx->callback_param = host;
565 cookie = tx->tx_submit(tx);
566
567 ret = dma_submit_error(cookie);
568 if (ret) {
569 dev_err(host->dev, "dma_submit_error %d\n", cookie);
570 goto unmap_dma;
571 }
572
573 dma_async_issue_pending(chan);
574
575 time_left =
576 wait_for_completion_timeout(&host->dma_access_complete,
577 msecs_to_jiffies(3000));
578 if (time_left == 0) {
579 dmaengine_terminate_all(chan);
580 dev_err(host->dev, "wait_for_completion_timeout\n");
581 ret = -ETIMEDOUT;
582 goto unmap_dma;
583 }
584
585 ret = 0;
586
587unmap_dma:
588 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
589
590 return ret;
591}
592
593
594
595
596
597
598
599static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
600{
601 int i;
602 struct nand_chip *chip = mtd_to_nand(mtd);
603
604 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
605 IS_ALIGNED(len, sizeof(uint32_t))) {
606 uint32_t *p = (uint32_t *)buf;
607 len = len >> 2;
608 for (i = 0; i < len; i++)
609 writel_relaxed(p[i], chip->IO_ADDR_W);
610 } else {
611 for (i = 0; i < len; i++)
612 writeb_relaxed(buf[i], chip->IO_ADDR_W);
613 }
614}
615
616
617
618
619
620
621
622static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
623{
624 int i;
625 struct nand_chip *chip = mtd_to_nand(mtd);
626
627 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
628 IS_ALIGNED(len, sizeof(uint32_t))) {
629 uint32_t *p = (uint32_t *)buf;
630 len = len >> 2;
631 for (i = 0; i < len; i++)
632 p[i] = readl_relaxed(chip->IO_ADDR_R);
633 } else {
634 for (i = 0; i < len; i++)
635 buf[i] = readb_relaxed(chip->IO_ADDR_R);
636 }
637}
638
639
640
641
642
643
644
645static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
646{
647 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
648
649 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
650}
651
652
653
654
655
656
657
658static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
659 int len)
660{
661 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
662
663 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
664}
665
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677
678
679
680static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
681 uint8_t *buf, int oob_required, int page)
682{
683 int i, j, s, stat, eccsize = chip->ecc.size;
684 int eccbytes = chip->ecc.bytes;
685 int eccsteps = chip->ecc.steps;
686 uint8_t *p = buf;
687 uint8_t *ecc_calc = chip->ecc.calc_buf;
688 uint8_t *ecc_code = chip->ecc.code_buf;
689 int off, len, group = 0;
690
691
692
693
694
695 uint16_t ecc_oob[7];
696 uint8_t *oob = (uint8_t *)&ecc_oob[0];
697 unsigned int max_bitflips = 0;
698
699 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
700 nand_read_page_op(chip, page, s * eccsize, NULL, 0);
701 chip->ecc.hwctl(mtd, NAND_ECC_READ);
702 chip->read_buf(mtd, p, eccsize);
703
704 for (j = 0; j < eccbytes;) {
705 struct mtd_oob_region oobregion;
706 int ret;
707
708 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
709 if (ret)
710 return ret;
711
712 off = oobregion.offset;
713 len = oobregion.length;
714
715
716
717
718
719
720 if (chip->options & NAND_BUSWIDTH_16)
721 len = roundup(len, 2);
722
723 nand_read_oob_op(chip, page, off, oob + j, len);
724 j += len;
725 }
726
727 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
728 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
729
730 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
731 if (stat < 0) {
732 mtd->ecc_stats.failed++;
733 } else {
734 mtd->ecc_stats.corrected += stat;
735 max_bitflips = max_t(unsigned int, max_bitflips, stat);
736 }
737 }
738
739 return max_bitflips;
740}
741
742
743
744
745
746
747
748
749
750
751
752static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
753 uint8_t *read_ecc, uint8_t *calc_ecc)
754{
755 struct nand_chip *chip = mtd_to_nand(mtd);
756 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
757 void __iomem *regs = host->regs_va;
758 unsigned int bank = host->bank;
759 uint32_t err_idx[8];
760 uint32_t num_err, i;
761 uint32_t ecc1, ecc2, ecc3, ecc4;
762
763 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
764
765
766 if (likely(num_err == 0))
767 return 0;
768
769
770 if (unlikely(num_err > 8)) {
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
786 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
787
788 if ((bits_ecc + bits_data) <= 8) {
789 if (bits_data)
790 memset(dat, 0xff, chip->ecc.size);
791 return bits_data;
792 }
793
794 return -EBADMSG;
795 }
796
797
798
799
800
801
802
803
804
805
806 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
807 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
808 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
809 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
810
811 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
812 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
813 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
814 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
815 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
816 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
817 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
818 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
819
820 i = 0;
821 while (num_err--) {
822 change_bit(0, (unsigned long *)&err_idx[i]);
823 change_bit(1, (unsigned long *)&err_idx[i]);
824
825 if (err_idx[i] < chip->ecc.size * 8) {
826 change_bit(err_idx[i], (unsigned long *)dat);
827 i++;
828 }
829 }
830 return i;
831}
832
833static bool filter(struct dma_chan *chan, void *slave)
834{
835 chan->private = slave;
836 return true;
837}
838
839static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
840 struct fsmc_nand_data *host,
841 struct nand_chip *nand)
842{
843 struct device_node *np = pdev->dev.of_node;
844 u32 val;
845 int ret;
846
847 nand->options = 0;
848
849 if (!of_property_read_u32(np, "bank-width", &val)) {
850 if (val == 2) {
851 nand->options |= NAND_BUSWIDTH_16;
852 } else if (val != 1) {
853 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
854 return -EINVAL;
855 }
856 }
857
858 if (of_get_property(np, "nand-skip-bbtscan", NULL))
859 nand->options |= NAND_SKIP_BBTSCAN;
860
861 host->dev_timings = devm_kzalloc(&pdev->dev,
862 sizeof(*host->dev_timings), GFP_KERNEL);
863 if (!host->dev_timings)
864 return -ENOMEM;
865 ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
866 sizeof(*host->dev_timings));
867 if (ret)
868 host->dev_timings = NULL;
869
870
871 host->bank = 0;
872 if (!of_property_read_u32(np, "bank", &val)) {
873 if (val > 3) {
874 dev_err(&pdev->dev, "invalid bank %u\n", val);
875 return -EINVAL;
876 }
877 host->bank = val;
878 }
879 return 0;
880}
881
882
883
884
885
886static int __init fsmc_nand_probe(struct platform_device *pdev)
887{
888 struct fsmc_nand_data *host;
889 struct mtd_info *mtd;
890 struct nand_chip *nand;
891 struct resource *res;
892 dma_cap_mask_t mask;
893 int ret = 0;
894 u32 pid;
895 int i;
896
897
898 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
899 if (!host)
900 return -ENOMEM;
901
902 nand = &host->nand;
903
904 ret = fsmc_nand_probe_config_dt(pdev, host, nand);
905 if (ret)
906 return ret;
907
908 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
909 host->data_va = devm_ioremap_resource(&pdev->dev, res);
910 if (IS_ERR(host->data_va))
911 return PTR_ERR(host->data_va);
912
913 host->data_pa = (dma_addr_t)res->start;
914
915 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
916 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
917 if (IS_ERR(host->addr_va))
918 return PTR_ERR(host->addr_va);
919
920 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
921 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
922 if (IS_ERR(host->cmd_va))
923 return PTR_ERR(host->cmd_va);
924
925 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
926 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
927 if (IS_ERR(host->regs_va))
928 return PTR_ERR(host->regs_va);
929
930 host->clk = devm_clk_get(&pdev->dev, NULL);
931 if (IS_ERR(host->clk)) {
932 dev_err(&pdev->dev, "failed to fetch block clock\n");
933 return PTR_ERR(host->clk);
934 }
935
936 ret = clk_prepare_enable(host->clk);
937 if (ret)
938 return ret;
939
940
941
942
943
944 for (pid = 0, i = 0; i < 4; i++)
945 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
946 host->pid = pid;
947 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
948 "revision %02x, config %02x\n",
949 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
950 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
951
952 host->dev = &pdev->dev;
953
954 if (host->mode == USE_DMA_ACCESS)
955 init_completion(&host->dma_access_complete);
956
957
958 mtd = nand_to_mtd(&host->nand);
959 nand_set_controller_data(nand, host);
960 nand_set_flash_node(nand, pdev->dev.of_node);
961
962 mtd->dev.parent = &pdev->dev;
963 nand->IO_ADDR_R = host->data_va;
964 nand->IO_ADDR_W = host->data_va;
965 nand->cmd_ctrl = fsmc_cmd_ctrl;
966 nand->chip_delay = 30;
967
968
969
970
971
972 nand->ecc.mode = NAND_ECC_HW;
973 nand->ecc.hwctl = fsmc_enable_hwecc;
974 nand->ecc.size = 512;
975 nand->badblockbits = 7;
976
977 switch (host->mode) {
978 case USE_DMA_ACCESS:
979 dma_cap_zero(mask);
980 dma_cap_set(DMA_MEMCPY, mask);
981 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
982 if (!host->read_dma_chan) {
983 dev_err(&pdev->dev, "Unable to get read dma channel\n");
984 goto err_req_read_chnl;
985 }
986 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
987 if (!host->write_dma_chan) {
988 dev_err(&pdev->dev, "Unable to get write dma channel\n");
989 goto err_req_write_chnl;
990 }
991 nand->read_buf = fsmc_read_buf_dma;
992 nand->write_buf = fsmc_write_buf_dma;
993 break;
994
995 default:
996 case USE_WORD_ACCESS:
997 nand->read_buf = fsmc_read_buf;
998 nand->write_buf = fsmc_write_buf;
999 break;
1000 }
1001
1002 if (host->dev_timings)
1003 fsmc_nand_setup(host, host->dev_timings);
1004 else
1005 nand->setup_data_interface = fsmc_setup_data_interface;
1006
1007 if (AMBA_REV_BITS(host->pid) >= 8) {
1008 nand->ecc.read_page = fsmc_read_page_hwecc;
1009 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1010 nand->ecc.correct = fsmc_bch8_correct_data;
1011 nand->ecc.bytes = 13;
1012 nand->ecc.strength = 8;
1013 }
1014
1015
1016
1017
1018 ret = nand_scan_ident(mtd, 1, NULL);
1019 if (ret) {
1020 dev_err(&pdev->dev, "No NAND Device found!\n");
1021 goto err_scan_ident;
1022 }
1023
1024 if (AMBA_REV_BITS(host->pid) >= 8) {
1025 switch (mtd->oobsize) {
1026 case 16:
1027 case 64:
1028 case 128:
1029 case 224:
1030 case 256:
1031 break;
1032 default:
1033 dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1034 mtd->oobsize);
1035 ret = -EINVAL;
1036 goto err_probe;
1037 }
1038
1039 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1040 } else {
1041 switch (nand->ecc.mode) {
1042 case NAND_ECC_HW:
1043 dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1044 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1045 nand->ecc.correct = nand_correct_data;
1046 nand->ecc.bytes = 3;
1047 nand->ecc.strength = 1;
1048 break;
1049
1050 case NAND_ECC_SOFT:
1051 if (nand->ecc.algo == NAND_ECC_BCH) {
1052 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1053 break;
1054 }
1055
1056 case NAND_ECC_ON_DIE:
1057 break;
1058
1059 default:
1060 dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1061 goto err_probe;
1062 }
1063
1064
1065
1066
1067
1068 if (nand->ecc.mode == NAND_ECC_HW) {
1069 switch (mtd->oobsize) {
1070 case 16:
1071 case 64:
1072 case 128:
1073 mtd_set_ooblayout(mtd,
1074 &fsmc_ecc1_ooblayout_ops);
1075 break;
1076 default:
1077 dev_warn(&pdev->dev,
1078 "No oob scheme defined for oobsize %d\n",
1079 mtd->oobsize);
1080 ret = -EINVAL;
1081 goto err_probe;
1082 }
1083 }
1084 }
1085
1086
1087 ret = nand_scan_tail(mtd);
1088 if (ret)
1089 goto err_probe;
1090
1091 mtd->name = "nand";
1092 ret = mtd_device_register(mtd, NULL, 0);
1093 if (ret)
1094 goto err_probe;
1095
1096 platform_set_drvdata(pdev, host);
1097 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1098 return 0;
1099
1100err_probe:
1101err_scan_ident:
1102 if (host->mode == USE_DMA_ACCESS)
1103 dma_release_channel(host->write_dma_chan);
1104err_req_write_chnl:
1105 if (host->mode == USE_DMA_ACCESS)
1106 dma_release_channel(host->read_dma_chan);
1107err_req_read_chnl:
1108 clk_disable_unprepare(host->clk);
1109 return ret;
1110}
1111
1112
1113
1114
1115static int fsmc_nand_remove(struct platform_device *pdev)
1116{
1117 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1118
1119 if (host) {
1120 nand_release(nand_to_mtd(&host->nand));
1121
1122 if (host->mode == USE_DMA_ACCESS) {
1123 dma_release_channel(host->write_dma_chan);
1124 dma_release_channel(host->read_dma_chan);
1125 }
1126 clk_disable_unprepare(host->clk);
1127 }
1128
1129 return 0;
1130}
1131
1132#ifdef CONFIG_PM_SLEEP
1133static int fsmc_nand_suspend(struct device *dev)
1134{
1135 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1136 if (host)
1137 clk_disable_unprepare(host->clk);
1138 return 0;
1139}
1140
1141static int fsmc_nand_resume(struct device *dev)
1142{
1143 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1144 if (host) {
1145 clk_prepare_enable(host->clk);
1146 if (host->dev_timings)
1147 fsmc_nand_setup(host, host->dev_timings);
1148 }
1149 return 0;
1150}
1151#endif
1152
1153static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1154
1155static const struct of_device_id fsmc_nand_id_table[] = {
1156 { .compatible = "st,spear600-fsmc-nand" },
1157 { .compatible = "stericsson,fsmc-nand" },
1158 {}
1159};
1160MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1161
1162static struct platform_driver fsmc_nand_driver = {
1163 .remove = fsmc_nand_remove,
1164 .driver = {
1165 .name = "fsmc-nand",
1166 .of_match_table = fsmc_nand_id_table,
1167 .pm = &fsmc_nand_pm_ops,
1168 },
1169};
1170
1171module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1172
1173MODULE_LICENSE("GPL");
1174MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1175MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
1176