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11#ifndef __BCM_SYSPORT_H
12#define __BCM_SYSPORT_H
13
14#include <linux/if_vlan.h>
15
16
17#define DESC_ADDR_HI_STATUS_LEN 0x00
18#define DESC_ADDR_HI_SHIFT 0
19#define DESC_ADDR_HI_MASK 0xff
20#define DESC_STATUS_SHIFT 8
21#define DESC_STATUS_MASK 0x3ff
22#define DESC_LEN_SHIFT 18
23#define DESC_LEN_MASK 0x7fff
24#define DESC_ADDR_LO 0x04
25
26
27#define DESC_SIZE (WORDS_PER_DESC * sizeof(u32))
28
29
30#define RX_BUF_LENGTH 2048
31
32
33
34
35#define ENET_BRCM_TAG_LEN 4
36#define ENET_PAD 10
37#define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
38 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
39
40
41struct bcm_tsb {
42 u32 pcp_dei_vid;
43#define PCP_DEI_MASK 0xf
44#define VID_SHIFT 4
45#define VID_MASK 0xfff
46 u32 l4_ptr_dest_map;
47#define L4_CSUM_PTR_MASK 0x1ff
48#define L4_PTR_SHIFT 9
49#define L4_PTR_MASK 0x1ff
50#define L4_UDP (1 << 18)
51#define L4_LENGTH_VALID (1 << 19)
52#define DEST_MAP_SHIFT 20
53#define DEST_MAP_MASK 0x1ff
54};
55
56
57
58
59struct bcm_rsb {
60 u32 rx_status_len;
61 u32 brcm_egress_tag;
62};
63
64
65#define DESC_L4_CSUM (1 << 7)
66#define DESC_SOP (1 << 8)
67#define DESC_EOP (1 << 9)
68
69
70#define RX_STATUS_UCAST 0
71#define RX_STATUS_BCAST 0x04
72#define RX_STATUS_MCAST 0x08
73#define RX_STATUS_L2_MCAST 0x0c
74#define RX_STATUS_ERR (1 << 4)
75#define RX_STATUS_OVFLOW (1 << 5)
76#define RX_STATUS_PARSE_FAIL (1 << 6)
77
78
79#define TX_STATUS_VLAN_NO_ACT 0x00
80#define TX_STATUS_VLAN_PCP_TSB 0x01
81#define TX_STATUS_VLAN_QUEUE 0x02
82#define TX_STATUS_VLAN_VID_TSB 0x03
83#define TX_STATUS_OWR_CRC (1 << 2)
84#define TX_STATUS_APP_CRC (1 << 3)
85#define TX_STATUS_BRCM_TAG_NO_ACT 0
86#define TX_STATUS_BRCM_TAG_ZERO 0x10
87#define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20
88#define TX_STATUS_BRCM_TAG_ONE_TSB 0x30
89#define TX_STATUS_SKIP_BYTES (1 << 6)
90
91
92#define SYS_PORT_TOPCTRL_OFFSET 0
93#define REV_CNTL 0x00
94#define REV_MASK 0xffff
95
96#define RX_FLUSH_CNTL 0x04
97#define RX_FLUSH (1 << 0)
98
99#define TX_FLUSH_CNTL 0x08
100#define TX_FLUSH (1 << 0)
101
102#define MISC_CNTL 0x0c
103#define SYS_CLK_SEL (1 << 0)
104#define TDMA_EOP_SEL (1 << 1)
105
106
107#define SYS_PORT_INTRL2_0_OFFSET 0x200
108#define SYS_PORT_INTRL2_1_OFFSET 0x240
109#define INTRL2_CPU_STATUS 0x00
110#define INTRL2_CPU_SET 0x04
111#define INTRL2_CPU_CLEAR 0x08
112#define INTRL2_CPU_MASK_STATUS 0x0c
113#define INTRL2_CPU_MASK_SET 0x10
114#define INTRL2_CPU_MASK_CLEAR 0x14
115
116
117#define INTRL2_0_GISB_ERR (1 << 0)
118#define INTRL2_0_RBUF_OVFLOW (1 << 1)
119#define INTRL2_0_TBUF_UNDFLOW (1 << 2)
120#define INTRL2_0_MPD (1 << 3)
121#define INTRL2_0_BRCM_MATCH_TAG (1 << 4)
122#define INTRL2_0_RDMA_MBDONE (1 << 5)
123#define INTRL2_0_OVER_MAX_THRESH (1 << 6)
124#define INTRL2_0_BELOW_HYST_THRESH (1 << 7)
125#define INTRL2_0_FREE_LIST_EMPTY (1 << 8)
126#define INTRL2_0_TX_RING_FULL (1 << 9)
127#define INTRL2_0_DESC_ALLOC_ERR (1 << 10)
128#define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11)
129
130
131#define INTRL2_0_TDMA_MBDONE_SHIFT 12
132#define INTRL2_0_TDMA_MBDONE_MASK (0xffff << INTRL2_0_TDMA_MBDONE_SHIFT)
133
134
135#define SYS_PORT_RXCHK_OFFSET 0x300
136
137#define RXCHK_CONTROL 0x00
138#define RXCHK_EN (1 << 0)
139#define RXCHK_SKIP_FCS (1 << 1)
140#define RXCHK_BAD_CSUM_DIS (1 << 2)
141#define RXCHK_BRCM_TAG_EN (1 << 3)
142#define RXCHK_BRCM_TAG_MATCH_SHIFT 4
143#define RXCHK_BRCM_TAG_MATCH_MASK 0xff
144#define RXCHK_PARSE_TNL (1 << 12)
145#define RXCHK_VIOL_EN (1 << 13)
146#define RXCHK_VIOL_DIS (1 << 14)
147#define RXCHK_INCOM_PKT (1 << 15)
148#define RXCHK_V6_DUPEXT_EN (1 << 16)
149#define RXCHK_V6_DUPEXT_DIS (1 << 17)
150#define RXCHK_ETHERTYPE_DIS (1 << 18)
151#define RXCHK_L2_HDR_DIS (1 << 19)
152#define RXCHK_L3_HDR_DIS (1 << 20)
153#define RXCHK_MAC_RX_ERR_DIS (1 << 21)
154#define RXCHK_PARSE_AUTH (1 << 22)
155
156#define RXCHK_BRCM_TAG0 0x04
157#define RXCHK_BRCM_TAG(i) ((i) * RXCHK_BRCM_TAG0)
158#define RXCHK_BRCM_TAG0_MASK 0x24
159#define RXCHK_BRCM_TAG_MASK(i) ((i) * RXCHK_BRCM_TAG0_MASK)
160#define RXCHK_BRCM_TAG_MATCH_STATUS 0x44
161#define RXCHK_ETHERTYPE 0x48
162#define RXCHK_BAD_CSUM_CNTR 0x4C
163#define RXCHK_OTHER_DISC_CNTR 0x50
164
165
166#define SYS_PORT_TXCHK_OFFSET 0x380
167#define TXCHK_PKT_RDY_THRESH 0x00
168
169
170#define SYS_PORT_RBUF_OFFSET 0x400
171
172#define RBUF_CONTROL 0x00
173#define RBUF_RSB_EN (1 << 0)
174#define RBUF_4B_ALGN (1 << 1)
175#define RBUF_BRCM_TAG_STRIP (1 << 2)
176#define RBUF_BAD_PKT_DISC (1 << 3)
177#define RBUF_RESUME_THRESH_SHIFT 4
178#define RBUF_RESUME_THRESH_MASK 0xff
179#define RBUF_OK_TO_SEND_SHIFT 12
180#define RBUF_OK_TO_SEND_MASK 0xff
181#define RBUF_CRC_REPLACE (1 << 20)
182#define RBUF_OK_TO_SEND_MODE (1 << 21)
183
184#define RBUF_RSB_SWAP0 (1 << 22)
185#define RBUF_RSB_SWAP1 (1 << 23)
186#define RBUF_ACPI_EN (1 << 23)
187
188#define RBUF_PKT_RDY_THRESH 0x04
189
190#define RBUF_STATUS 0x08
191#define RBUF_WOL_MODE (1 << 0)
192#define RBUF_MPD (1 << 1)
193#define RBUF_ACPI (1 << 2)
194
195#define RBUF_OVFL_DISC_CNTR 0x0c
196#define RBUF_ERR_PKT_CNTR 0x10
197
198
199#define SYS_PORT_TBUF_OFFSET 0x600
200
201#define TBUF_CONTROL 0x00
202#define TBUF_BP_EN (1 << 0)
203#define TBUF_MAX_PKT_THRESH_SHIFT 1
204#define TBUF_MAX_PKT_THRESH_MASK 0x1f
205#define TBUF_FULL_THRESH_SHIFT 8
206#define TBUF_FULL_THRESH_MASK 0x1f
207
208
209#define SYS_PORT_UMAC_OFFSET 0x800
210
211#define UMAC_CMD 0x008
212#define CMD_TX_EN (1 << 0)
213#define CMD_RX_EN (1 << 1)
214#define CMD_SPEED_SHIFT 2
215#define CMD_SPEED_10 0
216#define CMD_SPEED_100 1
217#define CMD_SPEED_1000 2
218#define CMD_SPEED_2500 3
219#define CMD_SPEED_MASK 3
220#define CMD_PROMISC (1 << 4)
221#define CMD_PAD_EN (1 << 5)
222#define CMD_CRC_FWD (1 << 6)
223#define CMD_PAUSE_FWD (1 << 7)
224#define CMD_RX_PAUSE_IGNORE (1 << 8)
225#define CMD_TX_ADDR_INS (1 << 9)
226#define CMD_HD_EN (1 << 10)
227#define CMD_SW_RESET (1 << 13)
228#define CMD_LCL_LOOP_EN (1 << 15)
229#define CMD_AUTO_CONFIG (1 << 22)
230#define CMD_CNTL_FRM_EN (1 << 23)
231#define CMD_NO_LEN_CHK (1 << 24)
232#define CMD_RMT_LOOP_EN (1 << 25)
233#define CMD_PRBL_EN (1 << 27)
234#define CMD_TX_PAUSE_IGNORE (1 << 28)
235#define CMD_TX_RX_EN (1 << 29)
236#define CMD_RUNT_FILTER_DIS (1 << 30)
237
238#define UMAC_MAC0 0x00c
239#define UMAC_MAC1 0x010
240#define UMAC_MAX_FRAME_LEN 0x014
241
242#define UMAC_TX_FLUSH 0x334
243
244#define UMAC_MIB_START 0x400
245
246
247
248
249#define UMAC_MIB_STAT_OFFSET 0xc
250
251#define UMAC_MIB_CTRL 0x580
252#define MIB_RX_CNT_RST (1 << 0)
253#define MIB_RUNT_CNT_RST (1 << 1)
254#define MIB_TX_CNT_RST (1 << 2)
255
256
257#define UMAC_MPD_CTRL 0x620
258#define MPD_EN (1 << 0)
259#define MSEQ_LEN_SHIFT 16
260#define MSEQ_LEN_MASK 0xff
261#define PSW_EN (1 << 27)
262
263#define UMAC_PSW_MS 0x624
264#define UMAC_PSW_LS 0x628
265#define UMAC_MDF_CTRL 0x650
266#define UMAC_MDF_ADDR 0x654
267
268
269#define SYS_PORT_GIB_OFFSET 0x1000
270
271#define GIB_CONTROL 0x00
272#define GIB_TX_EN (1 << 0)
273#define GIB_RX_EN (1 << 1)
274#define GIB_TX_FLUSH (1 << 2)
275#define GIB_RX_FLUSH (1 << 3)
276#define GIB_GTX_CLK_SEL_SHIFT 4
277#define GIB_GTX_CLK_EXT_CLK (0 << GIB_GTX_CLK_SEL_SHIFT)
278#define GIB_GTX_CLK_125MHZ (1 << GIB_GTX_CLK_SEL_SHIFT)
279#define GIB_GTX_CLK_250MHZ (2 << GIB_GTX_CLK_SEL_SHIFT)
280#define GIB_FCS_STRIP (1 << 6)
281#define GIB_LCL_LOOP_EN (1 << 7)
282#define GIB_LCL_LOOP_TXEN (1 << 8)
283#define GIB_RMT_LOOP_EN (1 << 9)
284#define GIB_RMT_LOOP_RXEN (1 << 10)
285#define GIB_RX_PAUSE_EN (1 << 11)
286#define GIB_PREAMBLE_LEN_SHIFT 12
287#define GIB_PREAMBLE_LEN_MASK 0xf
288#define GIB_IPG_LEN_SHIFT 16
289#define GIB_IPG_LEN_MASK 0x3f
290#define GIB_PAD_EXTENSION_SHIFT 22
291#define GIB_PAD_EXTENSION_MASK 0x3f
292
293#define GIB_MAC1 0x08
294#define GIB_MAC0 0x0c
295
296
297#define SYS_PORT_RDMA_OFFSET 0x2000
298
299#define RDMA_CONTROL 0x1000
300#define RDMA_EN (1 << 0)
301#define RDMA_RING_CFG (1 << 1)
302#define RDMA_DISC_EN (1 << 2)
303#define RDMA_BUF_DATA_OFFSET_SHIFT 4
304#define RDMA_BUF_DATA_OFFSET_MASK 0x3ff
305
306#define RDMA_STATUS 0x1004
307#define RDMA_DISABLED (1 << 0)
308#define RDMA_DESC_RAM_INIT_BUSY (1 << 1)
309#define RDMA_BP_STATUS (1 << 2)
310
311#define RDMA_SCB_BURST_SIZE 0x1008
312
313#define RDMA_RING_BUF_SIZE 0x100c
314#define RDMA_RING_SIZE_SHIFT 16
315
316#define RDMA_WRITE_PTR_HI 0x1010
317#define RDMA_WRITE_PTR_LO 0x1014
318#define RDMA_PROD_INDEX 0x1018
319#define RDMA_PROD_INDEX_MASK 0xffff
320
321#define RDMA_CONS_INDEX 0x101c
322#define RDMA_CONS_INDEX_MASK 0xffff
323
324#define RDMA_START_ADDR_HI 0x1020
325#define RDMA_START_ADDR_LO 0x1024
326#define RDMA_END_ADDR_HI 0x1028
327#define RDMA_END_ADDR_LO 0x102c
328
329#define RDMA_MBDONE_INTR 0x1030
330#define RDMA_INTR_THRESH_MASK 0x1ff
331#define RDMA_TIMEOUT_SHIFT 16
332#define RDMA_TIMEOUT_MASK 0xffff
333
334#define RDMA_XON_XOFF_THRESH 0x1034
335#define RDMA_XON_XOFF_THRESH_MASK 0xffff
336#define RDMA_XOFF_THRESH_SHIFT 16
337
338#define RDMA_READ_PTR_HI 0x1038
339#define RDMA_READ_PTR_LO 0x103c
340
341#define RDMA_OVERRIDE 0x1040
342#define RDMA_LE_MODE (1 << 0)
343#define RDMA_REG_MODE (1 << 1)
344
345#define RDMA_TEST 0x1044
346#define RDMA_TP_OUT_SEL (1 << 0)
347#define RDMA_MEM_SEL (1 << 1)
348
349#define RDMA_DEBUG 0x1048
350
351
352#define TDMA_NUM_RINGS 32
353#define TDMA_PORT_SIZE DESC_SIZE
354
355#define SYS_PORT_TDMA_OFFSET 0x4000
356#define TDMA_WRITE_PORT_OFFSET 0x0000
357#define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \
358 (i) * TDMA_PORT_SIZE)
359#define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \
360 sizeof(u32) + (i) * TDMA_PORT_SIZE)
361
362#define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \
363 (TDMA_NUM_RINGS * TDMA_PORT_SIZE))
364#define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \
365 (i) * TDMA_PORT_SIZE)
366#define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \
367 sizeof(u32) + (i) * TDMA_PORT_SIZE)
368
369#define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \
370 (TDMA_NUM_RINGS * TDMA_PORT_SIZE))
371#define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \
372 (i) * sizeof(u32))
373
374#define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \
375 (TDMA_NUM_RINGS * sizeof(u32)))
376
377
378#define RING_HEAD_TAIL_PTR 0x00
379#define RING_HEAD_MASK 0x7ff
380#define RING_TAIL_SHIFT 11
381#define RING_TAIL_MASK 0x7ff
382#define RING_FLUSH (1 << 24)
383#define RING_EN (1 << 25)
384
385#define RING_COUNT 0x04
386#define RING_COUNT_MASK 0x7ff
387#define RING_BUFF_DONE_SHIFT 11
388#define RING_BUFF_DONE_MASK 0x7ff
389
390#define RING_MAX_HYST 0x08
391#define RING_MAX_THRESH_MASK 0x7ff
392#define RING_HYST_THRESH_SHIFT 11
393#define RING_HYST_THRESH_MASK 0x7ff
394
395#define RING_INTR_CONTROL 0x0c
396#define RING_INTR_THRESH_MASK 0x7ff
397#define RING_EMPTY_INTR_EN (1 << 15)
398#define RING_TIMEOUT_SHIFT 16
399#define RING_TIMEOUT_MASK 0xffff
400
401#define RING_PROD_CONS_INDEX 0x10
402#define RING_PROD_INDEX_MASK 0xffff
403#define RING_CONS_INDEX_SHIFT 16
404#define RING_CONS_INDEX_MASK 0xffff
405
406#define RING_MAPPING 0x14
407#define RING_QID_MASK 0x7
408#define RING_PORT_ID_SHIFT 3
409#define RING_PORT_ID_MASK 0x7
410#define RING_IGNORE_STATUS (1 << 6)
411#define RING_FAILOVER_EN (1 << 7)
412#define RING_CREDIT_SHIFT 8
413#define RING_CREDIT_MASK 0xffff
414
415#define RING_PCP_DEI_VID 0x18
416#define RING_VID_MASK 0x7ff
417#define RING_DEI (1 << 12)
418#define RING_PCP_SHIFT 13
419#define RING_PCP_MASK 0x7
420#define RING_PKT_SIZE_ADJ_SHIFT 16
421#define RING_PKT_SIZE_ADJ_MASK 0xf
422
423#define TDMA_DESC_RING_SIZE 28
424
425
426#define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \
427 ((i) * TDMA_DESC_RING_SIZE))
428
429
430#define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \
431 RING_HEAD_TAIL_PTR)
432#define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \
433 RING_COUNT)
434#define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \
435 RING_MAX_HYST)
436#define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \
437 RING_INTR_CONTROL)
438#define TDMA_DESC_RING_PROD_CONS_INDEX(i) \
439 (TDMA_DESC_RING_BASE(i) + \
440 RING_PROD_CONS_INDEX)
441#define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \
442 RING_MAPPING)
443#define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \
444 RING_PCP_DEI_VID)
445
446#define TDMA_CONTROL 0x600
447#define TDMA_EN 0
448#define TSB_EN 1
449
450
451
452#define TSB_SWAP0 2
453#define TSB_SWAP1 3
454#define ACB_ALGO 3
455#define BUF_DATA_OFFSET_SHIFT 4
456#define BUF_DATA_OFFSET_MASK 0x3ff
457#define VLAN_EN 14
458#define SW_BRCM_TAG 15
459#define WNC_KPT_SIZE_UPDATE 16
460#define SYNC_PKT_SIZE 17
461#define ACH_TXDONE_DELAY_SHIFT 18
462#define ACH_TXDONE_DELAY_MASK 0xff
463
464#define TDMA_STATUS 0x604
465#define TDMA_DISABLED (1 << 0)
466#define TDMA_LL_RAM_INIT_BUSY (1 << 1)
467
468#define TDMA_SCB_BURST_SIZE 0x608
469#define TDMA_OVER_MAX_THRESH_STATUS 0x60c
470#define TDMA_OVER_HYST_THRESH_STATUS 0x610
471#define TDMA_TPID 0x614
472
473#define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618
474#define TDMA_FREE_HEAD_MASK 0x7ff
475#define TDMA_FREE_TAIL_SHIFT 11
476#define TDMA_FREE_TAIL_MASK 0x7ff
477
478#define TDMA_FREE_LIST_COUNT 0x61c
479#define TDMA_FREE_LIST_COUNT_MASK 0x7ff
480
481#define TDMA_TIER2_ARB_CTRL 0x620
482#define TDMA_ARB_MODE_RR 0
483#define TDMA_ARB_MODE_WEIGHT_RR 0x1
484#define TDMA_ARB_MODE_STRICT 0x2
485#define TDMA_ARB_MODE_DEFICIT_RR 0x3
486#define TDMA_CREDIT_SHIFT 4
487#define TDMA_CREDIT_MASK 0xffff
488
489#define TDMA_TIER1_ARB_0_CTRL 0x624
490#define TDMA_ARB_EN (1 << 0)
491
492#define TDMA_TIER1_ARB_0_QUEUE_EN 0x628
493#define TDMA_TIER1_ARB_1_CTRL 0x62c
494#define TDMA_TIER1_ARB_1_QUEUE_EN 0x630
495#define TDMA_TIER1_ARB_2_CTRL 0x634
496#define TDMA_TIER1_ARB_2_QUEUE_EN 0x638
497#define TDMA_TIER1_ARB_3_CTRL 0x63c
498#define TDMA_TIER1_ARB_3_QUEUE_EN 0x640
499
500#define TDMA_SCB_ENDIAN_OVERRIDE 0x644
501#define TDMA_LE_MODE (1 << 0)
502#define TDMA_REG_MODE (1 << 1)
503
504#define TDMA_TEST 0x648
505#define TDMA_TP_OUT_SEL (1 << 0)
506#define TDMA_MEM_TM (1 << 1)
507
508#define TDMA_DEBUG 0x64c
509
510
511struct dma_desc {
512 u32 addr_status_len;
513 u32 addr_lo;
514};
515
516
517#define SP_NUM_HW_RX_DESC_WORDS 1024
518#define SP_LT_NUM_HW_RX_DESC_WORDS 256
519
520
521#define SP_NUM_TX_DESC 1536
522#define SP_LT_NUM_TX_DESC 256
523
524#define WORDS_PER_DESC (sizeof(struct dma_desc) / sizeof(u32))
525
526
527struct bcm_sysport_pkt_counters {
528 u32 cnt_64;
529 u32 cnt_127;
530 u32 cnt_255;
531 u32 cnt_511;
532 u32 cnt_1023;
533 u32 cnt_1518;
534 u32 cnt_mgv;
535 u32 cnt_2047;
536 u32 cnt_4095;
537 u32 cnt_9216;
538};
539
540
541struct bcm_sysport_rx_counters {
542 struct bcm_sysport_pkt_counters pkt_cnt;
543 u32 pkt;
544 u32 bytes;
545 u32 mca;
546 u32 bca;
547 u32 fcs;
548 u32 cf;
549 u32 pf;
550 u32 uo;
551 u32 aln;
552 u32 flr;
553 u32 cde;
554 u32 fcr;
555 u32 ovr;
556 u32 jbr;
557 u32 mtue;
558 u32 pok;
559 u32 uc;
560 u32 ppp;
561 u32 rcrc;
562};
563
564
565struct bcm_sysport_tx_counters {
566 struct bcm_sysport_pkt_counters pkt_cnt;
567 u32 pkts;
568 u32 mca;
569 u32 bca;
570 u32 pf;
571 u32 cf;
572 u32 fcs;
573 u32 ovr;
574 u32 drf;
575 u32 edf;
576 u32 scl;
577 u32 mcl;
578 u32 lcl;
579 u32 ecl;
580 u32 frg;
581 u32 ncl;
582 u32 jbr;
583 u32 bytes;
584 u32 pok;
585 u32 uc;
586};
587
588struct bcm_sysport_mib {
589 struct bcm_sysport_rx_counters rx;
590 struct bcm_sysport_tx_counters tx;
591 u32 rx_runt_cnt;
592 u32 rx_runt_fcs;
593 u32 rx_runt_fcs_align;
594 u32 rx_runt_bytes;
595 u32 rxchk_bad_csum;
596 u32 rxchk_other_pkt_disc;
597 u32 rbuf_ovflow_cnt;
598 u32 rbuf_err_cnt;
599 u32 alloc_rx_buff_failed;
600 u32 rx_dma_failed;
601 u32 tx_dma_failed;
602};
603
604
605enum bcm_sysport_stat_type {
606 BCM_SYSPORT_STAT_NETDEV = -1,
607 BCM_SYSPORT_STAT_NETDEV64,
608 BCM_SYSPORT_STAT_MIB_RX,
609 BCM_SYSPORT_STAT_MIB_TX,
610 BCM_SYSPORT_STAT_RUNT,
611 BCM_SYSPORT_STAT_RXCHK,
612 BCM_SYSPORT_STAT_RBUF,
613 BCM_SYSPORT_STAT_SOFT,
614};
615
616
617#define STAT_NETDEV(m) { \
618 .stat_string = __stringify(m), \
619 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
620 .stat_offset = offsetof(struct net_device_stats, m), \
621 .type = BCM_SYSPORT_STAT_NETDEV, \
622}
623
624#define STAT_NETDEV64(m) { \
625 .stat_string = __stringify(m), \
626 .stat_sizeof = sizeof(((struct bcm_sysport_stats64 *)0)->m), \
627 .stat_offset = offsetof(struct bcm_sysport_stats64, m), \
628 .type = BCM_SYSPORT_STAT_NETDEV64, \
629}
630
631#define STAT_MIB(str, m, _type) { \
632 .stat_string = str, \
633 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
634 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
635 .type = _type, \
636}
637
638#define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX)
639#define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX)
640#define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT)
641#define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT)
642
643#define STAT_RXCHK(str, m, ofs) { \
644 .stat_string = str, \
645 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
646 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
647 .type = BCM_SYSPORT_STAT_RXCHK, \
648 .reg_offset = ofs, \
649}
650
651#define STAT_RBUF(str, m, ofs) { \
652 .stat_string = str, \
653 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
654 .stat_offset = offsetof(struct bcm_sysport_priv, m), \
655 .type = BCM_SYSPORT_STAT_RBUF, \
656 .reg_offset = ofs, \
657}
658
659
660#define NUM_SYSPORT_TXQ_STAT 2
661
662struct bcm_sysport_stats {
663 char stat_string[ETH_GSTRING_LEN];
664 int stat_sizeof;
665 int stat_offset;
666 enum bcm_sysport_stat_type type;
667
668 u16 reg_offset;
669};
670
671struct bcm_sysport_stats64 {
672
673 u64 rx_packets;
674 u64 rx_bytes;
675 u64 tx_packets;
676 u64 tx_bytes;
677};
678
679
680struct bcm_sysport_cb {
681 struct sk_buff *skb;
682 void __iomem *bd_addr;
683
684 DEFINE_DMA_UNMAP_ADDR(dma_addr);
685 DEFINE_DMA_UNMAP_LEN(dma_len);
686};
687
688enum bcm_sysport_type {
689 SYSTEMPORT = 0,
690 SYSTEMPORT_LITE,
691};
692
693struct bcm_sysport_hw_params {
694 bool is_lite;
695 unsigned int num_rx_desc_words;
696};
697
698
699struct bcm_sysport_tx_ring {
700 spinlock_t lock;
701 struct napi_struct napi;
702 dma_addr_t desc_dma;
703 unsigned int index;
704 unsigned int size;
705 unsigned int alloc_size;
706 unsigned int desc_count;
707 unsigned int curr_desc;
708 unsigned int c_index;
709 unsigned int clean_index;
710 struct bcm_sysport_cb *cbs;
711 struct dma_desc *desc_cpu;
712 struct bcm_sysport_priv *priv;
713 unsigned long packets;
714 unsigned long bytes;
715 unsigned int switch_queue;
716 unsigned int switch_port;
717 bool inspect;
718};
719
720
721struct bcm_sysport_priv {
722 void __iomem *base;
723 u32 irq0_stat;
724 u32 irq0_mask;
725 u32 irq1_stat;
726 u32 irq1_mask;
727 bool is_lite;
728 unsigned int num_rx_desc_words;
729 struct napi_struct napi ____cacheline_aligned;
730 struct net_device *netdev;
731 struct platform_device *pdev;
732 int irq0;
733 int irq1;
734 int wol_irq;
735
736
737 struct bcm_sysport_tx_ring *tx_rings;
738
739
740 void __iomem *rx_bds;
741 struct bcm_sysport_cb *rx_cbs;
742 unsigned int num_rx_bds;
743 unsigned int rx_read_ptr;
744 unsigned int rx_c_index;
745
746
747 struct device_node *phy_dn;
748 phy_interface_t phy_interface;
749 int old_pause;
750 int old_link;
751 int old_duplex;
752
753
754 unsigned int rx_chk_en:1;
755 unsigned int tsb_en:1;
756 unsigned int crc_fwd:1;
757 u16 rev;
758 u32 wolopts;
759 unsigned int wol_irq_disabled:1;
760
761
762 struct bcm_sysport_mib mib;
763
764
765 u32 msg_enable;
766
767 struct bcm_sysport_stats64 stats64;
768
769
770 struct u64_stats_sync syncp;
771
772
773 struct notifier_block dsa_notifier;
774 unsigned int per_port_num_tx_queues;
775 unsigned long queue_bitmap;
776 struct bcm_sysport_tx_ring *ring_map[DSA_MAX_PORTS * 8];
777
778};
779#endif
780