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10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12#include <linux/bcma/bcma.h>
13#include <linux/etherdevice.h>
14#include <linux/interrupt.h>
15#include <linux/bcm47xx_nvram.h>
16#include <linux/phy.h>
17#include <linux/phy_fixed.h>
18#include <net/dsa.h>
19#include "bgmac.h"
20
21static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask,
22 u32 value, int timeout)
23{
24 u32 val;
25 int i;
26
27 for (i = 0; i < timeout / 10; i++) {
28 val = bgmac_read(bgmac, reg);
29 if ((val & mask) == value)
30 return true;
31 udelay(10);
32 }
33 dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg);
34 return false;
35}
36
37
38
39
40
41static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
42{
43 u32 val;
44 int i;
45
46 if (!ring->mmio_base)
47 return;
48
49
50
51
52
53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
54 BGMAC_DMA_TX_SUSPEND);
55 for (i = 0; i < 10000 / 10; i++) {
56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
57 val &= BGMAC_DMA_TX_STAT;
58 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
59 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
60 val == BGMAC_DMA_TX_STAT_STOPPED) {
61 i = 0;
62 break;
63 }
64 udelay(10);
65 }
66 if (i)
67 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
68 ring->mmio_base, val);
69
70
71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
72 if (!bgmac_wait_value(bgmac,
73 ring->mmio_base + BGMAC_DMA_TX_STATUS,
74 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
75 10000)) {
76 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
77 ring->mmio_base);
78 udelay(300);
79 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
80 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
81 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
82 ring->mmio_base);
83 }
84}
85
86static void bgmac_dma_tx_enable(struct bgmac *bgmac,
87 struct bgmac_dma_ring *ring)
88{
89 u32 ctl;
90
91 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
92 if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
93 ctl &= ~BGMAC_DMA_TX_BL_MASK;
94 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
95
96 ctl &= ~BGMAC_DMA_TX_MR_MASK;
97 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
98
99 ctl &= ~BGMAC_DMA_TX_PC_MASK;
100 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
101
102 ctl &= ~BGMAC_DMA_TX_PT_MASK;
103 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
104 }
105 ctl |= BGMAC_DMA_TX_ENABLE;
106 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
107 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
108}
109
110static void
111bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
112 int i, int len, u32 ctl0)
113{
114 struct bgmac_slot_info *slot;
115 struct bgmac_dma_desc *dma_desc;
116 u32 ctl1;
117
118 if (i == BGMAC_TX_RING_SLOTS - 1)
119 ctl0 |= BGMAC_DESC_CTL0_EOT;
120
121 ctl1 = len & BGMAC_DESC_CTL1_LEN;
122
123 slot = &ring->slots[i];
124 dma_desc = &ring->cpu_base[i];
125 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
126 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
127 dma_desc->ctl0 = cpu_to_le32(ctl0);
128 dma_desc->ctl1 = cpu_to_le32(ctl1);
129}
130
131static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
132 struct bgmac_dma_ring *ring,
133 struct sk_buff *skb)
134{
135 struct device *dma_dev = bgmac->dma_dev;
136 struct net_device *net_dev = bgmac->net_dev;
137 int index = ring->end % BGMAC_TX_RING_SLOTS;
138 struct bgmac_slot_info *slot = &ring->slots[index];
139 int nr_frags;
140 u32 flags;
141 int i;
142
143 if (skb->len > BGMAC_DESC_CTL1_LEN) {
144 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
145 goto err_drop;
146 }
147
148 if (skb->ip_summed == CHECKSUM_PARTIAL)
149 skb_checksum_help(skb);
150
151 nr_frags = skb_shinfo(skb)->nr_frags;
152
153
154
155
156 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
157 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
158 netif_stop_queue(net_dev);
159 return NETDEV_TX_BUSY;
160 }
161
162 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
163 DMA_TO_DEVICE);
164 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
165 goto err_dma_head;
166
167 flags = BGMAC_DESC_CTL0_SOF;
168 if (!nr_frags)
169 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
170
171 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
172 flags = 0;
173
174 for (i = 0; i < nr_frags; i++) {
175 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
176 int len = skb_frag_size(frag);
177
178 index = (index + 1) % BGMAC_TX_RING_SLOTS;
179 slot = &ring->slots[index];
180 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
181 len, DMA_TO_DEVICE);
182 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
183 goto err_dma;
184
185 if (i == nr_frags - 1)
186 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
187
188 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
189 }
190
191 slot->skb = skb;
192 ring->end += nr_frags + 1;
193 netdev_sent_queue(net_dev, skb->len);
194
195 wmb();
196
197
198
199
200 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
201 ring->index_base +
202 (ring->end % BGMAC_TX_RING_SLOTS) *
203 sizeof(struct bgmac_dma_desc));
204
205 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
206 netif_stop_queue(net_dev);
207
208 return NETDEV_TX_OK;
209
210err_dma:
211 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
212 DMA_TO_DEVICE);
213
214 while (i-- > 0) {
215 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
216 struct bgmac_slot_info *slot = &ring->slots[index];
217 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
218 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
219
220 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
221 }
222
223err_dma_head:
224 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
225 ring->mmio_base);
226
227err_drop:
228 dev_kfree_skb(skb);
229 net_dev->stats.tx_dropped++;
230 net_dev->stats.tx_errors++;
231 return NETDEV_TX_OK;
232}
233
234
235static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
236{
237 struct device *dma_dev = bgmac->dma_dev;
238 int empty_slot;
239 bool freed = false;
240 unsigned bytes_compl = 0, pkts_compl = 0;
241
242
243 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
244 empty_slot &= BGMAC_DMA_TX_STATDPTR;
245 empty_slot -= ring->index_base;
246 empty_slot &= BGMAC_DMA_TX_STATDPTR;
247 empty_slot /= sizeof(struct bgmac_dma_desc);
248
249 while (ring->start != ring->end) {
250 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
251 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
252 u32 ctl0, ctl1;
253 int len;
254
255 if (slot_idx == empty_slot)
256 break;
257
258 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
259 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
260 len = ctl1 & BGMAC_DESC_CTL1_LEN;
261 if (ctl0 & BGMAC_DESC_CTL0_SOF)
262
263 dma_unmap_single(dma_dev, slot->dma_addr, len,
264 DMA_TO_DEVICE);
265 else
266 dma_unmap_page(dma_dev, slot->dma_addr, len,
267 DMA_TO_DEVICE);
268
269 if (slot->skb) {
270 bgmac->net_dev->stats.tx_bytes += slot->skb->len;
271 bgmac->net_dev->stats.tx_packets++;
272 bytes_compl += slot->skb->len;
273 pkts_compl++;
274
275
276 dev_kfree_skb(slot->skb);
277 slot->skb = NULL;
278 }
279
280 slot->dma_addr = 0;
281 ring->start++;
282 freed = true;
283 }
284
285 if (!pkts_compl)
286 return;
287
288 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
289
290 if (netif_queue_stopped(bgmac->net_dev))
291 netif_wake_queue(bgmac->net_dev);
292}
293
294static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
295{
296 if (!ring->mmio_base)
297 return;
298
299 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
300 if (!bgmac_wait_value(bgmac,
301 ring->mmio_base + BGMAC_DMA_RX_STATUS,
302 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
303 10000))
304 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
305 ring->mmio_base);
306}
307
308static void bgmac_dma_rx_enable(struct bgmac *bgmac,
309 struct bgmac_dma_ring *ring)
310{
311 u32 ctl;
312
313 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
314
315
316 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
317
318 if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
319 ctl &= ~BGMAC_DMA_RX_BL_MASK;
320 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
321
322 ctl &= ~BGMAC_DMA_RX_PC_MASK;
323 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
324
325 ctl &= ~BGMAC_DMA_RX_PT_MASK;
326 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
327 }
328 ctl |= BGMAC_DMA_RX_ENABLE;
329 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
330 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
331 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
332 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
333}
334
335static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
336 struct bgmac_slot_info *slot)
337{
338 struct device *dma_dev = bgmac->dma_dev;
339 dma_addr_t dma_addr;
340 struct bgmac_rx_header *rx;
341 void *buf;
342
343
344 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
345 if (!buf)
346 return -ENOMEM;
347
348
349 rx = buf + BGMAC_RX_BUF_OFFSET;
350 rx->len = cpu_to_le16(0xdead);
351 rx->flags = cpu_to_le16(0xbeef);
352
353
354 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
355 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
356 if (dma_mapping_error(dma_dev, dma_addr)) {
357 netdev_err(bgmac->net_dev, "DMA mapping error\n");
358 put_page(virt_to_head_page(buf));
359 return -ENOMEM;
360 }
361
362
363 slot->buf = buf;
364 slot->dma_addr = dma_addr;
365
366 return 0;
367}
368
369static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
370 struct bgmac_dma_ring *ring)
371{
372 dma_wmb();
373
374 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
375 ring->index_base +
376 ring->end * sizeof(struct bgmac_dma_desc));
377}
378
379static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
380 struct bgmac_dma_ring *ring, int desc_idx)
381{
382 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
383 u32 ctl0 = 0, ctl1 = 0;
384
385 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
386 ctl0 |= BGMAC_DESC_CTL0_EOT;
387 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
388
389
390
391
392
393 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
394 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
395 dma_desc->ctl0 = cpu_to_le32(ctl0);
396 dma_desc->ctl1 = cpu_to_le32(ctl1);
397
398 ring->end = desc_idx;
399}
400
401static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
402 struct bgmac_slot_info *slot)
403{
404 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
405
406 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
407 DMA_FROM_DEVICE);
408 rx->len = cpu_to_le16(0xdead);
409 rx->flags = cpu_to_le16(0xbeef);
410 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
411 DMA_FROM_DEVICE);
412}
413
414static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
415 int weight)
416{
417 u32 end_slot;
418 int handled = 0;
419
420 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
421 end_slot &= BGMAC_DMA_RX_STATDPTR;
422 end_slot -= ring->index_base;
423 end_slot &= BGMAC_DMA_RX_STATDPTR;
424 end_slot /= sizeof(struct bgmac_dma_desc);
425
426 while (ring->start != end_slot) {
427 struct device *dma_dev = bgmac->dma_dev;
428 struct bgmac_slot_info *slot = &ring->slots[ring->start];
429 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
430 struct sk_buff *skb;
431 void *buf = slot->buf;
432 dma_addr_t dma_addr = slot->dma_addr;
433 u16 len, flags;
434
435 do {
436
437 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
438 bgmac_dma_rx_poison_buf(dma_dev, slot);
439 break;
440 }
441
442
443 dma_unmap_single(dma_dev, dma_addr,
444 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
445
446
447 len = le16_to_cpu(rx->len);
448 flags = le16_to_cpu(rx->flags);
449
450
451 if (len == 0xdead && flags == 0xbeef) {
452 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
453 ring->start);
454 put_page(virt_to_head_page(buf));
455 bgmac->net_dev->stats.rx_errors++;
456 break;
457 }
458
459 if (len > BGMAC_RX_ALLOC_SIZE) {
460 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
461 ring->start);
462 put_page(virt_to_head_page(buf));
463 bgmac->net_dev->stats.rx_length_errors++;
464 bgmac->net_dev->stats.rx_errors++;
465 break;
466 }
467
468
469 len -= ETH_FCS_LEN;
470
471 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
472 if (unlikely(!skb)) {
473 netdev_err(bgmac->net_dev, "build_skb failed\n");
474 put_page(virt_to_head_page(buf));
475 bgmac->net_dev->stats.rx_errors++;
476 break;
477 }
478 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
479 BGMAC_RX_BUF_OFFSET + len);
480 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
481 BGMAC_RX_BUF_OFFSET);
482
483 skb_checksum_none_assert(skb);
484 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
485 bgmac->net_dev->stats.rx_bytes += len;
486 bgmac->net_dev->stats.rx_packets++;
487 napi_gro_receive(&bgmac->napi, skb);
488 handled++;
489 } while (0);
490
491 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
492
493 if (++ring->start >= BGMAC_RX_RING_SLOTS)
494 ring->start = 0;
495
496 if (handled >= weight)
497 break;
498 }
499
500 bgmac_dma_rx_update_index(bgmac, ring);
501
502 return handled;
503}
504
505
506static bool bgmac_dma_unaligned(struct bgmac *bgmac,
507 struct bgmac_dma_ring *ring,
508 enum bgmac_dma_ring_type ring_type)
509{
510 switch (ring_type) {
511 case BGMAC_DMA_RING_TX:
512 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
513 0xff0);
514 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
515 return true;
516 break;
517 case BGMAC_DMA_RING_RX:
518 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
519 0xff0);
520 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
521 return true;
522 break;
523 }
524 return false;
525}
526
527static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
528 struct bgmac_dma_ring *ring)
529{
530 struct device *dma_dev = bgmac->dma_dev;
531 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
532 struct bgmac_slot_info *slot;
533 int i;
534
535 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
536 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
537
538 slot = &ring->slots[i];
539 dev_kfree_skb(slot->skb);
540
541 if (!slot->dma_addr)
542 continue;
543
544 if (slot->skb)
545 dma_unmap_single(dma_dev, slot->dma_addr,
546 len, DMA_TO_DEVICE);
547 else
548 dma_unmap_page(dma_dev, slot->dma_addr,
549 len, DMA_TO_DEVICE);
550 }
551}
552
553static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
554 struct bgmac_dma_ring *ring)
555{
556 struct device *dma_dev = bgmac->dma_dev;
557 struct bgmac_slot_info *slot;
558 int i;
559
560 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
561 slot = &ring->slots[i];
562 if (!slot->dma_addr)
563 continue;
564
565 dma_unmap_single(dma_dev, slot->dma_addr,
566 BGMAC_RX_BUF_SIZE,
567 DMA_FROM_DEVICE);
568 put_page(virt_to_head_page(slot->buf));
569 slot->dma_addr = 0;
570 }
571}
572
573static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
574 struct bgmac_dma_ring *ring,
575 int num_slots)
576{
577 struct device *dma_dev = bgmac->dma_dev;
578 int size;
579
580 if (!ring->cpu_base)
581 return;
582
583
584 size = num_slots * sizeof(struct bgmac_dma_desc);
585 dma_free_coherent(dma_dev, size, ring->cpu_base,
586 ring->dma_base);
587}
588
589static void bgmac_dma_cleanup(struct bgmac *bgmac)
590{
591 int i;
592
593 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
594 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
595
596 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
597 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
598}
599
600static void bgmac_dma_free(struct bgmac *bgmac)
601{
602 int i;
603
604 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
605 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
606 BGMAC_TX_RING_SLOTS);
607
608 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
609 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
610 BGMAC_RX_RING_SLOTS);
611}
612
613static int bgmac_dma_alloc(struct bgmac *bgmac)
614{
615 struct device *dma_dev = bgmac->dma_dev;
616 struct bgmac_dma_ring *ring;
617 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
618 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
619 int size;
620 int err;
621 int i;
622
623 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
624 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
625
626 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
627 if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) {
628 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
629 return -ENOTSUPP;
630 }
631 }
632
633 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
634 ring = &bgmac->tx_ring[i];
635 ring->mmio_base = ring_base[i];
636
637
638 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
639 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
640 &ring->dma_base,
641 GFP_KERNEL);
642 if (!ring->cpu_base) {
643 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
644 ring->mmio_base);
645 goto err_dma_free;
646 }
647
648 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
649 BGMAC_DMA_RING_TX);
650 if (ring->unaligned)
651 ring->index_base = lower_32_bits(ring->dma_base);
652 else
653 ring->index_base = 0;
654
655
656 }
657
658 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
659 ring = &bgmac->rx_ring[i];
660 ring->mmio_base = ring_base[i];
661
662
663 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
664 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
665 &ring->dma_base,
666 GFP_KERNEL);
667 if (!ring->cpu_base) {
668 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
669 ring->mmio_base);
670 err = -ENOMEM;
671 goto err_dma_free;
672 }
673
674 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
675 BGMAC_DMA_RING_RX);
676 if (ring->unaligned)
677 ring->index_base = lower_32_bits(ring->dma_base);
678 else
679 ring->index_base = 0;
680 }
681
682 return 0;
683
684err_dma_free:
685 bgmac_dma_free(bgmac);
686 return -ENOMEM;
687}
688
689static int bgmac_dma_init(struct bgmac *bgmac)
690{
691 struct bgmac_dma_ring *ring;
692 int i, err;
693
694 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
695 ring = &bgmac->tx_ring[i];
696
697 if (!ring->unaligned)
698 bgmac_dma_tx_enable(bgmac, ring);
699 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
700 lower_32_bits(ring->dma_base));
701 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
702 upper_32_bits(ring->dma_base));
703 if (ring->unaligned)
704 bgmac_dma_tx_enable(bgmac, ring);
705
706 ring->start = 0;
707 ring->end = 0;
708 }
709
710 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
711 int j;
712
713 ring = &bgmac->rx_ring[i];
714
715 if (!ring->unaligned)
716 bgmac_dma_rx_enable(bgmac, ring);
717 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
718 lower_32_bits(ring->dma_base));
719 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
720 upper_32_bits(ring->dma_base));
721 if (ring->unaligned)
722 bgmac_dma_rx_enable(bgmac, ring);
723
724 ring->start = 0;
725 ring->end = 0;
726 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
727 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
728 if (err)
729 goto error;
730
731 bgmac_dma_rx_setup_desc(bgmac, ring, j);
732 }
733
734 bgmac_dma_rx_update_index(bgmac, ring);
735 }
736
737 return 0;
738
739error:
740 bgmac_dma_cleanup(bgmac);
741 return err;
742}
743
744
745
746
747
748
749
750
751
752static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
753 bool force)
754{
755 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
756 u32 new_val = (cmdcfg & mask) | set;
757 u32 cmdcfg_sr;
758
759 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
760 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
761 else
762 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
763
764 bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
765 udelay(2);
766
767 if (new_val != cmdcfg || force)
768 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
769
770 bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
771 udelay(2);
772}
773
774static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
775{
776 u32 tmp;
777
778 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
779 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
780 tmp = (addr[4] << 8) | addr[5];
781 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
782}
783
784static void bgmac_set_rx_mode(struct net_device *net_dev)
785{
786 struct bgmac *bgmac = netdev_priv(net_dev);
787
788 if (net_dev->flags & IFF_PROMISC)
789 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
790 else
791 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
792}
793
794#if 0
795static void bgmac_chip_stats_update(struct bgmac *bgmac)
796{
797 int i;
798
799 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
800 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
801 bgmac->mib_tx_regs[i] =
802 bgmac_read(bgmac,
803 BGMAC_TX_GOOD_OCTETS + (i * 4));
804 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
805 bgmac->mib_rx_regs[i] =
806 bgmac_read(bgmac,
807 BGMAC_RX_GOOD_OCTETS + (i * 4));
808 }
809
810
811}
812#endif
813
814static void bgmac_clear_mib(struct bgmac *bgmac)
815{
816 int i;
817
818 if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
819 return;
820
821 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
822 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
823 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
824 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
825 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
826}
827
828
829static void bgmac_mac_speed(struct bgmac *bgmac)
830{
831 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
832 u32 set = 0;
833
834 switch (bgmac->mac_speed) {
835 case SPEED_10:
836 set |= BGMAC_CMDCFG_ES_10;
837 break;
838 case SPEED_100:
839 set |= BGMAC_CMDCFG_ES_100;
840 break;
841 case SPEED_1000:
842 set |= BGMAC_CMDCFG_ES_1000;
843 break;
844 case SPEED_2500:
845 set |= BGMAC_CMDCFG_ES_2500;
846 break;
847 default:
848 dev_err(bgmac->dev, "Unsupported speed: %d\n",
849 bgmac->mac_speed);
850 }
851
852 if (bgmac->mac_duplex == DUPLEX_HALF)
853 set |= BGMAC_CMDCFG_HD;
854
855 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
856}
857
858static void bgmac_miiconfig(struct bgmac *bgmac)
859{
860 if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
861 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
862 bgmac_idm_write(bgmac, BCMA_IOCTL,
863 bgmac_idm_read(bgmac, BCMA_IOCTL) |
864 0x40 | BGMAC_BCMA_IOCTL_SW_CLKEN);
865 }
866 bgmac->mac_speed = SPEED_2500;
867 bgmac->mac_duplex = DUPLEX_FULL;
868 bgmac_mac_speed(bgmac);
869 } else {
870 u8 imode;
871
872 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
873 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
874 if (imode == 0 || imode == 1) {
875 bgmac->mac_speed = SPEED_100;
876 bgmac->mac_duplex = DUPLEX_FULL;
877 bgmac_mac_speed(bgmac);
878 }
879 }
880}
881
882static void bgmac_chip_reset_idm_config(struct bgmac *bgmac)
883{
884 u32 iost;
885
886 iost = bgmac_idm_read(bgmac, BCMA_IOST);
887 if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
888 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
889
890
891 if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
892 u32 flags = 0;
893
894 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
895 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
896 if (!bgmac->has_robosw)
897 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
898 }
899 bgmac_clk_enable(bgmac, flags);
900 }
901
902 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
903 bgmac_idm_write(bgmac, BCMA_IOCTL,
904 bgmac_idm_read(bgmac, BCMA_IOCTL) &
905 ~BGMAC_BCMA_IOCTL_SW_RESET);
906}
907
908
909static void bgmac_chip_reset(struct bgmac *bgmac)
910{
911 u32 cmdcfg_sr;
912 int i;
913
914 if (bgmac_clk_enabled(bgmac)) {
915 if (!bgmac->stats_grabbed) {
916
917 bgmac->stats_grabbed = true;
918 }
919
920 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
921 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
922
923 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
924 udelay(1);
925
926 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
927 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
928
929
930 }
931
932 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK))
933 bgmac_chip_reset_idm_config(bgmac);
934
935
936 if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
937 bgmac_set(bgmac, BCMA_CLKCTLST,
938 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
939 bgmac_wait_value(bgmac, BCMA_CLKCTLST,
940 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
941 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
942 1000);
943 }
944
945 if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
946 u8 et_swtype = 0;
947 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
948 BGMAC_CHIPCTL_1_IF_TYPE_MII;
949 char buf[4];
950
951 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
952 if (kstrtou8(buf, 0, &et_swtype))
953 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
954 buf);
955 et_swtype &= 0x0f;
956 et_swtype <<= 4;
957 sw_type = et_swtype;
958 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
959 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII |
960 BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
961 } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
962 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
963 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
964 }
965 bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
966 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
967 sw_type);
968 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) {
969 u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII |
970 BGMAC_CHIPCTL_4_SW_TYPE_EPHY;
971 u8 et_swtype = 0;
972 char buf[4];
973
974 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
975 if (kstrtou8(buf, 0, &et_swtype))
976 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
977 buf);
978 sw_type = (et_swtype & 0x0f) << 12;
979 } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) {
980 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII |
981 BGMAC_CHIPCTL_4_SW_TYPE_RGMII;
982 }
983 bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK |
984 BGMAC_CHIPCTL_4_SW_TYPE_MASK),
985 sw_type);
986 } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) {
987 bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK,
988 BGMAC_CHIPCTL_7_IF_TYPE_RGMII);
989 }
990
991
992
993
994
995
996 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
997 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
998 else
999 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
1000
1001 bgmac_cmdcfg_maskset(bgmac,
1002 ~(BGMAC_CMDCFG_TE |
1003 BGMAC_CMDCFG_RE |
1004 BGMAC_CMDCFG_RPI |
1005 BGMAC_CMDCFG_TAI |
1006 BGMAC_CMDCFG_HD |
1007 BGMAC_CMDCFG_ML |
1008 BGMAC_CMDCFG_CFE |
1009 BGMAC_CMDCFG_RL |
1010 BGMAC_CMDCFG_RED |
1011 BGMAC_CMDCFG_PE |
1012 BGMAC_CMDCFG_TPI |
1013 BGMAC_CMDCFG_PAD_EN |
1014 BGMAC_CMDCFG_PF),
1015 BGMAC_CMDCFG_PROM |
1016 BGMAC_CMDCFG_NLC |
1017 BGMAC_CMDCFG_CFE |
1018 cmdcfg_sr,
1019 false);
1020 bgmac->mac_speed = SPEED_UNKNOWN;
1021 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1022
1023 bgmac_clear_mib(bgmac);
1024 if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
1025 bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0,
1026 BCMA_GMAC_CMN_PC_MTE);
1027 else
1028 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1029 bgmac_miiconfig(bgmac);
1030 if (bgmac->mii_bus)
1031 bgmac->mii_bus->reset(bgmac->mii_bus);
1032
1033 netdev_reset_queue(bgmac->net_dev);
1034}
1035
1036static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1037{
1038 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1039}
1040
1041static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1042{
1043 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1044 bgmac_read(bgmac, BGMAC_INT_MASK);
1045}
1046
1047
1048static void bgmac_enable(struct bgmac *bgmac)
1049{
1050 u32 cmdcfg_sr;
1051 u32 cmdcfg;
1052 u32 mode;
1053
1054 if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
1055 cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
1056 else
1057 cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
1058
1059 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1060 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1061 cmdcfg_sr, true);
1062 udelay(2);
1063 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1064 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1065
1066 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1067 BGMAC_DS_MM_SHIFT;
1068 if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
1069 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1070 if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2)
1071 bgmac_cco_ctl_maskset(bgmac, 1, ~0,
1072 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1073
1074 if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
1075 BGMAC_FEAT_FLW_CTRL2)) {
1076 u32 fl_ctl;
1077
1078 if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
1079 fl_ctl = 0x2300e1;
1080 else
1081 fl_ctl = 0x03cb04cb;
1082
1083 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1084 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1085 }
1086
1087 if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
1088 u32 rxq_ctl;
1089 u16 bp_clk;
1090 u8 mdp;
1091
1092 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1093 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1094 bp_clk = bgmac_get_bus_clock(bgmac) / 1000000;
1095 mdp = (bp_clk * 128 / 1000) - 3;
1096 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1097 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1098 }
1099}
1100
1101
1102static void bgmac_chip_init(struct bgmac *bgmac)
1103{
1104
1105 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1106
1107
1108 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1109
1110
1111 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1112
1113 bgmac_set_rx_mode(bgmac->net_dev);
1114
1115 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1116
1117 if (bgmac->loopback)
1118 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1119 else
1120 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1121
1122 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1123
1124 bgmac_chip_intrs_on(bgmac);
1125
1126 bgmac_enable(bgmac);
1127}
1128
1129static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1130{
1131 struct bgmac *bgmac = netdev_priv(dev_id);
1132
1133 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1134 int_status &= bgmac->int_mask;
1135
1136 if (!int_status)
1137 return IRQ_NONE;
1138
1139 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1140 if (int_status)
1141 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
1142
1143
1144 bgmac_chip_intrs_off(bgmac);
1145
1146 napi_schedule(&bgmac->napi);
1147
1148 return IRQ_HANDLED;
1149}
1150
1151static int bgmac_poll(struct napi_struct *napi, int weight)
1152{
1153 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1154 int handled = 0;
1155
1156
1157 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1158
1159 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1160 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1161
1162
1163 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1164 return weight;
1165
1166 if (handled < weight) {
1167 napi_complete_done(napi, handled);
1168 bgmac_chip_intrs_on(bgmac);
1169 }
1170
1171 return handled;
1172}
1173
1174
1175
1176
1177
1178static int bgmac_open(struct net_device *net_dev)
1179{
1180 struct bgmac *bgmac = netdev_priv(net_dev);
1181 int err = 0;
1182
1183 bgmac_chip_reset(bgmac);
1184
1185 err = bgmac_dma_init(bgmac);
1186 if (err)
1187 return err;
1188
1189
1190 bgmac_chip_init(bgmac);
1191
1192 err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED,
1193 KBUILD_MODNAME, net_dev);
1194 if (err < 0) {
1195 dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
1196 bgmac_dma_cleanup(bgmac);
1197 return err;
1198 }
1199 napi_enable(&bgmac->napi);
1200
1201 phy_start(net_dev->phydev);
1202
1203 netif_start_queue(net_dev);
1204
1205 return 0;
1206}
1207
1208static int bgmac_stop(struct net_device *net_dev)
1209{
1210 struct bgmac *bgmac = netdev_priv(net_dev);
1211
1212 netif_carrier_off(net_dev);
1213
1214 phy_stop(net_dev->phydev);
1215
1216 napi_disable(&bgmac->napi);
1217 bgmac_chip_intrs_off(bgmac);
1218 free_irq(bgmac->irq, net_dev);
1219
1220 bgmac_chip_reset(bgmac);
1221 bgmac_dma_cleanup(bgmac);
1222
1223 return 0;
1224}
1225
1226static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1227 struct net_device *net_dev)
1228{
1229 struct bgmac *bgmac = netdev_priv(net_dev);
1230 struct bgmac_dma_ring *ring;
1231
1232
1233 ring = &bgmac->tx_ring[0];
1234 return bgmac_dma_tx_add(bgmac, ring, skb);
1235}
1236
1237static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1238{
1239 struct bgmac *bgmac = netdev_priv(net_dev);
1240 struct sockaddr *sa = addr;
1241 int ret;
1242
1243 ret = eth_prepare_mac_addr_change(net_dev, addr);
1244 if (ret < 0)
1245 return ret;
1246
1247 ether_addr_copy(net_dev->dev_addr, sa->sa_data);
1248 bgmac_write_mac_address(bgmac, net_dev->dev_addr);
1249
1250 eth_commit_mac_addr_change(net_dev, addr);
1251 return 0;
1252}
1253
1254static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1255{
1256 if (!netif_running(net_dev))
1257 return -EINVAL;
1258
1259 return phy_mii_ioctl(net_dev->phydev, ifr, cmd);
1260}
1261
1262static const struct net_device_ops bgmac_netdev_ops = {
1263 .ndo_open = bgmac_open,
1264 .ndo_stop = bgmac_stop,
1265 .ndo_start_xmit = bgmac_start_xmit,
1266 .ndo_set_rx_mode = bgmac_set_rx_mode,
1267 .ndo_set_mac_address = bgmac_set_mac_address,
1268 .ndo_validate_addr = eth_validate_addr,
1269 .ndo_do_ioctl = bgmac_ioctl,
1270};
1271
1272
1273
1274
1275
1276struct bgmac_stat {
1277 u8 size;
1278 u32 offset;
1279 const char *name;
1280};
1281
1282static struct bgmac_stat bgmac_get_strings_stats[] = {
1283 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
1284 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
1285 { 8, BGMAC_TX_OCTETS, "tx_octets" },
1286 { 4, BGMAC_TX_PKTS, "tx_pkts" },
1287 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
1288 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
1289 { 4, BGMAC_TX_LEN_64, "tx_64" },
1290 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
1291 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
1292 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
1293 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
1294 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
1295 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
1296 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
1297 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
1298 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
1299 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
1300 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
1301 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
1302 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
1303 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
1304 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
1305 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
1306 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
1307 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
1308 { 4, BGMAC_TX_DEFERED, "tx_defered" },
1309 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
1310 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
1311 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
1312 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
1313 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
1314 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
1315 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
1316 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
1317 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
1318 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
1319 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
1320 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
1321 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
1322 { 8, BGMAC_RX_OCTETS, "rx_octets" },
1323 { 4, BGMAC_RX_PKTS, "rx_pkts" },
1324 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
1325 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
1326 { 4, BGMAC_RX_LEN_64, "rx_64" },
1327 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
1328 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
1329 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
1330 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
1331 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
1332 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
1333 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
1334 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
1335 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
1336 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
1337 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
1338 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
1339 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
1340 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
1341 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
1342 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
1343 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
1344 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
1345 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
1346 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
1347 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
1348 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
1349};
1350
1351#define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
1352
1353static int bgmac_get_sset_count(struct net_device *dev, int string_set)
1354{
1355 switch (string_set) {
1356 case ETH_SS_STATS:
1357 return BGMAC_STATS_LEN;
1358 }
1359
1360 return -EOPNOTSUPP;
1361}
1362
1363static void bgmac_get_strings(struct net_device *dev, u32 stringset,
1364 u8 *data)
1365{
1366 int i;
1367
1368 if (stringset != ETH_SS_STATS)
1369 return;
1370
1371 for (i = 0; i < BGMAC_STATS_LEN; i++)
1372 strlcpy(data + i * ETH_GSTRING_LEN,
1373 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
1374}
1375
1376static void bgmac_get_ethtool_stats(struct net_device *dev,
1377 struct ethtool_stats *ss, uint64_t *data)
1378{
1379 struct bgmac *bgmac = netdev_priv(dev);
1380 const struct bgmac_stat *s;
1381 unsigned int i;
1382 u64 val;
1383
1384 if (!netif_running(dev))
1385 return;
1386
1387 for (i = 0; i < BGMAC_STATS_LEN; i++) {
1388 s = &bgmac_get_strings_stats[i];
1389 val = 0;
1390 if (s->size == 8)
1391 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
1392 val |= bgmac_read(bgmac, s->offset);
1393 data[i] = val;
1394 }
1395}
1396
1397static void bgmac_get_drvinfo(struct net_device *net_dev,
1398 struct ethtool_drvinfo *info)
1399{
1400 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1401 strlcpy(info->bus_info, "AXI", sizeof(info->bus_info));
1402}
1403
1404static const struct ethtool_ops bgmac_ethtool_ops = {
1405 .get_strings = bgmac_get_strings,
1406 .get_sset_count = bgmac_get_sset_count,
1407 .get_ethtool_stats = bgmac_get_ethtool_stats,
1408 .get_drvinfo = bgmac_get_drvinfo,
1409 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1410 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1411};
1412
1413
1414
1415
1416
1417void bgmac_adjust_link(struct net_device *net_dev)
1418{
1419 struct bgmac *bgmac = netdev_priv(net_dev);
1420 struct phy_device *phy_dev = net_dev->phydev;
1421 bool update = false;
1422
1423 if (phy_dev->link) {
1424 if (phy_dev->speed != bgmac->mac_speed) {
1425 bgmac->mac_speed = phy_dev->speed;
1426 update = true;
1427 }
1428
1429 if (phy_dev->duplex != bgmac->mac_duplex) {
1430 bgmac->mac_duplex = phy_dev->duplex;
1431 update = true;
1432 }
1433 }
1434
1435 if (update) {
1436 bgmac_mac_speed(bgmac);
1437 phy_print_status(phy_dev);
1438 }
1439}
1440EXPORT_SYMBOL_GPL(bgmac_adjust_link);
1441
1442int bgmac_phy_connect_direct(struct bgmac *bgmac)
1443{
1444 struct fixed_phy_status fphy_status = {
1445 .link = 1,
1446 .speed = SPEED_1000,
1447 .duplex = DUPLEX_FULL,
1448 };
1449 struct phy_device *phy_dev;
1450 int err;
1451
1452 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
1453 if (!phy_dev || IS_ERR(phy_dev)) {
1454 dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
1455 return -ENODEV;
1456 }
1457
1458 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1459 PHY_INTERFACE_MODE_MII);
1460 if (err) {
1461 dev_err(bgmac->dev, "Connecting PHY failed\n");
1462 return err;
1463 }
1464
1465 return err;
1466}
1467EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct);
1468
1469struct bgmac *bgmac_alloc(struct device *dev)
1470{
1471 struct net_device *net_dev;
1472 struct bgmac *bgmac;
1473
1474
1475 net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac));
1476 if (!net_dev)
1477 return NULL;
1478
1479 net_dev->netdev_ops = &bgmac_netdev_ops;
1480 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1481
1482 bgmac = netdev_priv(net_dev);
1483 bgmac->dev = dev;
1484 bgmac->net_dev = net_dev;
1485
1486 return bgmac;
1487}
1488EXPORT_SYMBOL_GPL(bgmac_alloc);
1489
1490int bgmac_enet_probe(struct bgmac *bgmac)
1491{
1492 struct net_device *net_dev = bgmac->net_dev;
1493 int err;
1494
1495 net_dev->irq = bgmac->irq;
1496 SET_NETDEV_DEV(net_dev, bgmac->dev);
1497 dev_set_drvdata(bgmac->dev, bgmac);
1498
1499 if (!is_valid_ether_addr(net_dev->dev_addr)) {
1500 dev_err(bgmac->dev, "Invalid MAC addr: %pM\n",
1501 net_dev->dev_addr);
1502 eth_hw_addr_random(net_dev);
1503 dev_warn(bgmac->dev, "Using random MAC: %pM\n",
1504 net_dev->dev_addr);
1505 }
1506
1507
1508
1509
1510 bgmac_clk_enable(bgmac, 0);
1511
1512
1513 if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
1514 if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
1515 bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86);
1516 }
1517
1518 bgmac_chip_reset(bgmac);
1519
1520 err = bgmac_dma_alloc(bgmac);
1521 if (err) {
1522 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
1523 goto err_out;
1524 }
1525
1526 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1527 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1528 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1529
1530 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1531
1532 err = bgmac_phy_connect(bgmac);
1533 if (err) {
1534 dev_err(bgmac->dev, "Cannot connect to phy\n");
1535 goto err_dma_free;
1536 }
1537
1538 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1539 net_dev->hw_features = net_dev->features;
1540 net_dev->vlan_features = net_dev->features;
1541
1542 err = register_netdev(bgmac->net_dev);
1543 if (err) {
1544 dev_err(bgmac->dev, "Cannot register net device\n");
1545 goto err_phy_disconnect;
1546 }
1547
1548 netif_carrier_off(net_dev);
1549
1550 return 0;
1551
1552err_phy_disconnect:
1553 phy_disconnect(net_dev->phydev);
1554err_dma_free:
1555 bgmac_dma_free(bgmac);
1556err_out:
1557
1558 return err;
1559}
1560EXPORT_SYMBOL_GPL(bgmac_enet_probe);
1561
1562void bgmac_enet_remove(struct bgmac *bgmac)
1563{
1564 unregister_netdev(bgmac->net_dev);
1565 phy_disconnect(bgmac->net_dev->phydev);
1566 netif_napi_del(&bgmac->napi);
1567 bgmac_dma_free(bgmac);
1568 free_netdev(bgmac->net_dev);
1569}
1570EXPORT_SYMBOL_GPL(bgmac_enet_remove);
1571
1572int bgmac_enet_suspend(struct bgmac *bgmac)
1573{
1574 if (!netif_running(bgmac->net_dev))
1575 return 0;
1576
1577 phy_stop(bgmac->net_dev->phydev);
1578
1579 netif_stop_queue(bgmac->net_dev);
1580
1581 napi_disable(&bgmac->napi);
1582
1583 netif_tx_lock(bgmac->net_dev);
1584 netif_device_detach(bgmac->net_dev);
1585 netif_tx_unlock(bgmac->net_dev);
1586
1587 bgmac_chip_intrs_off(bgmac);
1588 bgmac_chip_reset(bgmac);
1589 bgmac_dma_cleanup(bgmac);
1590
1591 return 0;
1592}
1593EXPORT_SYMBOL_GPL(bgmac_enet_suspend);
1594
1595int bgmac_enet_resume(struct bgmac *bgmac)
1596{
1597 int rc;
1598
1599 if (!netif_running(bgmac->net_dev))
1600 return 0;
1601
1602 rc = bgmac_dma_init(bgmac);
1603 if (rc)
1604 return rc;
1605
1606 bgmac_chip_init(bgmac);
1607
1608 napi_enable(&bgmac->napi);
1609
1610 netif_tx_lock(bgmac->net_dev);
1611 netif_device_attach(bgmac->net_dev);
1612 netif_tx_unlock(bgmac->net_dev);
1613
1614 netif_start_queue(bgmac->net_dev);
1615
1616 phy_start(bgmac->net_dev->phydev);
1617
1618 return 0;
1619}
1620EXPORT_SYMBOL_GPL(bgmac_enet_resume);
1621
1622MODULE_AUTHOR("Rafał Miłecki");
1623MODULE_LICENSE("GPL");
1624
