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35#ifndef __T4_HW_H
36#define __T4_HW_H
37
38#include <linux/types.h>
39
40enum {
41 NCHAN = 4,
42 MAX_MTU = 9600,
43 EEPROMSIZE = 17408,
44 EEPROMVSIZE = 32768,
45 EEPROMPFSIZE = 1024,
46 RSS_NENTRIES = 2048,
47 T6_RSS_NENTRIES = 4096,
48 TCB_SIZE = 128,
49 NMTUS = 16,
50 NCCTRL_WIN = 32,
51 NTX_SCHED = 8,
52 PM_NSTATS = 5,
53 T6_PM_NSTATS = 7,
54 MBOX_LEN = 64,
55 TRACE_LEN = 112,
56 FILTER_OPT_LEN = 36,
57};
58
59enum {
60 CIM_NUM_IBQ = 6,
61 CIM_NUM_OBQ = 6,
62 CIM_NUM_OBQ_T5 = 8,
63 CIMLA_SIZE = 2048,
64 CIM_PIFLA_SIZE = 64,
65 CIM_MALA_SIZE = 64,
66 CIM_IBQ_SIZE = 128,
67 CIM_OBQ_SIZE = 128,
68 TPLA_SIZE = 128,
69 ULPRX_LA_SIZE = 512,
70};
71
72
73enum ctxt_type {
74 CTXT_EGRESS,
75 CTXT_INGRESS,
76 CTXT_FLM,
77 CTXT_CNM,
78};
79
80enum {
81 SF_PAGE_SIZE = 256,
82 SF_SEC_SIZE = 64 * 1024,
83};
84
85enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR };
86
87enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV };
88
89enum {
90 SGE_MAX_WR_LEN = 512,
91 SGE_CTXT_SIZE = 24,
92 SGE_NTIMERS = 6,
93 SGE_NCOUNTERS = 4,
94 SGE_MAX_IQ_SIZE = 65520,
95
96 SGE_TIMER_RSTRT_CNTR = 6,
97 SGE_TIMER_UPD_CIDX = 7,
98
99 SGE_EQ_IDXSIZE = 64,
100
101 SGE_INTRDST_PCI = 0,
102 SGE_INTRDST_IQ = 1,
103
104 SGE_UPDATEDEL_NONE = 0,
105 SGE_UPDATEDEL_INTR = 1,
106 SGE_UPDATEDEL_STPG = 2,
107 SGE_UPDATEDEL_BOTH = 3,
108
109 SGE_HOSTFCMODE_NONE = 0,
110 SGE_HOSTFCMODE_IQ = 1,
111 SGE_HOSTFCMODE_STPG = 2,
112 SGE_HOSTFCMODE_BOTH = 3,
113
114 SGE_FETCHBURSTMIN_16B = 0,
115 SGE_FETCHBURSTMIN_32B = 1,
116 SGE_FETCHBURSTMIN_64B = 2,
117 SGE_FETCHBURSTMIN_128B = 3,
118
119 SGE_FETCHBURSTMAX_64B = 0,
120 SGE_FETCHBURSTMAX_128B = 1,
121 SGE_FETCHBURSTMAX_256B = 2,
122 SGE_FETCHBURSTMAX_512B = 3,
123
124 SGE_CIDXFLUSHTHRESH_1 = 0,
125 SGE_CIDXFLUSHTHRESH_2 = 1,
126 SGE_CIDXFLUSHTHRESH_4 = 2,
127 SGE_CIDXFLUSHTHRESH_8 = 3,
128 SGE_CIDXFLUSHTHRESH_16 = 4,
129 SGE_CIDXFLUSHTHRESH_32 = 5,
130 SGE_CIDXFLUSHTHRESH_64 = 6,
131 SGE_CIDXFLUSHTHRESH_128 = 7,
132
133 SGE_INGPADBOUNDARY_SHIFT = 5,
134};
135
136
137enum pcie_memwin {
138 MEMWIN_NIC = 0,
139 MEMWIN_RSVD1 = 1,
140 MEMWIN_RSVD2 = 2,
141 MEMWIN_RDMA = 3,
142 MEMWIN_RSVD4 = 4,
143 MEMWIN_FOISCSI = 5,
144 MEMWIN_CSIOSTOR = 6,
145 MEMWIN_RSVD7 = 7,
146};
147
148struct sge_qstat {
149 __be32 qid;
150 __be16 cidx;
151 __be16 pidx;
152};
153
154
155
156
157struct rsp_ctrl {
158 __be32 hdrbuflen_pidx;
159 __be32 pldbuflen_qid;
160 union {
161 u8 type_gen;
162 __be64 last_flit;
163 };
164};
165
166#define RSPD_NEWBUF_S 31
167#define RSPD_NEWBUF_V(x) ((x) << RSPD_NEWBUF_S)
168#define RSPD_NEWBUF_F RSPD_NEWBUF_V(1U)
169
170#define RSPD_LEN_S 0
171#define RSPD_LEN_M 0x7fffffff
172#define RSPD_LEN_G(x) (((x) >> RSPD_LEN_S) & RSPD_LEN_M)
173
174#define RSPD_QID_S RSPD_LEN_S
175#define RSPD_QID_M RSPD_LEN_M
176#define RSPD_QID_G(x) RSPD_LEN_G(x)
177
178#define RSPD_GEN_S 7
179
180#define RSPD_TYPE_S 4
181#define RSPD_TYPE_M 0x3
182#define RSPD_TYPE_G(x) (((x) >> RSPD_TYPE_S) & RSPD_TYPE_M)
183
184
185#define QINTR_CNT_EN_S 0
186#define QINTR_CNT_EN_V(x) ((x) << QINTR_CNT_EN_S)
187#define QINTR_CNT_EN_F QINTR_CNT_EN_V(1U)
188
189#define QINTR_TIMER_IDX_S 1
190#define QINTR_TIMER_IDX_M 0x7
191#define QINTR_TIMER_IDX_V(x) ((x) << QINTR_TIMER_IDX_S)
192#define QINTR_TIMER_IDX_G(x) (((x) >> QINTR_TIMER_IDX_S) & QINTR_TIMER_IDX_M)
193
194
195
196
197#define FLASH_START(start) ((start) * SF_SEC_SIZE)
198#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
199
200enum {
201
202
203
204 FLASH_EXP_ROM_START_SEC = 0,
205 FLASH_EXP_ROM_NSECS = 6,
206 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
207 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
208
209
210
211
212
213 FLASH_IBFT_START_SEC = 6,
214 FLASH_IBFT_NSECS = 1,
215 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
216 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
217
218
219
220
221 FLASH_BOOTCFG_START_SEC = 7,
222 FLASH_BOOTCFG_NSECS = 1,
223 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
224 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
225
226
227
228
229 FLASH_FW_START_SEC = 8,
230 FLASH_FW_NSECS = 16,
231 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
232 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
233
234
235
236 FLASH_FWBOOTSTRAP_START_SEC = 27,
237 FLASH_FWBOOTSTRAP_NSECS = 1,
238 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
239 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
240
241
242
243
244 FLASH_ISCSI_CRASH_START_SEC = 29,
245 FLASH_ISCSI_CRASH_NSECS = 1,
246 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
247 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
248
249
250
251
252 FLASH_FCOE_CRASH_START_SEC = 30,
253 FLASH_FCOE_CRASH_NSECS = 1,
254 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
255 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
256
257
258
259
260
261
262
263 FLASH_CFG_START_SEC = 31,
264 FLASH_CFG_NSECS = 1,
265 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
266 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
267
268
269
270
271
272 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
273
274 FLASH_FPGA_CFG_START_SEC = 15,
275 FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
276
277
278
279
280};
281
282#undef FLASH_START
283#undef FLASH_MAX_SIZE
284
285#define SGE_TIMESTAMP_S 0
286#define SGE_TIMESTAMP_M 0xfffffffffffffffULL
287#define SGE_TIMESTAMP_V(x) ((__u64)(x) << SGE_TIMESTAMP_S)
288#define SGE_TIMESTAMP_G(x) (((__u64)(x) >> SGE_TIMESTAMP_S) & SGE_TIMESTAMP_M)
289
290#define I2C_DEV_ADDR_A0 0xa0
291#define I2C_DEV_ADDR_A2 0xa2
292#define I2C_PAGE_SIZE 0x100
293#define SFP_DIAG_TYPE_ADDR 0x5c
294#define SFP_DIAG_TYPE_LEN 0x1
295#define SFF_8472_COMP_ADDR 0x5e
296#define SFF_8472_COMP_LEN 0x1
297#define SFF_REV_ADDR 0x1
298#define SFF_REV_LEN 0x1
299
300#endif
301