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36#include <linux/pci.h>
37
38#include "t4vf_common.h"
39#include "t4vf_defs.h"
40
41#include "../cxgb4/t4_regs.h"
42#include "../cxgb4/t4_values.h"
43#include "../cxgb4/t4fw_api.h"
44
45
46
47
48
49
50int t4vf_wait_dev_ready(struct adapter *adapter)
51{
52 const u32 whoami = T4VF_PL_BASE_ADDR + PL_VF_WHOAMI;
53 const u32 notready1 = 0xffffffff;
54 const u32 notready2 = 0xeeeeeeee;
55 u32 val;
56
57 val = t4_read_reg(adapter, whoami);
58 if (val != notready1 && val != notready2)
59 return 0;
60 msleep(500);
61 val = t4_read_reg(adapter, whoami);
62 if (val != notready1 && val != notready2)
63 return 0;
64 else
65 return -EIO;
66}
67
68
69
70
71
72static void get_mbox_rpl(struct adapter *adapter, __be64 *rpl, int size,
73 u32 mbox_data)
74{
75 for ( ; size; size -= 8, mbox_data += 8)
76 *rpl++ = cpu_to_be64(t4_read_reg64(adapter, mbox_data));
77}
78
79
80
81
82
83
84
85
86
87static void t4vf_record_mbox(struct adapter *adapter, const __be64 *cmd,
88 int size, int access, int execute)
89{
90 struct mbox_cmd_log *log = adapter->mbox_log;
91 struct mbox_cmd *entry;
92 int i;
93
94 entry = mbox_cmd_log_entry(log, log->cursor++);
95 if (log->cursor == log->size)
96 log->cursor = 0;
97
98 for (i = 0; i < size / 8; i++)
99 entry->cmd[i] = be64_to_cpu(cmd[i]);
100 while (i < MBOX_LEN / 8)
101 entry->cmd[i++] = 0;
102 entry->timestamp = jiffies;
103 entry->seqno = log->seqno++;
104 entry->access = access;
105 entry->execute = execute;
106}
107
108
109
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115
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118
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126
127
128int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
129 void *rpl, bool sleep_ok)
130{
131 static const int delay[] = {
132 1, 1, 3, 5, 10, 10, 20, 50, 100
133 };
134
135 u16 access = 0, execute = 0;
136 u32 v, mbox_data;
137 int i, ms, delay_idx, ret;
138 const __be64 *p;
139 u32 mbox_ctl = T4VF_CIM_BASE_ADDR + CIM_VF_EXT_MAILBOX_CTRL;
140 u32 cmd_op = FW_CMD_OP_G(be32_to_cpu(((struct fw_cmd_hdr *)cmd)->hi));
141 __be64 cmd_rpl[MBOX_LEN / 8];
142 struct mbox_list entry;
143
144
145
146
147 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
148 mbox_data = T4VF_MBDATA_BASE_ADDR;
149 else
150 mbox_data = T6VF_MBDATA_BASE_ADDR;
151
152
153
154
155
156 if ((size % 16) != 0 ||
157 size > NUM_CIM_VF_MAILBOX_DATA_INSTANCES * 4)
158 return -EINVAL;
159
160
161
162
163
164
165 spin_lock(&adapter->mbox_lock);
166 list_add_tail(&entry.list, &adapter->mlist.list);
167 spin_unlock(&adapter->mbox_lock);
168
169 delay_idx = 0;
170 ms = delay[0];
171
172 for (i = 0; ; i += ms) {
173
174
175
176
177
178 if (i > FW_CMD_MAX_TIMEOUT) {
179 spin_lock(&adapter->mbox_lock);
180 list_del(&entry.list);
181 spin_unlock(&adapter->mbox_lock);
182 ret = -EBUSY;
183 t4vf_record_mbox(adapter, cmd, size, access, ret);
184 return ret;
185 }
186
187
188
189
190 if (list_first_entry(&adapter->mlist.list, struct mbox_list,
191 list) == &entry)
192 break;
193
194
195 if (sleep_ok) {
196 ms = delay[delay_idx];
197 if (delay_idx < ARRAY_SIZE(delay) - 1)
198 delay_idx++;
199 msleep(ms);
200 } else {
201 mdelay(ms);
202 }
203 }
204
205
206
207
208
209 v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
210 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
211 v = MBOWNER_G(t4_read_reg(adapter, mbox_ctl));
212 if (v != MBOX_OWNER_DRV) {
213 spin_lock(&adapter->mbox_lock);
214 list_del(&entry.list);
215 spin_unlock(&adapter->mbox_lock);
216 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
217 t4vf_record_mbox(adapter, cmd, size, access, ret);
218 return ret;
219 }
220
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231
232
233
234 if (cmd_op != FW_VI_STATS_CMD)
235 t4vf_record_mbox(adapter, cmd, size, access, 0);
236 for (i = 0, p = cmd; i < size; i += 8)
237 t4_write_reg64(adapter, mbox_data + i, be64_to_cpu(*p++));
238 t4_read_reg(adapter, mbox_data);
239
240 t4_write_reg(adapter, mbox_ctl,
241 MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
242 t4_read_reg(adapter, mbox_ctl);
243
244
245
246
247 delay_idx = 0;
248 ms = delay[0];
249
250 for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
251 if (sleep_ok) {
252 ms = delay[delay_idx];
253 if (delay_idx < ARRAY_SIZE(delay) - 1)
254 delay_idx++;
255 msleep(ms);
256 } else
257 mdelay(ms);
258
259
260
261
262 v = t4_read_reg(adapter, mbox_ctl);
263 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
264
265
266
267
268 if ((v & MBMSGVALID_F) == 0) {
269 t4_write_reg(adapter, mbox_ctl,
270 MBOWNER_V(MBOX_OWNER_NONE));
271 continue;
272 }
273
274
275
276
277
278
279
280
281 get_mbox_rpl(adapter, cmd_rpl, size, mbox_data);
282
283
284 v = be64_to_cpu(cmd_rpl[0]);
285
286 if (rpl) {
287
288 WARN_ON((be32_to_cpu(*(const __be32 *)cmd)
289 & FW_CMD_REQUEST_F) == 0);
290 memcpy(rpl, cmd_rpl, size);
291 WARN_ON((be32_to_cpu(*(__be32 *)rpl)
292 & FW_CMD_REQUEST_F) != 0);
293 }
294 t4_write_reg(adapter, mbox_ctl,
295 MBOWNER_V(MBOX_OWNER_NONE));
296 execute = i + ms;
297 if (cmd_op != FW_VI_STATS_CMD)
298 t4vf_record_mbox(adapter, cmd_rpl, size, access,
299 execute);
300 spin_lock(&adapter->mbox_lock);
301 list_del(&entry.list);
302 spin_unlock(&adapter->mbox_lock);
303 return -FW_CMD_RETVAL_G(v);
304 }
305 }
306
307
308 ret = -ETIMEDOUT;
309 t4vf_record_mbox(adapter, cmd, size, access, ret);
310 spin_lock(&adapter->mbox_lock);
311 list_del(&entry.list);
312 spin_unlock(&adapter->mbox_lock);
313 return ret;
314}
315
316#define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
317 FW_PORT_CAP32_ANEG)
318
319
320
321
322
323
324
325static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
326{
327 fw_port_cap32_t caps32 = 0;
328
329 #define CAP16_TO_CAP32(__cap) \
330 do { \
331 if (caps16 & FW_PORT_CAP_##__cap) \
332 caps32 |= FW_PORT_CAP32_##__cap; \
333 } while (0)
334
335 CAP16_TO_CAP32(SPEED_100M);
336 CAP16_TO_CAP32(SPEED_1G);
337 CAP16_TO_CAP32(SPEED_25G);
338 CAP16_TO_CAP32(SPEED_10G);
339 CAP16_TO_CAP32(SPEED_40G);
340 CAP16_TO_CAP32(SPEED_100G);
341 CAP16_TO_CAP32(FC_RX);
342 CAP16_TO_CAP32(FC_TX);
343 CAP16_TO_CAP32(ANEG);
344 CAP16_TO_CAP32(MDIX);
345 CAP16_TO_CAP32(MDIAUTO);
346 CAP16_TO_CAP32(FEC_RS);
347 CAP16_TO_CAP32(FEC_BASER_RS);
348 CAP16_TO_CAP32(802_3_PAUSE);
349 CAP16_TO_CAP32(802_3_ASM_DIR);
350
351 #undef CAP16_TO_CAP32
352
353 return caps32;
354}
355
356
357static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
358{
359 enum cc_pause cc_pause = 0;
360
361 if (fw_pause & FW_PORT_CAP32_FC_RX)
362 cc_pause |= PAUSE_RX;
363 if (fw_pause & FW_PORT_CAP32_FC_TX)
364 cc_pause |= PAUSE_TX;
365
366 return cc_pause;
367}
368
369
370static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
371{
372 enum cc_fec cc_fec = 0;
373
374 if (fw_fec & FW_PORT_CAP32_FEC_RS)
375 cc_fec |= FEC_RS;
376 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
377 cc_fec |= FEC_BASER_RS;
378
379 return cc_fec;
380}
381
382
383
384
385static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
386{
387 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
388 do { \
389 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
390 return __speed; \
391 } while (0)
392
393 TEST_SPEED_RETURN(400G, 400000);
394 TEST_SPEED_RETURN(200G, 200000);
395 TEST_SPEED_RETURN(100G, 100000);
396 TEST_SPEED_RETURN(50G, 50000);
397 TEST_SPEED_RETURN(40G, 40000);
398 TEST_SPEED_RETURN(25G, 25000);
399 TEST_SPEED_RETURN(10G, 10000);
400 TEST_SPEED_RETURN(1G, 1000);
401 TEST_SPEED_RETURN(100M, 100);
402
403 #undef TEST_SPEED_RETURN
404
405 return 0;
406}
407
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415
416
417static void init_link_config(struct link_config *lc,
418 fw_port_cap32_t pcaps,
419 fw_port_cap32_t acaps)
420{
421 lc->pcaps = pcaps;
422 lc->lpacaps = 0;
423 lc->speed_caps = 0;
424 lc->speed = 0;
425 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
426
427
428
429
430 lc->auto_fec = fwcap_to_cc_fec(acaps);
431 lc->requested_fec = FEC_AUTO;
432 lc->fec = lc->auto_fec;
433
434 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
435 lc->acaps = acaps & ADVERT_MASK;
436 lc->autoneg = AUTONEG_ENABLE;
437 lc->requested_fc |= PAUSE_AUTONEG;
438 } else {
439 lc->acaps = 0;
440 lc->autoneg = AUTONEG_DISABLE;
441 }
442}
443
444
445
446
447
448
449int t4vf_port_init(struct adapter *adapter, int pidx)
450{
451 struct port_info *pi = adap2pinfo(adapter, pidx);
452 unsigned int fw_caps = adapter->params.fw_caps_support;
453 struct fw_vi_cmd vi_cmd, vi_rpl;
454 struct fw_port_cmd port_cmd, port_rpl;
455 enum fw_port_type port_type;
456 int mdio_addr;
457 fw_port_cap32_t pcaps, acaps;
458 int ret;
459
460
461
462
463
464
465
466 if (fw_caps == FW_CAPS_UNKNOWN) {
467 u32 param, val;
468
469 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
470 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
471 val = 1;
472 ret = t4vf_set_params(adapter, 1, ¶m, &val);
473 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
474 adapter->params.fw_caps_support = fw_caps;
475 }
476
477
478
479
480
481 memset(&vi_cmd, 0, sizeof(vi_cmd));
482 vi_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
483 FW_CMD_REQUEST_F |
484 FW_CMD_READ_F);
485 vi_cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(vi_cmd));
486 vi_cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(pi->viid));
487 ret = t4vf_wr_mbox(adapter, &vi_cmd, sizeof(vi_cmd), &vi_rpl);
488 if (ret != FW_SUCCESS)
489 return ret;
490
491 BUG_ON(pi->port_id != FW_VI_CMD_PORTID_G(vi_rpl.portid_pkd));
492 pi->rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(vi_rpl.rsssize_pkd));
493 t4_os_set_hw_addr(adapter, pidx, vi_rpl.mac);
494
495
496
497
498
499 if (!(adapter->params.vfres.r_caps & FW_CMD_CAP_PORT))
500 return 0;
501
502 memset(&port_cmd, 0, sizeof(port_cmd));
503 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
504 FW_CMD_REQUEST_F |
505 FW_CMD_READ_F |
506 FW_PORT_CMD_PORTID_V(pi->port_id));
507 port_cmd.action_to_len16 = cpu_to_be32(
508 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
509 ? FW_PORT_ACTION_GET_PORT_INFO
510 : FW_PORT_ACTION_GET_PORT_INFO32) |
511 FW_LEN16(port_cmd));
512 ret = t4vf_wr_mbox(adapter, &port_cmd, sizeof(port_cmd), &port_rpl);
513 if (ret != FW_SUCCESS)
514 return ret;
515
516
517 if (fw_caps == FW_CAPS16) {
518 u32 lstatus = be32_to_cpu(port_rpl.u.info.lstatus_to_modtype);
519
520 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
521 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
522 ? FW_PORT_CMD_MDIOADDR_G(lstatus)
523 : -1);
524 pcaps = fwcaps16_to_caps32(be16_to_cpu(port_rpl.u.info.pcap));
525 acaps = fwcaps16_to_caps32(be16_to_cpu(port_rpl.u.info.acap));
526 } else {
527 u32 lstatus32 =
528 be32_to_cpu(port_rpl.u.info32.lstatus32_to_cbllen32);
529
530 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
531 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
532 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
533 : -1);
534 pcaps = be32_to_cpu(port_rpl.u.info32.pcaps32);
535 acaps = be32_to_cpu(port_rpl.u.info32.acaps32);
536 }
537
538 pi->port_type = port_type;
539 pi->mdio_addr = mdio_addr;
540 pi->mod_type = FW_PORT_MOD_TYPE_NA;
541
542 init_link_config(&pi->link_cfg, pcaps, acaps);
543 return 0;
544}
545
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552
553
554int t4vf_fw_reset(struct adapter *adapter)
555{
556 struct fw_reset_cmd cmd;
557
558 memset(&cmd, 0, sizeof(cmd));
559 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RESET_CMD) |
560 FW_CMD_WRITE_F);
561 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
562 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
563}
564
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573
574
575static int t4vf_query_params(struct adapter *adapter, unsigned int nparams,
576 const u32 *params, u32 *vals)
577{
578 int i, ret;
579 struct fw_params_cmd cmd, rpl;
580 struct fw_params_param *p;
581 size_t len16;
582
583 if (nparams > 7)
584 return -EINVAL;
585
586 memset(&cmd, 0, sizeof(cmd));
587 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
588 FW_CMD_REQUEST_F |
589 FW_CMD_READ_F);
590 len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
591 param[nparams].mnem), 16);
592 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
593 for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++)
594 p->mnem = htonl(*params++);
595
596 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
597 if (ret == 0)
598 for (i = 0, p = &rpl.param[0]; i < nparams; i++, p++)
599 *vals++ = be32_to_cpu(p->val);
600 return ret;
601}
602
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609
610
611
612
613int t4vf_set_params(struct adapter *adapter, unsigned int nparams,
614 const u32 *params, const u32 *vals)
615{
616 int i;
617 struct fw_params_cmd cmd;
618 struct fw_params_param *p;
619 size_t len16;
620
621 if (nparams > 7)
622 return -EINVAL;
623
624 memset(&cmd, 0, sizeof(cmd));
625 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
626 FW_CMD_REQUEST_F |
627 FW_CMD_WRITE_F);
628 len16 = DIV_ROUND_UP(offsetof(struct fw_params_cmd,
629 param[nparams]), 16);
630 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
631 for (i = 0, p = &cmd.param[0]; i < nparams; i++, p++) {
632 p->mnem = cpu_to_be32(*params++);
633 p->val = cpu_to_be32(*vals++);
634 }
635
636 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
637}
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642
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645
646
647
648
649
650int t4vf_fl_pkt_align(struct adapter *adapter)
651{
652 u32 sge_control, sge_control2;
653 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
654
655 sge_control = adapter->params.sge.sge_control;
656
657
658
659
660
661
662
663
664
665
666
667
668
669 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
670 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
671 else
672 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
673
674 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
675
676 fl_align = ingpadboundary;
677 if (!is_t4(adapter->params.chip)) {
678
679
680
681 sge_control2 = adapter->params.sge.sge_control2;
682 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
683 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
684 ingpackboundary = 16;
685 else
686 ingpackboundary = 1 << (ingpackboundary +
687 INGPACKBOUNDARY_SHIFT_X);
688
689 fl_align = max(ingpadboundary, ingpackboundary);
690 }
691 return fl_align;
692}
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718
719int t4vf_bar2_sge_qregs(struct adapter *adapter,
720 unsigned int qid,
721 enum t4_bar2_qtype qtype,
722 u64 *pbar2_qoffset,
723 unsigned int *pbar2_qid)
724{
725 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
726 u64 bar2_page_offset, bar2_qoffset;
727 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
728
729
730
731 if (is_t4(adapter->params.chip))
732 return -EINVAL;
733
734
735
736 page_shift = adapter->params.sge.sge_vf_hps + 10;
737 page_size = 1 << page_shift;
738
739
740
741 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
742 ? adapter->params.sge.sge_vf_eq_qpp
743 : adapter->params.sge.sge_vf_iq_qpp);
744 qpp_mask = (1 << qpp_shift) - 1;
745
746
747
748
749
750
751 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
752 bar2_qid = qid & qpp_mask;
753 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
754
755
756
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759
760
761
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764
765
766
767
768
769
770
771 bar2_qoffset = bar2_page_offset;
772 bar2_qinferred = (bar2_qid_offset < page_size);
773 if (bar2_qinferred) {
774 bar2_qoffset += bar2_qid_offset;
775 bar2_qid = 0;
776 }
777
778 *pbar2_qoffset = bar2_qoffset;
779 *pbar2_qid = bar2_qid;
780 return 0;
781}
782
783unsigned int t4vf_get_pf_from_vf(struct adapter *adapter)
784{
785 u32 whoami;
786
787 whoami = t4_read_reg(adapter, T4VF_PL_BASE_ADDR + PL_VF_WHOAMI_A);
788 return (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
789 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami));
790}
791
792
793
794
795
796
797
798
799
800int t4vf_get_sge_params(struct adapter *adapter)
801{
802 struct sge_params *sge_params = &adapter->params.sge;
803 u32 params[7], vals[7];
804 int v;
805
806 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
807 FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL_A));
808 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
809 FW_PARAMS_PARAM_XYZ_V(SGE_HOST_PAGE_SIZE_A));
810 params[2] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
811 FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE0_A));
812 params[3] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
813 FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE1_A));
814 params[4] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
815 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1_A));
816 params[5] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
817 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3_A));
818 params[6] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
819 FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5_A));
820 v = t4vf_query_params(adapter, 7, params, vals);
821 if (v)
822 return v;
823 sge_params->sge_control = vals[0];
824 sge_params->sge_host_page_size = vals[1];
825 sge_params->sge_fl_buffer_size[0] = vals[2];
826 sge_params->sge_fl_buffer_size[1] = vals[3];
827 sge_params->sge_timer_value_0_and_1 = vals[4];
828 sge_params->sge_timer_value_2_and_3 = vals[5];
829 sge_params->sge_timer_value_4_and_5 = vals[6];
830
831
832
833
834
835
836
837
838
839
840
841 if (!is_t4(adapter->params.chip)) {
842 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
843 FW_PARAMS_PARAM_XYZ_V(SGE_CONTROL2_A));
844 v = t4vf_query_params(adapter, 1, params, vals);
845 if (v != FW_SUCCESS) {
846 dev_err(adapter->pdev_dev,
847 "Unable to get SGE Control2; "
848 "probably old firmware.\n");
849 return v;
850 }
851 sge_params->sge_control2 = vals[0];
852 }
853
854 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
855 FW_PARAMS_PARAM_XYZ_V(SGE_INGRESS_RX_THRESHOLD_A));
856 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
857 FW_PARAMS_PARAM_XYZ_V(SGE_CONM_CTRL_A));
858 v = t4vf_query_params(adapter, 2, params, vals);
859 if (v)
860 return v;
861 sge_params->sge_ingress_rx_threshold = vals[0];
862 sge_params->sge_congestion_control = vals[1];
863
864
865
866
867
868 if (!is_t4(adapter->params.chip)) {
869 unsigned int pf, s_hps, s_qpp;
870
871 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
872 FW_PARAMS_PARAM_XYZ_V(
873 SGE_EGRESS_QUEUES_PER_PAGE_VF_A));
874 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
875 FW_PARAMS_PARAM_XYZ_V(
876 SGE_INGRESS_QUEUES_PER_PAGE_VF_A));
877 v = t4vf_query_params(adapter, 2, params, vals);
878 if (v != FW_SUCCESS) {
879 dev_warn(adapter->pdev_dev,
880 "Unable to get VF SGE Queues/Page; "
881 "probably old firmware.\n");
882 return v;
883 }
884 sge_params->sge_egress_queues_per_page = vals[0];
885 sge_params->sge_ingress_queues_per_page = vals[1];
886
887
888
889
890
891
892 pf = t4vf_get_pf_from_vf(adapter);
893 s_hps = (HOSTPAGESIZEPF0_S +
894 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * pf);
895 sge_params->sge_vf_hps =
896 ((sge_params->sge_host_page_size >> s_hps)
897 & HOSTPAGESIZEPF0_M);
898
899 s_qpp = (QUEUESPERPAGEPF0_S +
900 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * pf);
901 sge_params->sge_vf_eq_qpp =
902 ((sge_params->sge_egress_queues_per_page >> s_qpp)
903 & QUEUESPERPAGEPF0_M);
904 sge_params->sge_vf_iq_qpp =
905 ((sge_params->sge_ingress_queues_per_page >> s_qpp)
906 & QUEUESPERPAGEPF0_M);
907 }
908
909 return 0;
910}
911
912
913
914
915
916
917
918
919int t4vf_get_vpd_params(struct adapter *adapter)
920{
921 struct vpd_params *vpd_params = &adapter->params.vpd;
922 u32 params[7], vals[7];
923 int v;
924
925 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
926 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
927 v = t4vf_query_params(adapter, 1, params, vals);
928 if (v)
929 return v;
930 vpd_params->cclk = vals[0];
931
932 return 0;
933}
934
935
936
937
938
939
940
941
942int t4vf_get_dev_params(struct adapter *adapter)
943{
944 struct dev_params *dev_params = &adapter->params.dev;
945 u32 params[7], vals[7];
946 int v;
947
948 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
949 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWREV));
950 params[1] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
951 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPREV));
952 v = t4vf_query_params(adapter, 2, params, vals);
953 if (v)
954 return v;
955 dev_params->fwrev = vals[0];
956 dev_params->tprev = vals[1];
957
958 return 0;
959}
960
961
962
963
964
965
966
967
968int t4vf_get_rss_glb_config(struct adapter *adapter)
969{
970 struct rss_params *rss = &adapter->params.rss;
971 struct fw_rss_glb_config_cmd cmd, rpl;
972 int v;
973
974
975
976
977
978 memset(&cmd, 0, sizeof(cmd));
979 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
980 FW_CMD_REQUEST_F |
981 FW_CMD_READ_F);
982 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
983 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
984 if (v)
985 return v;
986
987
988
989
990
991
992
993 rss->mode = FW_RSS_GLB_CONFIG_CMD_MODE_G(
994 be32_to_cpu(rpl.u.manual.mode_pkd));
995 switch (rss->mode) {
996 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
997 u32 word = be32_to_cpu(
998 rpl.u.basicvirtual.synmapen_to_hashtoeplitz);
999
1000 rss->u.basicvirtual.synmapen =
1001 ((word & FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F) != 0);
1002 rss->u.basicvirtual.syn4tupenipv6 =
1003 ((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F) != 0);
1004 rss->u.basicvirtual.syn2tupenipv6 =
1005 ((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F) != 0);
1006 rss->u.basicvirtual.syn4tupenipv4 =
1007 ((word & FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F) != 0);
1008 rss->u.basicvirtual.syn2tupenipv4 =
1009 ((word & FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F) != 0);
1010
1011 rss->u.basicvirtual.ofdmapen =
1012 ((word & FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F) != 0);
1013
1014 rss->u.basicvirtual.tnlmapen =
1015 ((word & FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F) != 0);
1016 rss->u.basicvirtual.tnlalllookup =
1017 ((word & FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F) != 0);
1018
1019 rss->u.basicvirtual.hashtoeplitz =
1020 ((word & FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F) != 0);
1021
1022
1023 if (!rss->u.basicvirtual.tnlmapen)
1024 return -EINVAL;
1025 break;
1026 }
1027
1028 default:
1029
1030 return -EINVAL;
1031 }
1032
1033 return 0;
1034}
1035
1036
1037
1038
1039
1040
1041
1042
1043int t4vf_get_vfres(struct adapter *adapter)
1044{
1045 struct vf_resources *vfres = &adapter->params.vfres;
1046 struct fw_pfvf_cmd cmd, rpl;
1047 int v;
1048 u32 word;
1049
1050
1051
1052
1053
1054 memset(&cmd, 0, sizeof(cmd));
1055 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
1056 FW_CMD_REQUEST_F |
1057 FW_CMD_READ_F);
1058 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1059 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1060 if (v)
1061 return v;
1062
1063
1064
1065
1066 word = be32_to_cpu(rpl.niqflint_niq);
1067 vfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
1068 vfres->niq = FW_PFVF_CMD_NIQ_G(word);
1069
1070 word = be32_to_cpu(rpl.type_to_neq);
1071 vfres->neq = FW_PFVF_CMD_NEQ_G(word);
1072 vfres->pmask = FW_PFVF_CMD_PMASK_G(word);
1073
1074 word = be32_to_cpu(rpl.tc_to_nexactf);
1075 vfres->tc = FW_PFVF_CMD_TC_G(word);
1076 vfres->nvi = FW_PFVF_CMD_NVI_G(word);
1077 vfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
1078
1079 word = be32_to_cpu(rpl.r_caps_to_nethctrl);
1080 vfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
1081 vfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
1082 vfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
1083
1084 return 0;
1085}
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096int t4vf_read_rss_vi_config(struct adapter *adapter, unsigned int viid,
1097 union rss_vi_config *config)
1098{
1099 struct fw_rss_vi_config_cmd cmd, rpl;
1100 int v;
1101
1102 memset(&cmd, 0, sizeof(cmd));
1103 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
1104 FW_CMD_REQUEST_F |
1105 FW_CMD_READ_F |
1106 FW_RSS_VI_CONFIG_CMD_VIID(viid));
1107 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1108 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1109 if (v)
1110 return v;
1111
1112 switch (adapter->params.rss.mode) {
1113 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
1114 u32 word = be32_to_cpu(rpl.u.basicvirtual.defaultq_to_udpen);
1115
1116 config->basicvirtual.ip6fourtupen =
1117 ((word & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F) != 0);
1118 config->basicvirtual.ip6twotupen =
1119 ((word & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F) != 0);
1120 config->basicvirtual.ip4fourtupen =
1121 ((word & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F) != 0);
1122 config->basicvirtual.ip4twotupen =
1123 ((word & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F) != 0);
1124 config->basicvirtual.udpen =
1125 ((word & FW_RSS_VI_CONFIG_CMD_UDPEN_F) != 0);
1126 config->basicvirtual.defaultq =
1127 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(word);
1128 break;
1129 }
1130
1131 default:
1132 return -EINVAL;
1133 }
1134
1135 return 0;
1136}
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147int t4vf_write_rss_vi_config(struct adapter *adapter, unsigned int viid,
1148 union rss_vi_config *config)
1149{
1150 struct fw_rss_vi_config_cmd cmd, rpl;
1151
1152 memset(&cmd, 0, sizeof(cmd));
1153 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
1154 FW_CMD_REQUEST_F |
1155 FW_CMD_WRITE_F |
1156 FW_RSS_VI_CONFIG_CMD_VIID(viid));
1157 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1158 switch (adapter->params.rss.mode) {
1159 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL: {
1160 u32 word = 0;
1161
1162 if (config->basicvirtual.ip6fourtupen)
1163 word |= FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F;
1164 if (config->basicvirtual.ip6twotupen)
1165 word |= FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F;
1166 if (config->basicvirtual.ip4fourtupen)
1167 word |= FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F;
1168 if (config->basicvirtual.ip4twotupen)
1169 word |= FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F;
1170 if (config->basicvirtual.udpen)
1171 word |= FW_RSS_VI_CONFIG_CMD_UDPEN_F;
1172 word |= FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(
1173 config->basicvirtual.defaultq);
1174 cmd.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(word);
1175 break;
1176 }
1177
1178 default:
1179 return -EINVAL;
1180 }
1181
1182 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1183}
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200int t4vf_config_rss_range(struct adapter *adapter, unsigned int viid,
1201 int start, int n, const u16 *rspq, int nrspq)
1202{
1203 const u16 *rsp = rspq;
1204 const u16 *rsp_end = rspq+nrspq;
1205 struct fw_rss_ind_tbl_cmd cmd;
1206
1207
1208
1209
1210 memset(&cmd, 0, sizeof(cmd));
1211 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
1212 FW_CMD_REQUEST_F |
1213 FW_CMD_WRITE_F |
1214 FW_RSS_IND_TBL_CMD_VIID_V(viid));
1215 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1216
1217
1218
1219
1220
1221
1222
1223 while (n > 0) {
1224 __be32 *qp = &cmd.iq0_to_iq2;
1225 int nq = min(n, 32);
1226 int ret;
1227
1228
1229
1230
1231
1232 cmd.niqid = cpu_to_be16(nq);
1233 cmd.startidx = cpu_to_be16(start);
1234
1235
1236
1237
1238 start += nq;
1239 n -= nq;
1240
1241
1242
1243
1244
1245
1246 while (nq > 0) {
1247
1248
1249
1250
1251
1252
1253 u16 qbuf[3];
1254 u16 *qbp = qbuf;
1255 int nqbuf = min(3, nq);
1256
1257 nq -= nqbuf;
1258 qbuf[0] = qbuf[1] = qbuf[2] = 0;
1259 while (nqbuf) {
1260 nqbuf--;
1261 *qbp++ = *rsp++;
1262 if (rsp >= rsp_end)
1263 rsp = rspq;
1264 }
1265 *qp++ = cpu_to_be32(FW_RSS_IND_TBL_CMD_IQ0_V(qbuf[0]) |
1266 FW_RSS_IND_TBL_CMD_IQ1_V(qbuf[1]) |
1267 FW_RSS_IND_TBL_CMD_IQ2_V(qbuf[2]));
1268 }
1269
1270
1271
1272
1273
1274 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1275 if (ret)
1276 return ret;
1277 }
1278 return 0;
1279}
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290int t4vf_alloc_vi(struct adapter *adapter, int port_id)
1291{
1292 struct fw_vi_cmd cmd, rpl;
1293 int v;
1294
1295
1296
1297
1298
1299 memset(&cmd, 0, sizeof(cmd));
1300 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
1301 FW_CMD_REQUEST_F |
1302 FW_CMD_WRITE_F |
1303 FW_CMD_EXEC_F);
1304 cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
1305 FW_VI_CMD_ALLOC_F);
1306 cmd.portid_pkd = FW_VI_CMD_PORTID_V(port_id);
1307 v = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1308 if (v)
1309 return v;
1310
1311 return FW_VI_CMD_VIID_G(be16_to_cpu(rpl.type_viid));
1312}
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322int t4vf_free_vi(struct adapter *adapter, int viid)
1323{
1324 struct fw_vi_cmd cmd;
1325
1326
1327
1328
1329 memset(&cmd, 0, sizeof(cmd));
1330 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
1331 FW_CMD_REQUEST_F |
1332 FW_CMD_EXEC_F);
1333 cmd.alloc_to_len16 = cpu_to_be32(FW_LEN16(cmd) |
1334 FW_VI_CMD_FREE_F);
1335 cmd.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
1336 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1337}
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348int t4vf_enable_vi(struct adapter *adapter, unsigned int viid,
1349 bool rx_en, bool tx_en)
1350{
1351 struct fw_vi_enable_cmd cmd;
1352
1353 memset(&cmd, 0, sizeof(cmd));
1354 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
1355 FW_CMD_REQUEST_F |
1356 FW_CMD_EXEC_F |
1357 FW_VI_ENABLE_CMD_VIID_V(viid));
1358 cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
1359 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
1360 FW_LEN16(cmd));
1361 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1362}
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372int t4vf_identify_port(struct adapter *adapter, unsigned int viid,
1373 unsigned int nblinks)
1374{
1375 struct fw_vi_enable_cmd cmd;
1376
1377 memset(&cmd, 0, sizeof(cmd));
1378 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
1379 FW_CMD_REQUEST_F |
1380 FW_CMD_EXEC_F |
1381 FW_VI_ENABLE_CMD_VIID_V(viid));
1382 cmd.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F |
1383 FW_LEN16(cmd));
1384 cmd.blinkdur = cpu_to_be16(nblinks);
1385 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1386}
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401int t4vf_set_rxmode(struct adapter *adapter, unsigned int viid,
1402 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1403 bool sleep_ok)
1404{
1405 struct fw_vi_rxmode_cmd cmd;
1406
1407
1408 if (mtu < 0)
1409 mtu = FW_VI_RXMODE_CMD_MTU_M;
1410 if (promisc < 0)
1411 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
1412 if (all_multi < 0)
1413 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
1414 if (bcast < 0)
1415 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
1416 if (vlanex < 0)
1417 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
1418
1419 memset(&cmd, 0, sizeof(cmd));
1420 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
1421 FW_CMD_REQUEST_F |
1422 FW_CMD_WRITE_F |
1423 FW_VI_RXMODE_CMD_VIID_V(viid));
1424 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
1425 cmd.mtu_to_vlanexen =
1426 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
1427 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
1428 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
1429 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
1430 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
1431 return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
1432}
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455int t4vf_alloc_mac_filt(struct adapter *adapter, unsigned int viid, bool free,
1456 unsigned int naddr, const u8 **addr, u16 *idx,
1457 u64 *hash, bool sleep_ok)
1458{
1459 int offset, ret = 0;
1460 unsigned nfilters = 0;
1461 unsigned int rem = naddr;
1462 struct fw_vi_mac_cmd cmd, rpl;
1463 unsigned int max_naddr = adapter->params.arch.mps_tcam_size;
1464
1465 if (naddr > max_naddr)
1466 return -EINVAL;
1467
1468 for (offset = 0; offset < naddr; ) {
1469 unsigned int fw_naddr = (rem < ARRAY_SIZE(cmd.u.exact)
1470 ? rem
1471 : ARRAY_SIZE(cmd.u.exact));
1472 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1473 u.exact[fw_naddr]), 16);
1474 struct fw_vi_mac_exact *p;
1475 int i;
1476
1477 memset(&cmd, 0, sizeof(cmd));
1478 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1479 FW_CMD_REQUEST_F |
1480 FW_CMD_WRITE_F |
1481 (free ? FW_CMD_EXEC_F : 0) |
1482 FW_VI_MAC_CMD_VIID_V(viid));
1483 cmd.freemacs_to_len16 =
1484 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
1485 FW_CMD_LEN16_V(len16));
1486
1487 for (i = 0, p = cmd.u.exact; i < fw_naddr; i++, p++) {
1488 p->valid_to_idx = cpu_to_be16(
1489 FW_VI_MAC_CMD_VALID_F |
1490 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
1491 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
1492 }
1493
1494
1495 ret = t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), &rpl,
1496 sleep_ok);
1497 if (ret && ret != -ENOMEM)
1498 break;
1499
1500 for (i = 0, p = rpl.u.exact; i < fw_naddr; i++, p++) {
1501 u16 index = FW_VI_MAC_CMD_IDX_G(
1502 be16_to_cpu(p->valid_to_idx));
1503
1504 if (idx)
1505 idx[offset+i] =
1506 (index >= max_naddr
1507 ? 0xffff
1508 : index);
1509 if (index < max_naddr)
1510 nfilters++;
1511 else if (hash)
1512 *hash |= (1ULL << hash_mac_addr(addr[offset+i]));
1513 }
1514
1515 free = false;
1516 offset += fw_naddr;
1517 rem -= fw_naddr;
1518 }
1519
1520
1521
1522
1523
1524 if (ret == 0 || ret == -ENOMEM)
1525 ret = nfilters;
1526 return ret;
1527}
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541int t4vf_free_mac_filt(struct adapter *adapter, unsigned int viid,
1542 unsigned int naddr, const u8 **addr, bool sleep_ok)
1543{
1544 int offset, ret = 0;
1545 struct fw_vi_mac_cmd cmd;
1546 unsigned int nfilters = 0;
1547 unsigned int max_naddr = adapter->params.arch.mps_tcam_size;
1548 unsigned int rem = naddr;
1549
1550 if (naddr > max_naddr)
1551 return -EINVAL;
1552
1553 for (offset = 0; offset < (int)naddr ; ) {
1554 unsigned int fw_naddr = (rem < ARRAY_SIZE(cmd.u.exact) ?
1555 rem : ARRAY_SIZE(cmd.u.exact));
1556 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1557 u.exact[fw_naddr]), 16);
1558 struct fw_vi_mac_exact *p;
1559 int i;
1560
1561 memset(&cmd, 0, sizeof(cmd));
1562 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1563 FW_CMD_REQUEST_F |
1564 FW_CMD_WRITE_F |
1565 FW_CMD_EXEC_V(0) |
1566 FW_VI_MAC_CMD_VIID_V(viid));
1567 cmd.freemacs_to_len16 =
1568 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
1569 FW_CMD_LEN16_V(len16));
1570
1571 for (i = 0, p = cmd.u.exact; i < (int)fw_naddr; i++, p++) {
1572 p->valid_to_idx = cpu_to_be16(
1573 FW_VI_MAC_CMD_VALID_F |
1574 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
1575 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
1576 }
1577
1578 ret = t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), &cmd,
1579 sleep_ok);
1580 if (ret)
1581 break;
1582
1583 for (i = 0, p = cmd.u.exact; i < fw_naddr; i++, p++) {
1584 u16 index = FW_VI_MAC_CMD_IDX_G(
1585 be16_to_cpu(p->valid_to_idx));
1586
1587 if (index < max_naddr)
1588 nfilters++;
1589 }
1590
1591 offset += fw_naddr;
1592 rem -= fw_naddr;
1593 }
1594
1595 if (ret == 0)
1596 ret = nfilters;
1597 return ret;
1598}
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618int t4vf_change_mac(struct adapter *adapter, unsigned int viid,
1619 int idx, const u8 *addr, bool persist)
1620{
1621 int ret;
1622 struct fw_vi_mac_cmd cmd, rpl;
1623 struct fw_vi_mac_exact *p = &cmd.u.exact[0];
1624 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1625 u.exact[1]), 16);
1626 unsigned int max_mac_addr = adapter->params.arch.mps_tcam_size;
1627
1628
1629
1630
1631
1632 if (idx < 0)
1633 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
1634
1635 memset(&cmd, 0, sizeof(cmd));
1636 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1637 FW_CMD_REQUEST_F |
1638 FW_CMD_WRITE_F |
1639 FW_VI_MAC_CMD_VIID_V(viid));
1640 cmd.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
1641 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
1642 FW_VI_MAC_CMD_IDX_V(idx));
1643 memcpy(p->macaddr, addr, sizeof(p->macaddr));
1644
1645 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
1646 if (ret == 0) {
1647 p = &rpl.u.exact[0];
1648 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
1649 if (ret >= max_mac_addr)
1650 ret = -ENOMEM;
1651 }
1652 return ret;
1653}
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665int t4vf_set_addr_hash(struct adapter *adapter, unsigned int viid,
1666 bool ucast, u64 vec, bool sleep_ok)
1667{
1668 struct fw_vi_mac_cmd cmd;
1669 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
1670 u.exact[0]), 16);
1671
1672 memset(&cmd, 0, sizeof(cmd));
1673 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
1674 FW_CMD_REQUEST_F |
1675 FW_CMD_WRITE_F |
1676 FW_VI_ENABLE_CMD_VIID_V(viid));
1677 cmd.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
1678 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
1679 FW_CMD_LEN16_V(len16));
1680 cmd.u.hash.hashvec = cpu_to_be64(vec);
1681 return t4vf_wr_mbox_core(adapter, &cmd, sizeof(cmd), NULL, sleep_ok);
1682}
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692int t4vf_get_port_stats(struct adapter *adapter, int pidx,
1693 struct t4vf_port_stats *s)
1694{
1695 struct port_info *pi = adap2pinfo(adapter, pidx);
1696 struct fw_vi_stats_vf fwstats;
1697 unsigned int rem = VI_VF_NUM_STATS;
1698 __be64 *fwsp = (__be64 *)&fwstats;
1699
1700
1701
1702
1703
1704
1705 while (rem) {
1706 unsigned int ix = VI_VF_NUM_STATS - rem;
1707 unsigned int nstats = min(6U, rem);
1708 struct fw_vi_stats_cmd cmd, rpl;
1709 size_t len = (offsetof(struct fw_vi_stats_cmd, u) +
1710 sizeof(struct fw_vi_stats_ctl));
1711 size_t len16 = DIV_ROUND_UP(len, 16);
1712 int ret;
1713
1714 memset(&cmd, 0, sizeof(cmd));
1715 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_STATS_CMD) |
1716 FW_VI_STATS_CMD_VIID_V(pi->viid) |
1717 FW_CMD_REQUEST_F |
1718 FW_CMD_READ_F);
1719 cmd.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(len16));
1720 cmd.u.ctl.nstats_ix =
1721 cpu_to_be16(FW_VI_STATS_CMD_IX_V(ix) |
1722 FW_VI_STATS_CMD_NSTATS_V(nstats));
1723 ret = t4vf_wr_mbox_ns(adapter, &cmd, len, &rpl);
1724 if (ret)
1725 return ret;
1726
1727 memcpy(fwsp, &rpl.u.ctl.stat0, sizeof(__be64) * nstats);
1728
1729 rem -= nstats;
1730 fwsp += nstats;
1731 }
1732
1733
1734
1735
1736 s->tx_bcast_bytes = be64_to_cpu(fwstats.tx_bcast_bytes);
1737 s->tx_bcast_frames = be64_to_cpu(fwstats.tx_bcast_frames);
1738 s->tx_mcast_bytes = be64_to_cpu(fwstats.tx_mcast_bytes);
1739 s->tx_mcast_frames = be64_to_cpu(fwstats.tx_mcast_frames);
1740 s->tx_ucast_bytes = be64_to_cpu(fwstats.tx_ucast_bytes);
1741 s->tx_ucast_frames = be64_to_cpu(fwstats.tx_ucast_frames);
1742 s->tx_drop_frames = be64_to_cpu(fwstats.tx_drop_frames);
1743 s->tx_offload_bytes = be64_to_cpu(fwstats.tx_offload_bytes);
1744 s->tx_offload_frames = be64_to_cpu(fwstats.tx_offload_frames);
1745
1746 s->rx_bcast_bytes = be64_to_cpu(fwstats.rx_bcast_bytes);
1747 s->rx_bcast_frames = be64_to_cpu(fwstats.rx_bcast_frames);
1748 s->rx_mcast_bytes = be64_to_cpu(fwstats.rx_mcast_bytes);
1749 s->rx_mcast_frames = be64_to_cpu(fwstats.rx_mcast_frames);
1750 s->rx_ucast_bytes = be64_to_cpu(fwstats.rx_ucast_bytes);
1751 s->rx_ucast_frames = be64_to_cpu(fwstats.rx_ucast_frames);
1752
1753 s->rx_err_frames = be64_to_cpu(fwstats.rx_err_frames);
1754
1755 return 0;
1756}
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768int t4vf_iq_free(struct adapter *adapter, unsigned int iqtype,
1769 unsigned int iqid, unsigned int fl0id, unsigned int fl1id)
1770{
1771 struct fw_iq_cmd cmd;
1772
1773 memset(&cmd, 0, sizeof(cmd));
1774 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) |
1775 FW_CMD_REQUEST_F |
1776 FW_CMD_EXEC_F);
1777 cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F |
1778 FW_LEN16(cmd));
1779 cmd.type_to_iqandstindex =
1780 cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
1781
1782 cmd.iqid = cpu_to_be16(iqid);
1783 cmd.fl0id = cpu_to_be16(fl0id);
1784 cmd.fl1id = cpu_to_be16(fl1id);
1785 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1786}
1787
1788
1789
1790
1791
1792
1793
1794
1795int t4vf_eth_eq_free(struct adapter *adapter, unsigned int eqid)
1796{
1797 struct fw_eq_eth_cmd cmd;
1798
1799 memset(&cmd, 0, sizeof(cmd));
1800 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
1801 FW_CMD_REQUEST_F |
1802 FW_CMD_EXEC_F);
1803 cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F |
1804 FW_LEN16(cmd));
1805 cmd.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
1806 return t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), NULL);
1807}
1808
1809
1810
1811
1812
1813
1814
1815static const char *t4vf_link_down_rc_str(unsigned char link_down_rc)
1816{
1817 static const char * const reason[] = {
1818 "Link Down",
1819 "Remote Fault",
1820 "Auto-negotiation Failure",
1821 "Reserved",
1822 "Insufficient Airflow",
1823 "Unable To Determine Reason",
1824 "No RX Signal Detected",
1825 "Reserved",
1826 };
1827
1828 if (link_down_rc >= ARRAY_SIZE(reason))
1829 return "Bad Reason Code";
1830
1831 return reason[link_down_rc];
1832}
1833
1834
1835
1836
1837
1838
1839
1840
1841static void t4vf_handle_get_port_info(struct port_info *pi,
1842 const struct fw_port_cmd *cmd)
1843{
1844 int action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
1845 struct adapter *adapter = pi->adapter;
1846 struct link_config *lc = &pi->link_cfg;
1847 int link_ok, linkdnrc;
1848 enum fw_port_type port_type;
1849 enum fw_port_module_type mod_type;
1850 unsigned int speed, fc, fec;
1851 fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
1852
1853
1854 switch (action) {
1855 case FW_PORT_ACTION_GET_PORT_INFO: {
1856 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
1857
1858 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
1859 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
1860 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
1861 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
1862 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
1863 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
1864 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
1865
1866
1867
1868
1869
1870 linkattr = 0;
1871 if (lstatus & FW_PORT_CMD_RXPAUSE_F)
1872 linkattr |= FW_PORT_CAP32_FC_RX;
1873 if (lstatus & FW_PORT_CMD_TXPAUSE_F)
1874 linkattr |= FW_PORT_CAP32_FC_TX;
1875 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
1876 linkattr |= FW_PORT_CAP32_SPEED_100M;
1877 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
1878 linkattr |= FW_PORT_CAP32_SPEED_1G;
1879 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
1880 linkattr |= FW_PORT_CAP32_SPEED_10G;
1881 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
1882 linkattr |= FW_PORT_CAP32_SPEED_25G;
1883 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
1884 linkattr |= FW_PORT_CAP32_SPEED_40G;
1885 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
1886 linkattr |= FW_PORT_CAP32_SPEED_100G;
1887
1888 break;
1889 }
1890
1891 case FW_PORT_ACTION_GET_PORT_INFO32: {
1892 u32 lstatus32;
1893
1894 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
1895 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
1896 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
1897 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
1898 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
1899 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
1900 acaps = be32_to_cpu(cmd->u.info32.acaps32);
1901 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
1902 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
1903 break;
1904 }
1905
1906 default:
1907 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
1908 be32_to_cpu(cmd->action_to_len16));
1909 return;
1910 }
1911
1912 fec = fwcap_to_cc_fec(acaps);
1913 fc = fwcap_to_cc_pause(linkattr);
1914 speed = fwcap_to_speed(linkattr);
1915
1916 if (mod_type != pi->mod_type) {
1917
1918
1919
1920
1921
1922
1923
1924 lc->auto_fec = fec;
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936 pi->port_type = port_type;
1937
1938 pi->mod_type = mod_type;
1939 t4vf_os_portmod_changed(adapter, pi->pidx);
1940 }
1941
1942 if (link_ok != lc->link_ok || speed != lc->speed ||
1943 fc != lc->fc || fec != lc->fec) {
1944 if (!link_ok && lc->link_ok) {
1945 lc->link_down_rc = linkdnrc;
1946 dev_warn(adapter->pdev_dev, "Port %d link down, reason: %s\n",
1947 pi->port_id, t4vf_link_down_rc_str(linkdnrc));
1948 }
1949 lc->link_ok = link_ok;
1950 lc->speed = speed;
1951 lc->fc = fc;
1952 lc->fec = fec;
1953
1954 lc->pcaps = pcaps;
1955 lc->lpacaps = lpacaps;
1956 lc->acaps = acaps & ADVERT_MASK;
1957
1958 if (lc->acaps & FW_PORT_CAP32_ANEG) {
1959 lc->autoneg = AUTONEG_ENABLE;
1960 } else {
1961
1962
1963
1964
1965 lc->acaps = 0;
1966 lc->speed_caps = fwcap_to_speed(acaps);
1967 lc->autoneg = AUTONEG_DISABLE;
1968 }
1969
1970 t4vf_os_link_changed(adapter, pi->pidx, link_ok);
1971 }
1972}
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982int t4vf_update_port_info(struct port_info *pi)
1983{
1984 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
1985 struct fw_port_cmd port_cmd;
1986 int ret;
1987
1988 memset(&port_cmd, 0, sizeof(port_cmd));
1989 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
1990 FW_CMD_REQUEST_F | FW_CMD_READ_F |
1991 FW_PORT_CMD_PORTID_V(pi->port_id));
1992 port_cmd.action_to_len16 = cpu_to_be32(
1993 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
1994 ? FW_PORT_ACTION_GET_PORT_INFO
1995 : FW_PORT_ACTION_GET_PORT_INFO32) |
1996 FW_LEN16(port_cmd));
1997 ret = t4vf_wr_mbox(pi->adapter, &port_cmd, sizeof(port_cmd),
1998 &port_cmd);
1999 if (ret)
2000 return ret;
2001 t4vf_handle_get_port_info(pi, &port_cmd);
2002 return 0;
2003}
2004
2005
2006
2007
2008
2009
2010
2011
2012int t4vf_handle_fw_rpl(struct adapter *adapter, const __be64 *rpl)
2013{
2014 const struct fw_cmd_hdr *cmd_hdr = (const struct fw_cmd_hdr *)rpl;
2015 u8 opcode = FW_CMD_OP_G(be32_to_cpu(cmd_hdr->hi));
2016
2017 switch (opcode) {
2018 case FW_PORT_CMD: {
2019
2020
2021
2022 const struct fw_port_cmd *port_cmd =
2023 (const struct fw_port_cmd *)rpl;
2024 int action = FW_PORT_CMD_ACTION_G(
2025 be32_to_cpu(port_cmd->action_to_len16));
2026 int port_id, pidx;
2027
2028 if (action != FW_PORT_ACTION_GET_PORT_INFO &&
2029 action != FW_PORT_ACTION_GET_PORT_INFO32) {
2030 dev_err(adapter->pdev_dev,
2031 "Unknown firmware PORT reply action %x\n",
2032 action);
2033 break;
2034 }
2035
2036 port_id = FW_PORT_CMD_PORTID_G(
2037 be32_to_cpu(port_cmd->op_to_portid));
2038 for_each_port(adapter, pidx) {
2039 struct port_info *pi = adap2pinfo(adapter, pidx);
2040
2041 if (pi->port_id != port_id)
2042 continue;
2043 t4vf_handle_get_port_info(pi, port_cmd);
2044 }
2045 break;
2046 }
2047
2048 default:
2049 dev_err(adapter->pdev_dev, "Unknown firmware reply %X\n",
2050 opcode);
2051 }
2052 return 0;
2053}
2054
2055
2056
2057int t4vf_prep_adapter(struct adapter *adapter)
2058{
2059 int err;
2060 unsigned int chipid;
2061
2062
2063
2064 err = t4vf_wait_dev_ready(adapter);
2065 if (err)
2066 return err;
2067
2068
2069
2070
2071 adapter->params.nports = 1;
2072 adapter->params.vfres.pmask = 1;
2073 adapter->params.vpd.cclk = 50000;
2074
2075 adapter->params.chip = 0;
2076 switch (CHELSIO_PCI_ID_VER(adapter->pdev->device)) {
2077 case CHELSIO_T4:
2078 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, 0);
2079 adapter->params.arch.sge_fl_db = DBPRIO_F;
2080 adapter->params.arch.mps_tcam_size =
2081 NUM_MPS_CLS_SRAM_L_INSTANCES;
2082 break;
2083
2084 case CHELSIO_T5:
2085 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
2086 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, chipid);
2087 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
2088 adapter->params.arch.mps_tcam_size =
2089 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
2090 break;
2091
2092 case CHELSIO_T6:
2093 chipid = REV_G(t4_read_reg(adapter, PL_VF_REV_A));
2094 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, chipid);
2095 adapter->params.arch.sge_fl_db = 0;
2096 adapter->params.arch.mps_tcam_size =
2097 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
2098 break;
2099 }
2100
2101 return 0;
2102}
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115int t4vf_get_vf_mac_acl(struct adapter *adapter, unsigned int pf,
2116 unsigned int *naddr, u8 *addr)
2117{
2118 struct fw_acl_mac_cmd cmd;
2119 int ret;
2120
2121 memset(&cmd, 0, sizeof(cmd));
2122 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
2123 FW_CMD_REQUEST_F |
2124 FW_CMD_READ_F);
2125 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
2126 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &cmd);
2127 if (ret)
2128 return ret;
2129
2130 if (cmd.nmac < *naddr)
2131 *naddr = cmd.nmac;
2132
2133 switch (pf) {
2134 case 3:
2135 memcpy(addr, cmd.macaddr3, sizeof(cmd.macaddr3));
2136 break;
2137 case 2:
2138 memcpy(addr, cmd.macaddr2, sizeof(cmd.macaddr2));
2139 break;
2140 case 1:
2141 memcpy(addr, cmd.macaddr1, sizeof(cmd.macaddr1));
2142 break;
2143 case 0:
2144 memcpy(addr, cmd.macaddr0, sizeof(cmd.macaddr0));
2145 break;
2146 }
2147
2148 return ret;
2149}
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159int t4vf_get_vf_vlan_acl(struct adapter *adapter)
2160{
2161 struct fw_acl_vlan_cmd cmd;
2162 int vlan = 0;
2163 int ret = 0;
2164
2165 cmd.op_to_vfn = htonl(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
2166 FW_CMD_REQUEST_F | FW_CMD_READ_F);
2167
2168
2169 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
2170
2171 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &cmd);
2172
2173 if (!ret)
2174 vlan = be16_to_cpu(cmd.vlanid[0]);
2175
2176 return vlan;
2177}
2178