linux/drivers/net/ethernet/mellanox/mlx4/qp.c
<<
>>
Prefs
   1/*
   2 * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
   4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6 *
   7 * This software is available to you under a choice of one of two
   8 * licenses.  You may choose to be licensed under the terms of the GNU
   9 * General Public License (GPL) Version 2, available from the file
  10 * COPYING in the main directory of this source tree, or the
  11 * OpenIB.org BSD license below:
  12 *
  13 *     Redistribution and use in source and binary forms, with or
  14 *     without modification, are permitted provided that the following
  15 *     conditions are met:
  16 *
  17 *      - Redistributions of source code must retain the above
  18 *        copyright notice, this list of conditions and the following
  19 *        disclaimer.
  20 *
  21 *      - Redistributions in binary form must reproduce the above
  22 *        copyright notice, this list of conditions and the following
  23 *        disclaimer in the documentation and/or other materials
  24 *        provided with the distribution.
  25 *
  26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33 * SOFTWARE.
  34 */
  35
  36#include <linux/gfp.h>
  37#include <linux/export.h>
  38
  39#include <linux/mlx4/cmd.h>
  40#include <linux/mlx4/qp.h>
  41
  42#include "mlx4.h"
  43#include "icm.h"
  44
  45/* QP to support BF should have bits 6,7 cleared */
  46#define MLX4_BF_QP_SKIP_MASK    0xc0
  47#define MLX4_MAX_BF_QP_RANGE    0x40
  48
  49void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
  50{
  51        struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
  52        struct mlx4_qp *qp;
  53
  54        spin_lock(&qp_table->lock);
  55
  56        qp = __mlx4_qp_lookup(dev, qpn);
  57        if (qp)
  58                refcount_inc(&qp->refcount);
  59
  60        spin_unlock(&qp_table->lock);
  61
  62        if (!qp) {
  63                mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn);
  64                return;
  65        }
  66
  67        qp->event(qp, event_type);
  68
  69        if (refcount_dec_and_test(&qp->refcount))
  70                complete(&qp->free);
  71}
  72
  73/* used for INIT/CLOSE port logic */
  74static int is_master_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp, int *real_qp0, int *proxy_qp0)
  75{
  76        /* this procedure is called after we already know we are on the master */
  77        /* qp0 is either the proxy qp0, or the real qp0 */
  78        u32 pf_proxy_offset = dev->phys_caps.base_proxy_sqpn + 8 * mlx4_master_func_num(dev);
  79        *proxy_qp0 = qp->qpn >= pf_proxy_offset && qp->qpn <= pf_proxy_offset + 1;
  80
  81        *real_qp0 = qp->qpn >= dev->phys_caps.base_sqpn &&
  82                qp->qpn <= dev->phys_caps.base_sqpn + 1;
  83
  84        return *real_qp0 || *proxy_qp0;
  85}
  86
  87static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
  88                     enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
  89                     struct mlx4_qp_context *context,
  90                     enum mlx4_qp_optpar optpar,
  91                     int sqd_event, struct mlx4_qp *qp, int native)
  92{
  93        static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
  94                [MLX4_QP_STATE_RST] = {
  95                        [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
  96                        [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
  97                        [MLX4_QP_STATE_INIT]    = MLX4_CMD_RST2INIT_QP,
  98                },
  99                [MLX4_QP_STATE_INIT]  = {
 100                        [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 101                        [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 102                        [MLX4_QP_STATE_INIT]    = MLX4_CMD_INIT2INIT_QP,
 103                        [MLX4_QP_STATE_RTR]     = MLX4_CMD_INIT2RTR_QP,
 104                },
 105                [MLX4_QP_STATE_RTR]   = {
 106                        [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 107                        [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 108                        [MLX4_QP_STATE_RTS]     = MLX4_CMD_RTR2RTS_QP,
 109                },
 110                [MLX4_QP_STATE_RTS]   = {
 111                        [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 112                        [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 113                        [MLX4_QP_STATE_RTS]     = MLX4_CMD_RTS2RTS_QP,
 114                        [MLX4_QP_STATE_SQD]     = MLX4_CMD_RTS2SQD_QP,
 115                },
 116                [MLX4_QP_STATE_SQD] = {
 117                        [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 118                        [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 119                        [MLX4_QP_STATE_RTS]     = MLX4_CMD_SQD2RTS_QP,
 120                        [MLX4_QP_STATE_SQD]     = MLX4_CMD_SQD2SQD_QP,
 121                },
 122                [MLX4_QP_STATE_SQER] = {
 123                        [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 124                        [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 125                        [MLX4_QP_STATE_RTS]     = MLX4_CMD_SQERR2RTS_QP,
 126                },
 127                [MLX4_QP_STATE_ERR] = {
 128                        [MLX4_QP_STATE_RST]     = MLX4_CMD_2RST_QP,
 129                        [MLX4_QP_STATE_ERR]     = MLX4_CMD_2ERR_QP,
 130                }
 131        };
 132
 133        struct mlx4_priv *priv = mlx4_priv(dev);
 134        struct mlx4_cmd_mailbox *mailbox;
 135        int ret = 0;
 136        int real_qp0 = 0;
 137        int proxy_qp0 = 0;
 138        u8 port;
 139
 140        if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE ||
 141            !op[cur_state][new_state])
 142                return -EINVAL;
 143
 144        if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) {
 145                ret = mlx4_cmd(dev, 0, qp->qpn, 2,
 146                        MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native);
 147                if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR &&
 148                    cur_state != MLX4_QP_STATE_RST &&
 149                    is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
 150                        port = (qp->qpn & 1) + 1;
 151                        if (proxy_qp0)
 152                                priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
 153                        else
 154                                priv->mfunc.master.qp0_state[port].qp0_active = 0;
 155                }
 156                return ret;
 157        }
 158
 159        mailbox = mlx4_alloc_cmd_mailbox(dev);
 160        if (IS_ERR(mailbox))
 161                return PTR_ERR(mailbox);
 162
 163        if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
 164                u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
 165                context->mtt_base_addr_h = mtt_addr >> 32;
 166                context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
 167                context->log_page_size   = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
 168        }
 169
 170        if ((cur_state == MLX4_QP_STATE_RTR) &&
 171            (new_state == MLX4_QP_STATE_RTS) &&
 172            dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
 173                context->roce_entropy =
 174                        cpu_to_be16(mlx4_qp_roce_entropy(dev, qp->qpn));
 175
 176        *(__be32 *) mailbox->buf = cpu_to_be32(optpar);
 177        memcpy(mailbox->buf + 8, context, sizeof(*context));
 178
 179        ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
 180                cpu_to_be32(qp->qpn);
 181
 182        ret = mlx4_cmd(dev, mailbox->dma,
 183                       qp->qpn | (!!sqd_event << 31),
 184                       new_state == MLX4_QP_STATE_RST ? 2 : 0,
 185                       op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native);
 186
 187        if (mlx4_is_master(dev) && is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
 188                port = (qp->qpn & 1) + 1;
 189                if (cur_state != MLX4_QP_STATE_ERR &&
 190                    cur_state != MLX4_QP_STATE_RST &&
 191                    new_state == MLX4_QP_STATE_ERR) {
 192                        if (proxy_qp0)
 193                                priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
 194                        else
 195                                priv->mfunc.master.qp0_state[port].qp0_active = 0;
 196                } else if (new_state == MLX4_QP_STATE_RTR) {
 197                        if (proxy_qp0)
 198                                priv->mfunc.master.qp0_state[port].proxy_qp0_active = 1;
 199                        else
 200                                priv->mfunc.master.qp0_state[port].qp0_active = 1;
 201                }
 202        }
 203
 204        mlx4_free_cmd_mailbox(dev, mailbox);
 205        return ret;
 206}
 207
 208int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 209                   enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
 210                   struct mlx4_qp_context *context,
 211                   enum mlx4_qp_optpar optpar,
 212                   int sqd_event, struct mlx4_qp *qp)
 213{
 214        return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context,
 215                                optpar, sqd_event, qp, 0);
 216}
 217EXPORT_SYMBOL_GPL(mlx4_qp_modify);
 218
 219int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 220                            int *base, u8 flags)
 221{
 222        u32 uid;
 223        int bf_qp = !!(flags & (u8)MLX4_RESERVE_ETH_BF_QP);
 224
 225        struct mlx4_priv *priv = mlx4_priv(dev);
 226        struct mlx4_qp_table *qp_table = &priv->qp_table;
 227
 228        if (cnt > MLX4_MAX_BF_QP_RANGE && bf_qp)
 229                return -ENOMEM;
 230
 231        uid = MLX4_QP_TABLE_ZONE_GENERAL;
 232        if (flags & (u8)MLX4_RESERVE_A0_QP) {
 233                if (bf_qp)
 234                        uid = MLX4_QP_TABLE_ZONE_RAW_ETH;
 235                else
 236                        uid = MLX4_QP_TABLE_ZONE_RSS;
 237        }
 238
 239        *base = mlx4_zone_alloc_entries(qp_table->zones, uid, cnt, align,
 240                                        bf_qp ? MLX4_BF_QP_SKIP_MASK : 0, NULL);
 241        if (*base == -1)
 242                return -ENOMEM;
 243
 244        return 0;
 245}
 246
 247int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
 248                          int *base, u8 flags, u8 usage)
 249{
 250        u32 in_modifier = RES_QP | (((u32)usage & 3) << 30);
 251        u64 in_param = 0;
 252        u64 out_param;
 253        int err;
 254
 255        /* Turn off all unsupported QP allocation flags */
 256        flags &= dev->caps.alloc_res_qp_mask;
 257
 258        if (mlx4_is_mfunc(dev)) {
 259                set_param_l(&in_param, (((u32)flags) << 24) | (u32)cnt);
 260                set_param_h(&in_param, align);
 261                err = mlx4_cmd_imm(dev, in_param, &out_param,
 262                                   in_modifier, RES_OP_RESERVE,
 263                                   MLX4_CMD_ALLOC_RES,
 264                                   MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 265                if (err)
 266                        return err;
 267
 268                *base = get_param_l(&out_param);
 269                return 0;
 270        }
 271        return __mlx4_qp_reserve_range(dev, cnt, align, base, flags);
 272}
 273EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);
 274
 275void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
 276{
 277        struct mlx4_priv *priv = mlx4_priv(dev);
 278        struct mlx4_qp_table *qp_table = &priv->qp_table;
 279
 280        if (mlx4_is_qp_reserved(dev, (u32) base_qpn))
 281                return;
 282        mlx4_zone_free_entries_unique(qp_table->zones, base_qpn, cnt);
 283}
 284
 285void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
 286{
 287        u64 in_param = 0;
 288        int err;
 289
 290        if (!cnt)
 291                return;
 292
 293        if (mlx4_is_mfunc(dev)) {
 294                set_param_l(&in_param, base_qpn);
 295                set_param_h(&in_param, cnt);
 296                err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
 297                               MLX4_CMD_FREE_RES,
 298                               MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
 299                if (err) {
 300                        mlx4_warn(dev, "Failed to release qp range base:%d cnt:%d\n",
 301                                  base_qpn, cnt);
 302                }
 303        } else
 304                 __mlx4_qp_release_range(dev, base_qpn, cnt);
 305}
 306EXPORT_SYMBOL_GPL(mlx4_qp_release_range);
 307
 308int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
 309{
 310        struct mlx4_priv *priv = mlx4_priv(dev);
 311        struct mlx4_qp_table *qp_table = &priv->qp_table;
 312        int err;
 313
 314        err = mlx4_table_get(dev, &qp_table->qp_table, qpn);
 315        if (err)
 316                goto err_out;
 317
 318        err = mlx4_table_get(dev, &qp_table->auxc_table, qpn);
 319        if (err)
 320                goto err_put_qp;
 321
 322        err = mlx4_table_get(dev, &qp_table->altc_table, qpn);
 323        if (err)
 324                goto err_put_auxc;
 325
 326        err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn);
 327        if (err)
 328                goto err_put_altc;
 329
 330        err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn);
 331        if (err)
 332                goto err_put_rdmarc;
 333
 334        return 0;
 335
 336err_put_rdmarc:
 337        mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
 338
 339err_put_altc:
 340        mlx4_table_put(dev, &qp_table->altc_table, qpn);
 341
 342err_put_auxc:
 343        mlx4_table_put(dev, &qp_table->auxc_table, qpn);
 344
 345err_put_qp:
 346        mlx4_table_put(dev, &qp_table->qp_table, qpn);
 347
 348err_out:
 349        return err;
 350}
 351
 352static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn)
 353{
 354        u64 param = 0;
 355
 356        if (mlx4_is_mfunc(dev)) {
 357                set_param_l(&param, qpn);
 358                return mlx4_cmd_imm(dev, param, &param, RES_QP, RES_OP_MAP_ICM,
 359                                    MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A,
 360                                    MLX4_CMD_WRAPPED);
 361        }
 362        return __mlx4_qp_alloc_icm(dev, qpn);
 363}
 364
 365void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
 366{
 367        struct mlx4_priv *priv = mlx4_priv(dev);
 368        struct mlx4_qp_table *qp_table = &priv->qp_table;
 369
 370        mlx4_table_put(dev, &qp_table->cmpt_table, qpn);
 371        mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
 372        mlx4_table_put(dev, &qp_table->altc_table, qpn);
 373        mlx4_table_put(dev, &qp_table->auxc_table, qpn);
 374        mlx4_table_put(dev, &qp_table->qp_table, qpn);
 375}
 376
 377static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
 378{
 379        u64 in_param = 0;
 380
 381        if (mlx4_is_mfunc(dev)) {
 382                set_param_l(&in_param, qpn);
 383                if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
 384                             MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
 385                             MLX4_CMD_WRAPPED))
 386                        mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn);
 387        } else
 388                __mlx4_qp_free_icm(dev, qpn);
 389}
 390
 391struct mlx4_qp *mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
 392{
 393        struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 394        struct mlx4_qp *qp;
 395
 396        spin_lock(&qp_table->lock);
 397
 398        qp = __mlx4_qp_lookup(dev, qpn);
 399
 400        spin_unlock(&qp_table->lock);
 401        return qp;
 402}
 403
 404int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp)
 405{
 406        struct mlx4_priv *priv = mlx4_priv(dev);
 407        struct mlx4_qp_table *qp_table = &priv->qp_table;
 408        int err;
 409
 410        if (!qpn)
 411                return -EINVAL;
 412
 413        qp->qpn = qpn;
 414
 415        err = mlx4_qp_alloc_icm(dev, qpn);
 416        if (err)
 417                return err;
 418
 419        spin_lock_irq(&qp_table->lock);
 420        err = radix_tree_insert(&dev->qp_table_tree, qp->qpn &
 421                                (dev->caps.num_qps - 1), qp);
 422        spin_unlock_irq(&qp_table->lock);
 423        if (err)
 424                goto err_icm;
 425
 426        refcount_set(&qp->refcount, 1);
 427        init_completion(&qp->free);
 428
 429        return 0;
 430
 431err_icm:
 432        mlx4_qp_free_icm(dev, qpn);
 433        return err;
 434}
 435
 436EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
 437
 438int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
 439                   enum mlx4_update_qp_attr attr,
 440                   struct mlx4_update_qp_params *params)
 441{
 442        struct mlx4_cmd_mailbox *mailbox;
 443        struct mlx4_update_qp_context *cmd;
 444        u64 pri_addr_path_mask = 0;
 445        u64 qp_mask = 0;
 446        int err = 0;
 447
 448        if (!attr || (attr & ~MLX4_UPDATE_QP_SUPPORTED_ATTRS))
 449                return -EINVAL;
 450
 451        mailbox = mlx4_alloc_cmd_mailbox(dev);
 452        if (IS_ERR(mailbox))
 453                return PTR_ERR(mailbox);
 454
 455        cmd = (struct mlx4_update_qp_context *)mailbox->buf;
 456
 457        if (attr & MLX4_UPDATE_QP_SMAC) {
 458                pri_addr_path_mask |= 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX;
 459                cmd->qp_context.pri_path.grh_mylmc = params->smac_index;
 460        }
 461
 462        if (attr & MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB) {
 463                if (!(dev->caps.flags2
 464                      & MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
 465                        mlx4_warn(dev,
 466                                  "Trying to set src check LB, but it isn't supported\n");
 467                        err = -EOPNOTSUPP;
 468                        goto out;
 469                }
 470                pri_addr_path_mask |=
 471                        1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB;
 472                if (params->flags &
 473                    MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB) {
 474                        cmd->qp_context.pri_path.fl |=
 475                                MLX4_FL_ETH_SRC_CHECK_MC_LB;
 476                }
 477        }
 478
 479        if (attr & MLX4_UPDATE_QP_VSD) {
 480                qp_mask |= 1ULL << MLX4_UPD_QP_MASK_VSD;
 481                if (params->flags & MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE)
 482                        cmd->qp_context.param3 |= cpu_to_be32(MLX4_STRIP_VLAN);
 483        }
 484
 485        if (attr & MLX4_UPDATE_QP_RATE_LIMIT) {
 486                qp_mask |= 1ULL << MLX4_UPD_QP_MASK_RATE_LIMIT;
 487                cmd->qp_context.rate_limit_params = cpu_to_be16((params->rate_unit << 14) | params->rate_val);
 488        }
 489
 490        if (attr & MLX4_UPDATE_QP_QOS_VPORT) {
 491                if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP)) {
 492                        mlx4_warn(dev, "Granular QoS per VF is not enabled\n");
 493                        err = -EOPNOTSUPP;
 494                        goto out;
 495                }
 496
 497                qp_mask |= 1ULL << MLX4_UPD_QP_MASK_QOS_VPP;
 498                cmd->qp_context.qos_vport = params->qos_vport;
 499        }
 500
 501        cmd->primary_addr_path_mask = cpu_to_be64(pri_addr_path_mask);
 502        cmd->qp_mask = cpu_to_be64(qp_mask);
 503
 504        err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0,
 505                       MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
 506                       MLX4_CMD_NATIVE);
 507out:
 508        mlx4_free_cmd_mailbox(dev, mailbox);
 509        return err;
 510}
 511EXPORT_SYMBOL_GPL(mlx4_update_qp);
 512
 513void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
 514{
 515        struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 516        unsigned long flags;
 517
 518        spin_lock_irqsave(&qp_table->lock, flags);
 519        radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
 520        spin_unlock_irqrestore(&qp_table->lock, flags);
 521}
 522EXPORT_SYMBOL_GPL(mlx4_qp_remove);
 523
 524void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
 525{
 526        if (refcount_dec_and_test(&qp->refcount))
 527                complete(&qp->free);
 528        wait_for_completion(&qp->free);
 529
 530        mlx4_qp_free_icm(dev, qp->qpn);
 531}
 532EXPORT_SYMBOL_GPL(mlx4_qp_free);
 533
 534static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
 535{
 536        return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
 537                        MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 538}
 539
 540#define MLX4_QP_TABLE_RSS_ETH_PRIORITY 2
 541#define MLX4_QP_TABLE_RAW_ETH_PRIORITY 1
 542#define MLX4_QP_TABLE_RAW_ETH_SIZE     256
 543
 544static int mlx4_create_zones(struct mlx4_dev *dev,
 545                             u32 reserved_bottom_general,
 546                             u32 reserved_top_general,
 547                             u32 reserved_bottom_rss,
 548                             u32 start_offset_rss,
 549                             u32 max_table_offset)
 550{
 551        struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 552        struct mlx4_bitmap (*bitmap)[MLX4_QP_TABLE_ZONE_NUM] = NULL;
 553        int bitmap_initialized = 0;
 554        u32 last_offset;
 555        int k;
 556        int err;
 557
 558        qp_table->zones = mlx4_zone_allocator_create(MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP);
 559
 560        if (NULL == qp_table->zones)
 561                return -ENOMEM;
 562
 563        bitmap = kmalloc(sizeof(*bitmap), GFP_KERNEL);
 564
 565        if (NULL == bitmap) {
 566                err = -ENOMEM;
 567                goto free_zone;
 568        }
 569
 570        err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_GENERAL, dev->caps.num_qps,
 571                               (1 << 23) - 1, reserved_bottom_general,
 572                               reserved_top_general);
 573
 574        if (err)
 575                goto free_bitmap;
 576
 577        ++bitmap_initialized;
 578
 579        err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_GENERAL,
 580                                MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO |
 581                                MLX4_ZONE_USE_RR, 0,
 582                                0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_GENERAL);
 583
 584        if (err)
 585                goto free_bitmap;
 586
 587        err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_RSS,
 588                               reserved_bottom_rss,
 589                               reserved_bottom_rss - 1,
 590                               dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 591                               reserved_bottom_rss - start_offset_rss);
 592
 593        if (err)
 594                goto free_bitmap;
 595
 596        ++bitmap_initialized;
 597
 598        err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_RSS,
 599                                MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
 600                                MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
 601                                MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RSS_ETH_PRIORITY,
 602                                0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_RSS);
 603
 604        if (err)
 605                goto free_bitmap;
 606
 607        last_offset = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
 608        /*  We have a single zone for the A0 steering QPs area of the FW. This area
 609         *  needs to be split into subareas. One set of subareas is for RSS QPs
 610         *  (in which qp number bits 6 and/or 7 are set); the other set of subareas
 611         *  is for RAW_ETH QPs, which require that both bits 6 and 7 are zero.
 612         *  Currently, the values returned by the FW (A0 steering area starting qp number
 613         *  and A0 steering area size) are such that there are only two subareas -- one
 614         *  for RSS and one for RAW_ETH.
 615         */
 616        for (k = MLX4_QP_TABLE_ZONE_RSS + 1; k < sizeof(*bitmap)/sizeof((*bitmap)[0]);
 617             k++) {
 618                int size;
 619                u32 offset = start_offset_rss;
 620                u32 bf_mask;
 621                u32 requested_size;
 622
 623                /* Assuming MLX4_BF_QP_SKIP_MASK is consecutive ones, this calculates
 624                 * a mask of all LSB bits set until (and not including) the first
 625                 * set bit of  MLX4_BF_QP_SKIP_MASK. For example, if MLX4_BF_QP_SKIP_MASK
 626                 * is 0xc0, bf_mask will be 0x3f.
 627                 */
 628                bf_mask = (MLX4_BF_QP_SKIP_MASK & ~(MLX4_BF_QP_SKIP_MASK - 1)) - 1;
 629                requested_size = min((u32)MLX4_QP_TABLE_RAW_ETH_SIZE, bf_mask + 1);
 630
 631                if (((last_offset & MLX4_BF_QP_SKIP_MASK) &&
 632                     ((int)(max_table_offset - last_offset)) >=
 633                     roundup_pow_of_two(MLX4_BF_QP_SKIP_MASK)) ||
 634                    (!(last_offset & MLX4_BF_QP_SKIP_MASK) &&
 635                     !((last_offset + requested_size - 1) &
 636                       MLX4_BF_QP_SKIP_MASK)))
 637                        size = requested_size;
 638                else {
 639                        u32 candidate_offset =
 640                                (last_offset | MLX4_BF_QP_SKIP_MASK | bf_mask) + 1;
 641
 642                        if (last_offset & MLX4_BF_QP_SKIP_MASK)
 643                                last_offset = candidate_offset;
 644
 645                        /* From this point, the BF bits are 0 */
 646
 647                        if (last_offset > max_table_offset) {
 648                                /* need to skip */
 649                                size = -1;
 650                        } else {
 651                                size = min3(max_table_offset - last_offset,
 652                                            bf_mask - (last_offset & bf_mask),
 653                                            requested_size);
 654                                if (size < requested_size) {
 655                                        int candidate_size;
 656
 657                                        candidate_size = min3(
 658                                                max_table_offset - candidate_offset,
 659                                                bf_mask - (last_offset & bf_mask),
 660                                                requested_size);
 661
 662                                        /*  We will not take this path if last_offset was
 663                                         *  already set above to candidate_offset
 664                                         */
 665                                        if (candidate_size > size) {
 666                                                last_offset = candidate_offset;
 667                                                size = candidate_size;
 668                                        }
 669                                }
 670                        }
 671                }
 672
 673                if (size > 0) {
 674                        /* mlx4_bitmap_alloc_range will find a contiguous range of "size"
 675                         * QPs in which both bits 6 and 7 are zero, because we pass it the
 676                         * MLX4_BF_SKIP_MASK).
 677                         */
 678                        offset = mlx4_bitmap_alloc_range(
 679                                        *bitmap + MLX4_QP_TABLE_ZONE_RSS,
 680                                        size, 1,
 681                                        MLX4_BF_QP_SKIP_MASK);
 682
 683                        if (offset == (u32)-1) {
 684                                err = -ENOMEM;
 685                                break;
 686                        }
 687
 688                        last_offset = offset + size;
 689
 690                        err = mlx4_bitmap_init(*bitmap + k, roundup_pow_of_two(size),
 691                                               roundup_pow_of_two(size) - 1, 0,
 692                                               roundup_pow_of_two(size) - size);
 693                } else {
 694                        /* Add an empty bitmap, we'll allocate from different zones (since
 695                         * at least one is reserved)
 696                         */
 697                        err = mlx4_bitmap_init(*bitmap + k, 1,
 698                                               MLX4_QP_TABLE_RAW_ETH_SIZE - 1, 0,
 699                                               0);
 700                        mlx4_bitmap_alloc_range(*bitmap + k, 1, 1, 0);
 701                }
 702
 703                if (err)
 704                        break;
 705
 706                ++bitmap_initialized;
 707
 708                err = mlx4_zone_add_one(qp_table->zones, *bitmap + k,
 709                                        MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
 710                                        MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
 711                                        MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RAW_ETH_PRIORITY,
 712                                        offset, qp_table->zones_uids + k);
 713
 714                if (err)
 715                        break;
 716        }
 717
 718        if (err)
 719                goto free_bitmap;
 720
 721        qp_table->bitmap_gen = *bitmap;
 722
 723        return err;
 724
 725free_bitmap:
 726        for (k = 0; k < bitmap_initialized; k++)
 727                mlx4_bitmap_cleanup(*bitmap + k);
 728        kfree(bitmap);
 729free_zone:
 730        mlx4_zone_allocator_destroy(qp_table->zones);
 731        return err;
 732}
 733
 734static void mlx4_cleanup_qp_zones(struct mlx4_dev *dev)
 735{
 736        struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 737
 738        if (qp_table->zones) {
 739                int i;
 740
 741                for (i = 0;
 742                     i < sizeof(qp_table->zones_uids)/sizeof(qp_table->zones_uids[0]);
 743                     i++) {
 744                        struct mlx4_bitmap *bitmap =
 745                                mlx4_zone_get_bitmap(qp_table->zones,
 746                                                     qp_table->zones_uids[i]);
 747
 748                        mlx4_zone_remove_one(qp_table->zones, qp_table->zones_uids[i]);
 749                        if (NULL == bitmap)
 750                                continue;
 751
 752                        mlx4_bitmap_cleanup(bitmap);
 753                }
 754                mlx4_zone_allocator_destroy(qp_table->zones);
 755                kfree(qp_table->bitmap_gen);
 756                qp_table->bitmap_gen = NULL;
 757                qp_table->zones = NULL;
 758        }
 759}
 760
 761int mlx4_init_qp_table(struct mlx4_dev *dev)
 762{
 763        struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
 764        int err;
 765        int reserved_from_top = 0;
 766        int reserved_from_bot;
 767        int k;
 768        int fixed_reserved_from_bot_rv = 0;
 769        int bottom_reserved_for_rss_bitmap;
 770        u32 max_table_offset = dev->caps.dmfs_high_rate_qpn_base +
 771                        dev->caps.dmfs_high_rate_qpn_range;
 772
 773        spin_lock_init(&qp_table->lock);
 774        INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
 775        if (mlx4_is_slave(dev))
 776                return 0;
 777
 778        /* We reserve 2 extra QPs per port for the special QPs.  The
 779         * block of special QPs must be aligned to a multiple of 8, so
 780         * round up.
 781         *
 782         * We also reserve the MSB of the 24-bit QP number to indicate
 783         * that a QP is an XRC QP.
 784         */
 785        for (k = 0; k <= MLX4_QP_REGION_BOTTOM; k++)
 786                fixed_reserved_from_bot_rv += dev->caps.reserved_qps_cnt[k];
 787
 788        if (fixed_reserved_from_bot_rv < max_table_offset)
 789                fixed_reserved_from_bot_rv = max_table_offset;
 790
 791        /* We reserve at least 1 extra for bitmaps that we don't have enough space for*/
 792        bottom_reserved_for_rss_bitmap =
 793                roundup_pow_of_two(fixed_reserved_from_bot_rv + 1);
 794        dev->phys_caps.base_sqpn = ALIGN(bottom_reserved_for_rss_bitmap, 8);
 795
 796        {
 797                int sort[MLX4_NUM_QP_REGION];
 798                int i, j;
 799                int last_base = dev->caps.num_qps;
 800
 801                for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
 802                        sort[i] = i;
 803
 804                for (i = MLX4_NUM_QP_REGION; i > MLX4_QP_REGION_BOTTOM; --i) {
 805                        for (j = MLX4_QP_REGION_BOTTOM + 2; j < i; ++j) {
 806                                if (dev->caps.reserved_qps_cnt[sort[j]] >
 807                                    dev->caps.reserved_qps_cnt[sort[j - 1]])
 808                                        swap(sort[j], sort[j - 1]);
 809                        }
 810                }
 811
 812                for (i = MLX4_QP_REGION_BOTTOM + 1; i < MLX4_NUM_QP_REGION; ++i) {
 813                        last_base -= dev->caps.reserved_qps_cnt[sort[i]];
 814                        dev->caps.reserved_qps_base[sort[i]] = last_base;
 815                        reserved_from_top +=
 816                                dev->caps.reserved_qps_cnt[sort[i]];
 817                }
 818        }
 819
 820       /* Reserve 8 real SQPs in both native and SRIOV modes.
 821        * In addition, in SRIOV mode, reserve 8 proxy SQPs per function
 822        * (for all PFs and VFs), and 8 corresponding tunnel QPs.
 823        * Each proxy SQP works opposite its own tunnel QP.
 824        *
 825        * The QPs are arranged as follows:
 826        * a. 8 real SQPs
 827        * b. All the proxy SQPs (8 per function)
 828        * c. All the tunnel QPs (8 per function)
 829        */
 830        reserved_from_bot = mlx4_num_reserved_sqps(dev);
 831        if (reserved_from_bot + reserved_from_top > dev->caps.num_qps) {
 832                mlx4_err(dev, "Number of reserved QPs is higher than number of QPs\n");
 833                return -EINVAL;
 834        }
 835
 836        err = mlx4_create_zones(dev, reserved_from_bot, reserved_from_bot,
 837                                bottom_reserved_for_rss_bitmap,
 838                                fixed_reserved_from_bot_rv,
 839                                max_table_offset);
 840
 841        if (err)
 842                return err;
 843
 844        if (mlx4_is_mfunc(dev)) {
 845                /* for PPF use */
 846                dev->phys_caps.base_proxy_sqpn = dev->phys_caps.base_sqpn + 8;
 847                dev->phys_caps.base_tunnel_sqpn = dev->phys_caps.base_sqpn + 8 + 8 * MLX4_MFUNC_MAX;
 848
 849                /* In mfunc, calculate proxy and tunnel qp offsets for the PF here,
 850                 * since the PF does not call mlx4_slave_caps */
 851                dev->caps.spec_qps = kcalloc(dev->caps.num_ports,
 852                                             sizeof(*dev->caps.spec_qps),
 853                                             GFP_KERNEL);
 854                if (!dev->caps.spec_qps) {
 855                        err = -ENOMEM;
 856                        goto err_mem;
 857                }
 858
 859                for (k = 0; k < dev->caps.num_ports; k++) {
 860                        dev->caps.spec_qps[k].qp0_proxy = dev->phys_caps.base_proxy_sqpn +
 861                                8 * mlx4_master_func_num(dev) + k;
 862                        dev->caps.spec_qps[k].qp0_tunnel = dev->caps.spec_qps[k].qp0_proxy + 8 * MLX4_MFUNC_MAX;
 863                        dev->caps.spec_qps[k].qp1_proxy = dev->phys_caps.base_proxy_sqpn +
 864                                8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k;
 865                        dev->caps.spec_qps[k].qp1_tunnel = dev->caps.spec_qps[k].qp1_proxy + 8 * MLX4_MFUNC_MAX;
 866                }
 867        }
 868
 869
 870        err = mlx4_CONF_SPECIAL_QP(dev, dev->phys_caps.base_sqpn);
 871        if (err)
 872                goto err_mem;
 873
 874        return err;
 875
 876err_mem:
 877        kfree(dev->caps.spec_qps);
 878        dev->caps.spec_qps = NULL;
 879        mlx4_cleanup_qp_zones(dev);
 880        return err;
 881}
 882
 883void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
 884{
 885        if (mlx4_is_slave(dev))
 886                return;
 887
 888        mlx4_CONF_SPECIAL_QP(dev, 0);
 889
 890        mlx4_cleanup_qp_zones(dev);
 891}
 892
 893int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
 894                  struct mlx4_qp_context *context)
 895{
 896        struct mlx4_cmd_mailbox *mailbox;
 897        int err;
 898
 899        mailbox = mlx4_alloc_cmd_mailbox(dev);
 900        if (IS_ERR(mailbox))
 901                return PTR_ERR(mailbox);
 902
 903        err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
 904                           MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
 905                           MLX4_CMD_WRAPPED);
 906        if (!err)
 907                memcpy(context, mailbox->buf + 8, sizeof(*context));
 908
 909        mlx4_free_cmd_mailbox(dev, mailbox);
 910        return err;
 911}
 912EXPORT_SYMBOL_GPL(mlx4_qp_query);
 913
 914int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 915                     struct mlx4_qp_context *context,
 916                     struct mlx4_qp *qp, enum mlx4_qp_state *qp_state)
 917{
 918        int err;
 919        int i;
 920        enum mlx4_qp_state states[] = {
 921                MLX4_QP_STATE_RST,
 922                MLX4_QP_STATE_INIT,
 923                MLX4_QP_STATE_RTR,
 924                MLX4_QP_STATE_RTS
 925        };
 926
 927        for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
 928                context->flags &= cpu_to_be32(~(0xf << 28));
 929                context->flags |= cpu_to_be32(states[i + 1] << 28);
 930                if (states[i + 1] != MLX4_QP_STATE_RTR)
 931                        context->params2 &= ~cpu_to_be32(MLX4_QP_BIT_FPP);
 932                err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
 933                                     context, 0, 0, qp);
 934                if (err) {
 935                        mlx4_err(dev, "Failed to bring QP to state: %d with error: %d\n",
 936                                 states[i + 1], err);
 937                        return err;
 938                }
 939
 940                *qp_state = states[i + 1];
 941        }
 942
 943        return 0;
 944}
 945EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);
 946
 947u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn)
 948{
 949        struct mlx4_qp_context context;
 950        struct mlx4_qp qp;
 951        int err;
 952
 953        qp.qpn = qpn;
 954        err = mlx4_qp_query(dev, &qp, &context);
 955        if (!err) {
 956                u32 dest_qpn = be32_to_cpu(context.remote_qpn) & 0xffffff;
 957                u16 folded_dst = folded_qp(dest_qpn);
 958                u16 folded_src = folded_qp(qpn);
 959
 960                return (dest_qpn != qpn) ?
 961                        ((folded_dst ^ folded_src) | 0xC000) :
 962                        folded_src | 0xC000;
 963        }
 964        return 0xdead;
 965}
 966