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14#include <linux/stmmac.h>
15#include "common.h"
16#include "dwmac4_descs.h"
17
18static int dwmac4_wrback_get_tx_status(void *data, struct stmmac_extra_stats *x,
19 struct dma_desc *p,
20 void __iomem *ioaddr)
21{
22 struct net_device_stats *stats = (struct net_device_stats *)data;
23 unsigned int tdes3;
24 int ret = tx_done;
25
26 tdes3 = le32_to_cpu(p->des3);
27
28
29 if (unlikely(tdes3 & TDES3_OWN))
30 return tx_dma_own;
31
32
33 if (likely(!(tdes3 & TDES3_LAST_DESCRIPTOR)))
34 return tx_not_ls;
35
36 if (unlikely(tdes3 & TDES3_ERROR_SUMMARY)) {
37 if (unlikely(tdes3 & TDES3_JABBER_TIMEOUT))
38 x->tx_jabber++;
39 if (unlikely(tdes3 & TDES3_PACKET_FLUSHED))
40 x->tx_frame_flushed++;
41 if (unlikely(tdes3 & TDES3_LOSS_CARRIER)) {
42 x->tx_losscarrier++;
43 stats->tx_carrier_errors++;
44 }
45 if (unlikely(tdes3 & TDES3_NO_CARRIER)) {
46 x->tx_carrier++;
47 stats->tx_carrier_errors++;
48 }
49 if (unlikely((tdes3 & TDES3_LATE_COLLISION) ||
50 (tdes3 & TDES3_EXCESSIVE_COLLISION)))
51 stats->collisions +=
52 (tdes3 & TDES3_COLLISION_COUNT_MASK)
53 >> TDES3_COLLISION_COUNT_SHIFT;
54
55 if (unlikely(tdes3 & TDES3_EXCESSIVE_DEFERRAL))
56 x->tx_deferred++;
57
58 if (unlikely(tdes3 & TDES3_UNDERFLOW_ERROR))
59 x->tx_underflow++;
60
61 if (unlikely(tdes3 & TDES3_IP_HDR_ERROR))
62 x->tx_ip_header_error++;
63
64 if (unlikely(tdes3 & TDES3_PAYLOAD_ERROR))
65 x->tx_payload_error++;
66
67 ret = tx_err;
68 }
69
70 if (unlikely(tdes3 & TDES3_DEFERRED))
71 x->tx_deferred++;
72
73 return ret;
74}
75
76static int dwmac4_wrback_get_rx_status(void *data, struct stmmac_extra_stats *x,
77 struct dma_desc *p)
78{
79 struct net_device_stats *stats = (struct net_device_stats *)data;
80 unsigned int rdes1 = le32_to_cpu(p->des1);
81 unsigned int rdes2 = le32_to_cpu(p->des2);
82 unsigned int rdes3 = le32_to_cpu(p->des3);
83 int message_type;
84 int ret = good_frame;
85
86 if (unlikely(rdes3 & RDES3_OWN))
87 return dma_own;
88
89
90 if (likely(!(rdes3 & RDES3_LAST_DESCRIPTOR)))
91 return discard_frame;
92
93 if (unlikely(rdes3 & RDES3_ERROR_SUMMARY)) {
94 if (unlikely(rdes3 & RDES3_GIANT_PACKET))
95 stats->rx_length_errors++;
96 if (unlikely(rdes3 & RDES3_OVERFLOW_ERROR))
97 x->rx_gmac_overflow++;
98
99 if (unlikely(rdes3 & RDES3_RECEIVE_WATCHDOG))
100 x->rx_watchdog++;
101
102 if (unlikely(rdes3 & RDES3_RECEIVE_ERROR))
103 x->rx_mii++;
104
105 if (unlikely(rdes3 & RDES3_CRC_ERROR)) {
106 x->rx_crc_errors++;
107 stats->rx_crc_errors++;
108 }
109
110 if (unlikely(rdes3 & RDES3_DRIBBLE_ERROR))
111 x->dribbling_bit++;
112
113 ret = discard_frame;
114 }
115
116 message_type = (rdes1 & ERDES4_MSG_TYPE_MASK) >> 8;
117
118 if (rdes1 & RDES1_IP_HDR_ERROR)
119 x->ip_hdr_err++;
120 if (rdes1 & RDES1_IP_CSUM_BYPASSED)
121 x->ip_csum_bypassed++;
122 if (rdes1 & RDES1_IPV4_HEADER)
123 x->ipv4_pkt_rcvd++;
124 if (rdes1 & RDES1_IPV6_HEADER)
125 x->ipv6_pkt_rcvd++;
126
127 if (message_type == RDES_EXT_NO_PTP)
128 x->no_ptp_rx_msg_type_ext++;
129 else if (message_type == RDES_EXT_SYNC)
130 x->ptp_rx_msg_type_sync++;
131 else if (message_type == RDES_EXT_FOLLOW_UP)
132 x->ptp_rx_msg_type_follow_up++;
133 else if (message_type == RDES_EXT_DELAY_REQ)
134 x->ptp_rx_msg_type_delay_req++;
135 else if (message_type == RDES_EXT_DELAY_RESP)
136 x->ptp_rx_msg_type_delay_resp++;
137 else if (message_type == RDES_EXT_PDELAY_REQ)
138 x->ptp_rx_msg_type_pdelay_req++;
139 else if (message_type == RDES_EXT_PDELAY_RESP)
140 x->ptp_rx_msg_type_pdelay_resp++;
141 else if (message_type == RDES_EXT_PDELAY_FOLLOW_UP)
142 x->ptp_rx_msg_type_pdelay_follow_up++;
143 else if (message_type == RDES_PTP_ANNOUNCE)
144 x->ptp_rx_msg_type_announce++;
145 else if (message_type == RDES_PTP_MANAGEMENT)
146 x->ptp_rx_msg_type_management++;
147 else if (message_type == RDES_PTP_PKT_RESERVED_TYPE)
148 x->ptp_rx_msg_pkt_reserved_type++;
149
150 if (rdes1 & RDES1_PTP_PACKET_TYPE)
151 x->ptp_frame_type++;
152 if (rdes1 & RDES1_PTP_VER)
153 x->ptp_ver++;
154 if (rdes1 & RDES1_TIMESTAMP_DROPPED)
155 x->timestamp_dropped++;
156
157 if (unlikely(rdes2 & RDES2_SA_FILTER_FAIL)) {
158 x->sa_rx_filter_fail++;
159 ret = discard_frame;
160 }
161 if (unlikely(rdes2 & RDES2_DA_FILTER_FAIL)) {
162 x->da_rx_filter_fail++;
163 ret = discard_frame;
164 }
165
166 if (rdes2 & RDES2_L3_FILTER_MATCH)
167 x->l3_filter_match++;
168 if (rdes2 & RDES2_L4_FILTER_MATCH)
169 x->l4_filter_match++;
170 if ((rdes2 & RDES2_L3_L4_FILT_NB_MATCH_MASK)
171 >> RDES2_L3_L4_FILT_NB_MATCH_SHIFT)
172 x->l3_l4_filter_no_match++;
173
174 return ret;
175}
176
177static int dwmac4_rd_get_tx_len(struct dma_desc *p)
178{
179 return (le32_to_cpu(p->des2) & TDES2_BUFFER1_SIZE_MASK);
180}
181
182static int dwmac4_get_tx_owner(struct dma_desc *p)
183{
184 return (le32_to_cpu(p->des3) & TDES3_OWN) >> TDES3_OWN_SHIFT;
185}
186
187static void dwmac4_set_tx_owner(struct dma_desc *p)
188{
189 p->des3 |= cpu_to_le32(TDES3_OWN);
190}
191
192static void dwmac4_set_rx_owner(struct dma_desc *p)
193{
194 p->des3 |= cpu_to_le32(RDES3_OWN);
195}
196
197static int dwmac4_get_tx_ls(struct dma_desc *p)
198{
199 return (le32_to_cpu(p->des3) & TDES3_LAST_DESCRIPTOR)
200 >> TDES3_LAST_DESCRIPTOR_SHIFT;
201}
202
203static int dwmac4_wrback_get_rx_frame_len(struct dma_desc *p, int rx_coe)
204{
205 return (le32_to_cpu(p->des3) & RDES3_PACKET_SIZE_MASK);
206}
207
208static void dwmac4_rd_enable_tx_timestamp(struct dma_desc *p)
209{
210 p->des2 |= cpu_to_le32(TDES2_TIMESTAMP_ENABLE);
211}
212
213static int dwmac4_wrback_get_tx_timestamp_status(struct dma_desc *p)
214{
215
216 if (le32_to_cpu(p->des3) & TDES3_CONTEXT_TYPE)
217 return 0;
218
219
220 if (le32_to_cpu(p->des3) & TDES3_TIMESTAMP_STATUS)
221 return 1;
222
223 return 0;
224}
225
226static inline u64 dwmac4_get_timestamp(void *desc, u32 ats)
227{
228 struct dma_desc *p = (struct dma_desc *)desc;
229 u64 ns;
230
231 ns = le32_to_cpu(p->des0);
232
233 ns += le32_to_cpu(p->des1) * 1000000000ULL;
234
235 return ns;
236}
237
238static int dwmac4_rx_check_timestamp(void *desc)
239{
240 struct dma_desc *p = (struct dma_desc *)desc;
241 u32 own, ctxt;
242 int ret = 1;
243
244 own = p->des3 & RDES3_OWN;
245 ctxt = ((p->des3 & RDES3_CONTEXT_DESCRIPTOR)
246 >> RDES3_CONTEXT_DESCRIPTOR_SHIFT);
247
248 if (likely(!own && ctxt)) {
249 if ((p->des0 == 0xffffffff) && (p->des1 == 0xffffffff))
250
251 ret = -EINVAL;
252 else
253
254 ret = 0;
255 }
256
257
258 return ret;
259}
260
261static int dwmac4_wrback_get_rx_timestamp_status(void *desc, void *next_desc,
262 u32 ats)
263{
264 struct dma_desc *p = (struct dma_desc *)desc;
265 int ret = -EINVAL;
266
267
268 if (likely(p->des3 & TDES3_RS1V)) {
269 if (likely(le32_to_cpu(p->des1) & RDES1_TIMESTAMP_AVAILABLE)) {
270 int i = 0;
271
272
273 do {
274 ret = dwmac4_rx_check_timestamp(next_desc);
275 if (ret < 0)
276 goto exit;
277 i++;
278
279 } while ((ret == 1) && (i < 10));
280
281 if (i == 10)
282 ret = -EBUSY;
283 }
284 }
285exit:
286 if (likely(ret == 0))
287 return 1;
288
289 return 0;
290}
291
292static void dwmac4_rd_init_rx_desc(struct dma_desc *p, int disable_rx_ic,
293 int mode, int end)
294{
295 p->des3 = cpu_to_le32(RDES3_OWN | RDES3_BUFFER1_VALID_ADDR);
296
297 if (!disable_rx_ic)
298 p->des3 |= cpu_to_le32(RDES3_INT_ON_COMPLETION_EN);
299}
300
301static void dwmac4_rd_init_tx_desc(struct dma_desc *p, int mode, int end)
302{
303 p->des0 = 0;
304 p->des1 = 0;
305 p->des2 = 0;
306 p->des3 = 0;
307}
308
309static void dwmac4_rd_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
310 bool csum_flag, int mode, bool tx_own,
311 bool ls, unsigned int tot_pkt_len)
312{
313 unsigned int tdes3 = le32_to_cpu(p->des3);
314
315 p->des2 |= cpu_to_le32(len & TDES2_BUFFER1_SIZE_MASK);
316
317 tdes3 |= tot_pkt_len & TDES3_PACKET_SIZE_MASK;
318 if (is_fs)
319 tdes3 |= TDES3_FIRST_DESCRIPTOR;
320 else
321 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
322
323 if (likely(csum_flag))
324 tdes3 |= (TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
325 else
326 tdes3 &= ~(TX_CIC_FULL << TDES3_CHECKSUM_INSERTION_SHIFT);
327
328 if (ls)
329 tdes3 |= TDES3_LAST_DESCRIPTOR;
330 else
331 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
332
333
334 if (tx_own)
335 tdes3 |= TDES3_OWN;
336
337 if (is_fs && tx_own)
338
339
340
341
342 dma_wmb();
343
344 p->des3 = cpu_to_le32(tdes3);
345}
346
347static void dwmac4_rd_prepare_tso_tx_desc(struct dma_desc *p, int is_fs,
348 int len1, int len2, bool tx_own,
349 bool ls, unsigned int tcphdrlen,
350 unsigned int tcppayloadlen)
351{
352 unsigned int tdes3 = le32_to_cpu(p->des3);
353
354 if (len1)
355 p->des2 |= cpu_to_le32((len1 & TDES2_BUFFER1_SIZE_MASK));
356
357 if (len2)
358 p->des2 |= cpu_to_le32((len2 << TDES2_BUFFER2_SIZE_MASK_SHIFT)
359 & TDES2_BUFFER2_SIZE_MASK);
360
361 if (is_fs) {
362 tdes3 |= TDES3_FIRST_DESCRIPTOR |
363 TDES3_TCP_SEGMENTATION_ENABLE |
364 ((tcphdrlen << TDES3_HDR_LEN_SHIFT) &
365 TDES3_SLOT_NUMBER_MASK) |
366 ((tcppayloadlen & TDES3_TCP_PKT_PAYLOAD_MASK));
367 } else {
368 tdes3 &= ~TDES3_FIRST_DESCRIPTOR;
369 }
370
371 if (ls)
372 tdes3 |= TDES3_LAST_DESCRIPTOR;
373 else
374 tdes3 &= ~TDES3_LAST_DESCRIPTOR;
375
376
377 if (tx_own)
378 tdes3 |= TDES3_OWN;
379
380 if (is_fs && tx_own)
381
382
383
384
385 dma_wmb();
386
387 p->des3 = cpu_to_le32(tdes3);
388}
389
390static void dwmac4_release_tx_desc(struct dma_desc *p, int mode)
391{
392 p->des2 = 0;
393 p->des3 = 0;
394}
395
396static void dwmac4_rd_set_tx_ic(struct dma_desc *p)
397{
398 p->des2 |= cpu_to_le32(TDES2_INTERRUPT_ON_COMPLETION);
399}
400
401static void dwmac4_display_ring(void *head, unsigned int size, bool rx)
402{
403 struct dma_desc *p = (struct dma_desc *)head;
404 int i;
405
406 pr_info("%s descriptor ring:\n", rx ? "RX" : "TX");
407
408 for (i = 0; i < size; i++) {
409 pr_info("%03d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
410 i, (unsigned int)virt_to_phys(p),
411 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
412 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
413 p++;
414 }
415}
416
417static void dwmac4_set_mss_ctxt(struct dma_desc *p, unsigned int mss)
418{
419 p->des0 = 0;
420 p->des1 = 0;
421 p->des2 = cpu_to_le32(mss);
422 p->des3 = cpu_to_le32(TDES3_CONTEXT_TYPE | TDES3_CTXT_TCMSSV);
423}
424
425const struct stmmac_desc_ops dwmac4_desc_ops = {
426 .tx_status = dwmac4_wrback_get_tx_status,
427 .rx_status = dwmac4_wrback_get_rx_status,
428 .get_tx_len = dwmac4_rd_get_tx_len,
429 .get_tx_owner = dwmac4_get_tx_owner,
430 .set_tx_owner = dwmac4_set_tx_owner,
431 .set_rx_owner = dwmac4_set_rx_owner,
432 .get_tx_ls = dwmac4_get_tx_ls,
433 .get_rx_frame_len = dwmac4_wrback_get_rx_frame_len,
434 .enable_tx_timestamp = dwmac4_rd_enable_tx_timestamp,
435 .get_tx_timestamp_status = dwmac4_wrback_get_tx_timestamp_status,
436 .get_rx_timestamp_status = dwmac4_wrback_get_rx_timestamp_status,
437 .get_timestamp = dwmac4_get_timestamp,
438 .set_tx_ic = dwmac4_rd_set_tx_ic,
439 .prepare_tx_desc = dwmac4_rd_prepare_tx_desc,
440 .prepare_tso_tx_desc = dwmac4_rd_prepare_tso_tx_desc,
441 .release_tx_desc = dwmac4_release_tx_desc,
442 .init_rx_desc = dwmac4_rd_init_rx_desc,
443 .init_tx_desc = dwmac4_rd_init_tx_desc,
444 .display_ring = dwmac4_display_ring,
445 .set_mss = dwmac4_set_mss_ctxt,
446};
447
448const struct stmmac_mode_ops dwmac4_ring_mode_ops = { };
449
