linux/drivers/net/wireless/ath/ath10k/bmi.h
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   1/*
   2 * Copyright (c) 2005-2011 Atheros Communications Inc.
   3 * Copyright (c) 2011-2015,2017 Qualcomm Atheros, Inc.
   4 *
   5 * Permission to use, copy, modify, and/or distribute this software for any
   6 * purpose with or without fee is hereby granted, provided that the above
   7 * copyright notice and this permission notice appear in all copies.
   8 *
   9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16 */
  17
  18#ifndef _BMI_H_
  19#define _BMI_H_
  20
  21#include "core.h"
  22
  23/*
  24 * Bootloader Messaging Interface (BMI)
  25 *
  26 * BMI is a very simple messaging interface used during initialization
  27 * to read memory, write memory, execute code, and to define an
  28 * application entry PC.
  29 *
  30 * It is used to download an application to QCA988x, to provide
  31 * patches to code that is already resident on QCA988x, and generally
  32 * to examine and modify state.  The Host has an opportunity to use
  33 * BMI only once during bootup.  Once the Host issues a BMI_DONE
  34 * command, this opportunity ends.
  35 *
  36 * The Host writes BMI requests to mailbox0, and reads BMI responses
  37 * from mailbox0.   BMI requests all begin with a command
  38 * (see below for specific commands), and are followed by
  39 * command-specific data.
  40 *
  41 * Flow control:
  42 * The Host can only issue a command once the Target gives it a
  43 * "BMI Command Credit", using AR8K Counter #4.  As soon as the
  44 * Target has completed a command, it issues another BMI Command
  45 * Credit (so the Host can issue the next command).
  46 *
  47 * BMI handles all required Target-side cache flushing.
  48 */
  49
  50/* Maximum data size used for BMI transfers */
  51#define BMI_MAX_DATA_SIZE       256
  52
  53/* len = cmd + addr + length */
  54#define BMI_MAX_CMDBUF_SIZE (BMI_MAX_DATA_SIZE + \
  55                        sizeof(u32) + \
  56                        sizeof(u32) + \
  57                        sizeof(u32))
  58
  59/* BMI Commands */
  60
  61enum bmi_cmd_id {
  62        BMI_NO_COMMAND          = 0,
  63        BMI_DONE                = 1,
  64        BMI_READ_MEMORY         = 2,
  65        BMI_WRITE_MEMORY        = 3,
  66        BMI_EXECUTE             = 4,
  67        BMI_SET_APP_START       = 5,
  68        BMI_READ_SOC_REGISTER   = 6,
  69        BMI_READ_SOC_WORD       = 6,
  70        BMI_WRITE_SOC_REGISTER  = 7,
  71        BMI_WRITE_SOC_WORD      = 7,
  72        BMI_GET_TARGET_ID       = 8,
  73        BMI_GET_TARGET_INFO     = 8,
  74        BMI_ROMPATCH_INSTALL    = 9,
  75        BMI_ROMPATCH_UNINSTALL  = 10,
  76        BMI_ROMPATCH_ACTIVATE   = 11,
  77        BMI_ROMPATCH_DEACTIVATE = 12,
  78        BMI_LZ_STREAM_START     = 13, /* should be followed by LZ_DATA */
  79        BMI_LZ_DATA             = 14,
  80        BMI_NVRAM_PROCESS       = 15,
  81};
  82
  83#define BMI_NVRAM_SEG_NAME_SZ 16
  84
  85#define BMI_PARAM_GET_EEPROM_BOARD_ID 0x10
  86#define BMI_PARAM_GET_FLASH_BOARD_ID 0x8000
  87#define BMI_PARAM_FLASH_SECTION_ALL 0x10000
  88
  89#define ATH10K_BMI_BOARD_ID_FROM_OTP_MASK   0x7c00
  90#define ATH10K_BMI_BOARD_ID_FROM_OTP_LSB    10
  91
  92#define ATH10K_BMI_CHIP_ID_FROM_OTP_MASK    0x18000
  93#define ATH10K_BMI_CHIP_ID_FROM_OTP_LSB     15
  94
  95#define ATH10K_BMI_BOARD_ID_STATUS_MASK 0xff
  96
  97struct bmi_cmd {
  98        __le32 id; /* enum bmi_cmd_id */
  99        union {
 100                struct {
 101                } done;
 102                struct {
 103                        __le32 addr;
 104                        __le32 len;
 105                } read_mem;
 106                struct {
 107                        __le32 addr;
 108                        __le32 len;
 109                        u8 payload[0];
 110                } write_mem;
 111                struct {
 112                        __le32 addr;
 113                        __le32 param;
 114                } execute;
 115                struct {
 116                        __le32 addr;
 117                } set_app_start;
 118                struct {
 119                        __le32 addr;
 120                } read_soc_reg;
 121                struct {
 122                        __le32 addr;
 123                        __le32 value;
 124                } write_soc_reg;
 125                struct {
 126                } get_target_info;
 127                struct {
 128                        __le32 rom_addr;
 129                        __le32 ram_addr; /* or value */
 130                        __le32 size;
 131                        __le32 activate; /* 0=install, but dont activate */
 132                } rompatch_install;
 133                struct {
 134                        __le32 patch_id;
 135                } rompatch_uninstall;
 136                struct {
 137                        __le32 count;
 138                        __le32 patch_ids[0]; /* length of @count */
 139                } rompatch_activate;
 140                struct {
 141                        __le32 count;
 142                        __le32 patch_ids[0]; /* length of @count */
 143                } rompatch_deactivate;
 144                struct {
 145                        __le32 addr;
 146                } lz_start;
 147                struct {
 148                        __le32 len; /* max BMI_MAX_DATA_SIZE */
 149                        u8 payload[0]; /* length of @len */
 150                } lz_data;
 151                struct {
 152                        u8 name[BMI_NVRAM_SEG_NAME_SZ];
 153                } nvram_process;
 154                u8 payload[BMI_MAX_CMDBUF_SIZE];
 155        };
 156} __packed;
 157
 158union bmi_resp {
 159        struct {
 160                u8 payload[0];
 161        } read_mem;
 162        struct {
 163                __le32 result;
 164        } execute;
 165        struct {
 166                __le32 value;
 167        } read_soc_reg;
 168        struct {
 169                __le32 len;
 170                __le32 version;
 171                __le32 type;
 172        } get_target_info;
 173        struct {
 174                __le32 patch_id;
 175        } rompatch_install;
 176        struct {
 177                __le32 patch_id;
 178        } rompatch_uninstall;
 179        struct {
 180                /* 0 = nothing executed
 181                 * otherwise = NVRAM segment return value
 182                 */
 183                __le32 result;
 184        } nvram_process;
 185        u8 payload[BMI_MAX_CMDBUF_SIZE];
 186} __packed;
 187
 188struct bmi_target_info {
 189        u32 version;
 190        u32 type;
 191};
 192
 193/* in jiffies */
 194#define BMI_COMMUNICATION_TIMEOUT_HZ (3 * HZ)
 195
 196#define BMI_CE_NUM_TO_TARG 0
 197#define BMI_CE_NUM_TO_HOST 1
 198
 199void ath10k_bmi_start(struct ath10k *ar);
 200int ath10k_bmi_done(struct ath10k *ar);
 201int ath10k_bmi_get_target_info(struct ath10k *ar,
 202                               struct bmi_target_info *target_info);
 203int ath10k_bmi_get_target_info_sdio(struct ath10k *ar,
 204                                    struct bmi_target_info *target_info);
 205int ath10k_bmi_read_memory(struct ath10k *ar, u32 address,
 206                           void *buffer, u32 length);
 207int ath10k_bmi_write_memory(struct ath10k *ar, u32 address,
 208                            const void *buffer, u32 length);
 209
 210#define ath10k_bmi_read32(ar, item, val)                                \
 211        ({                                                              \
 212                int ret;                                                \
 213                u32 addr;                                               \
 214                __le32 tmp;                                             \
 215                                                                        \
 216                addr = host_interest_item_address(HI_ITEM(item));       \
 217                ret = ath10k_bmi_read_memory(ar, addr, (u8 *)&tmp, 4); \
 218                if (!ret)                                               \
 219                        *val = __le32_to_cpu(tmp);                      \
 220                ret;                                                    \
 221         })
 222
 223#define ath10k_bmi_write32(ar, item, val)                               \
 224        ({                                                              \
 225                int ret;                                                \
 226                u32 address;                                            \
 227                __le32 v = __cpu_to_le32(val);                          \
 228                                                                        \
 229                address = host_interest_item_address(HI_ITEM(item));    \
 230                ret = ath10k_bmi_write_memory(ar, address,              \
 231                                              (u8 *)&v, sizeof(v));     \
 232                ret;                                                    \
 233        })
 234
 235int ath10k_bmi_execute(struct ath10k *ar, u32 address, u32 param, u32 *result);
 236int ath10k_bmi_lz_stream_start(struct ath10k *ar, u32 address);
 237int ath10k_bmi_lz_data(struct ath10k *ar, const void *buffer, u32 length);
 238int ath10k_bmi_fast_download(struct ath10k *ar, u32 address,
 239                             const void *buffer, u32 length);
 240int ath10k_bmi_read_soc_reg(struct ath10k *ar, u32 address, u32 *reg_val);
 241int ath10k_bmi_write_soc_reg(struct ath10k *ar, u32 address, u32 reg_val);
 242#endif /* _BMI_H_ */
 243