1/* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19/* 20 Module: rt2400pci 21 Abstract: Data structures and registers for the rt2400pci module. 22 Supported chipsets: RT2460. 23 */ 24 25#ifndef RT2400PCI_H 26#define RT2400PCI_H 27 28/* 29 * RF chip defines. 30 */ 31#define RF2420 0x0000 32#define RF2421 0x0001 33 34/* 35 * Signal information. 36 * Default offset is required for RSSI <-> dBm conversion. 37 */ 38#define DEFAULT_RSSI_OFFSET 100 39 40/* 41 * Register layout information. 42 */ 43#define CSR_REG_BASE 0x0000 44#define CSR_REG_SIZE 0x014c 45#define EEPROM_BASE 0x0000 46#define EEPROM_SIZE 0x0100 47#define BBP_BASE 0x0000 48#define BBP_SIZE 0x0020 49#define RF_BASE 0x0004 50#define RF_SIZE 0x000c 51 52/* 53 * Number of TX queues. 54 */ 55#define NUM_TX_QUEUES 2 56 57/* 58 * Control/Status Registers(CSR). 59 * Some values are set in TU, whereas 1 TU == 1024 us. 60 */ 61 62/* 63 * CSR0: ASIC revision number. 64 */ 65#define CSR0 0x0000 66#define CSR0_REVISION FIELD32(0x0000ffff) 67 68/* 69 * CSR1: System control register. 70 * SOFT_RESET: Software reset, 1: reset, 0: normal. 71 * BBP_RESET: Hardware reset, 1: reset, 0, release. 72 * HOST_READY: Host ready after initialization. 73 */ 74#define CSR1 0x0004 75#define CSR1_SOFT_RESET FIELD32(0x00000001) 76#define CSR1_BBP_RESET FIELD32(0x00000002) 77#define CSR1_HOST_READY FIELD32(0x00000004) 78 79/* 80 * CSR2: System admin status register (invalid). 81 */ 82#define CSR2 0x0008 83 84/* 85 * CSR3: STA MAC address register 0. 86 */ 87#define CSR3 0x000c 88#define CSR3_BYTE0 FIELD32(0x000000ff) 89#define CSR3_BYTE1 FIELD32(0x0000ff00) 90#define CSR3_BYTE2 FIELD32(0x00ff0000) 91#define CSR3_BYTE3 FIELD32(0xff000000) 92 93/* 94 * CSR4: STA MAC address register 1. 95 */ 96#define CSR4 0x0010 97#define CSR4_BYTE4 FIELD32(0x000000ff) 98#define CSR4_BYTE5 FIELD32(0x0000ff00) 99 100/* 101 * CSR5: BSSID register 0. 102 */ 103#define CSR5 0x0014 104#define CSR5_BYTE0 FIELD32(0x000000ff) 105#define CSR5_BYTE1 FIELD32(0x0000ff00) 106#define CSR5_BYTE2 FIELD32(0x00ff0000) 107#define CSR5_BYTE3 FIELD32(0xff000000) 108 109/* 110 * CSR6: BSSID register 1. 111 */ 112#define CSR6 0x0018 113#define CSR6_BYTE4 FIELD32(0x000000ff) 114#define CSR6_BYTE5 FIELD32(0x0000ff00) 115 116/* 117 * CSR7: Interrupt source register. 118 * Write 1 to clear interrupt. 119 * TBCN_EXPIRE: Beacon timer expired interrupt. 120 * TWAKE_EXPIRE: Wakeup timer expired interrupt. 121 * TATIMW_EXPIRE: Timer of atim window expired interrupt. 122 * TXDONE_TXRING: Tx ring transmit done interrupt. 123 * TXDONE_ATIMRING: Atim ring transmit done interrupt. 124 * TXDONE_PRIORING: Priority ring transmit done interrupt. 125 * RXDONE: Receive done interrupt. 126 */ 127#define CSR7 0x001c 128#define CSR7_TBCN_EXPIRE FIELD32(0x00000001) 129#define CSR7_TWAKE_EXPIRE FIELD32(0x00000002) 130#define CSR7_TATIMW_EXPIRE FIELD32(0x00000004) 131#define CSR7_TXDONE_TXRING FIELD32(0x00000008) 132#define CSR7_TXDONE_ATIMRING FIELD32(0x00000010) 133#define CSR7_TXDONE_PRIORING FIELD32(0x00000020) 134#define CSR7_RXDONE FIELD32(0x00000040) 135 136/* 137 * CSR8: Interrupt mask register. 138 * Write 1 to mask interrupt. 139 * TBCN_EXPIRE: Beacon timer expired interrupt. 140 * TWAKE_EXPIRE: Wakeup timer expired interrupt. 141 * TATIMW_EXPIRE: Timer of atim window expired interrupt. 142 * TXDONE_TXRING: Tx ring transmit done interrupt. 143 * TXDONE_ATIMRING: Atim ring transmit done interrupt. 144 * TXDONE_PRIORING: Priority ring transmit done interrupt. 145 * RXDONE: Receive done interrupt. 146 */ 147#define CSR8 0x0020 148#define CSR8_TBCN_EXPIRE FIELD32(0x00000001) 149#define CSR8_TWAKE_EXPIRE FIELD32(0x00000002) 150#define CSR8_TATIMW_EXPIRE FIELD32(0x00000004) 151#define CSR8_TXDONE_TXRING FIELD32(0x00000008) 152#define CSR8_TXDONE_ATIMRING FIELD32(0x00000010) 153#define CSR8_TXDONE_PRIORING FIELD32(0x00000020) 154#define CSR8_RXDONE FIELD32(0x00000040) 155 156/* 157 * CSR9: Maximum frame length register. 158 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12. 159 */ 160#define CSR9 0x0024 161#define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80) 162 163/* 164 * CSR11: Back-off control register. 165 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1). 166 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1). 167 * SLOT_TIME: Slot time, default is 20us for 802.11b. 168 * LONG_RETRY: Long retry count. 169 * SHORT_RETRY: Short retry count. 170 */ 171#define CSR11 0x002c 172#define CSR11_CWMIN FIELD32(0x0000000f) 173#define CSR11_CWMAX FIELD32(0x000000f0) 174#define CSR11_SLOT_TIME FIELD32(0x00001f00) 175#define CSR11_LONG_RETRY FIELD32(0x00ff0000) 176#define CSR11_SHORT_RETRY FIELD32(0xff000000) 177 178/* 179 * CSR12: Synchronization configuration register 0. 180 * All units in 1/16 TU. 181 * BEACON_INTERVAL: Beacon interval, default is 100 TU. 182 * CFPMAX_DURATION: Cfp maximum duration, default is 100 TU. 183 */ 184#define CSR12 0x0030 185#define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff) 186#define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000) 187 188/* 189 * CSR13: Synchronization configuration register 1. 190 * All units in 1/16 TU. 191 * ATIMW_DURATION: Atim window duration. 192 * CFP_PERIOD: Cfp period, default is 0 TU. 193 */ 194#define CSR13 0x0034 195#define CSR13_ATIMW_DURATION FIELD32(0x0000ffff) 196#define CSR13_CFP_PERIOD FIELD32(0x00ff0000) 197 198/* 199 * CSR14: Synchronization control register. 200 * TSF_COUNT: Enable tsf auto counting. 201 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. 202 * TBCN: Enable tbcn with reload value. 203 * TCFP: Enable tcfp & cfp / cp switching. 204 * TATIMW: Enable tatimw & atim window switching. 205 * BEACON_GEN: Enable beacon generator. 206 * CFP_COUNT_PRELOAD: Cfp count preload value. 207 * TBCM_PRELOAD: Tbcn preload value in units of 64us. 208 */ 209#define CSR14 0x0038 210#define CSR14_TSF_COUNT FIELD32(0x00000001) 211#define CSR14_TSF_SYNC FIELD32(0x00000006) 212#define CSR14_TBCN FIELD32(0x00000008) 213#define CSR14_TCFP FIELD32(0x00000010) 214#define CSR14_TATIMW FIELD32(0x00000020) 215#define CSR14_BEACON_GEN FIELD32(0x00000040) 216#define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00) 217#define CSR14_TBCM_PRELOAD FIELD32(0xffff0000) 218 219/* 220 * CSR15: Synchronization status register. 221 * CFP: ASIC is in contention-free period. 222 * ATIMW: ASIC is in ATIM window. 223 * BEACON_SENT: Beacon is send. 224 */ 225#define CSR15 0x003c 226#define CSR15_CFP FIELD32(0x00000001) 227#define CSR15_ATIMW FIELD32(0x00000002) 228#define CSR15_BEACON_SENT FIELD32(0x00000004) 229 230/* 231 * CSR16: TSF timer register 0. 232 */ 233#define CSR16 0x0040 234#define CSR16_LOW_TSFTIMER FIELD32(0xffffffff) 235 236/* 237 * CSR17: TSF timer register 1. 238 */ 239#define CSR17 0x0044 240#define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff) 241 242/* 243 * CSR18: IFS timer register 0. 244 * SIFS: Sifs, default is 10 us. 245 * PIFS: Pifs, default is 30 us. 246 */ 247#define CSR18 0x0048 248#define CSR18_SIFS FIELD32(0x0000ffff) 249#define CSR18_PIFS FIELD32(0xffff0000) 250 251/* 252 * CSR19: IFS timer register 1. 253 * DIFS: Difs, default is 50 us. 254 * EIFS: Eifs, default is 364 us. 255 */ 256#define CSR19 0x004c 257#define CSR19_DIFS FIELD32(0x0000ffff) 258#define CSR19_EIFS FIELD32(0xffff0000) 259 260/* 261 * CSR20: Wakeup timer register. 262 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU. 263 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup. 264 * AUTOWAKE: Enable auto wakeup / sleep mechanism. 265 */ 266#define CSR20 0x0050 267#define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff) 268#define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000) 269#define CSR20_AUTOWAKE FIELD32(0x01000000) 270 271/* 272 * CSR21: EEPROM control register. 273 * RELOAD: Write 1 to reload eeprom content. 274 * TYPE_93C46: 1: 93c46, 0:93c66. 275 */ 276#define CSR21 0x0054 277#define CSR21_RELOAD FIELD32(0x00000001) 278#define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002) 279#define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004) 280#define CSR21_EEPROM_DATA_IN FIELD32(0x00000008) 281#define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010) 282#define CSR21_TYPE_93C46 FIELD32(0x00000020) 283 284/* 285 * CSR22: CFP control register. 286 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU. 287 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain. 288 */ 289#define CSR22 0x0058 290#define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff) 291#define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000) 292 293/* 294 * Transmit related CSRs. 295 * Some values are set in TU, whereas 1 TU == 1024 us. 296 */ 297 298/* 299 * TXCSR0: TX Control Register. 300 * KICK_TX: Kick tx ring. 301 * KICK_ATIM: Kick atim ring. 302 * KICK_PRIO: Kick priority ring. 303 * ABORT: Abort all transmit related ring operation. 304 */ 305#define TXCSR0 0x0060 306#define TXCSR0_KICK_TX FIELD32(0x00000001) 307#define TXCSR0_KICK_ATIM FIELD32(0x00000002) 308#define TXCSR0_KICK_PRIO FIELD32(0x00000004) 309#define TXCSR0_ABORT FIELD32(0x00000008) 310 311/* 312 * TXCSR1: TX Configuration Register. 313 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps. 314 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps. 315 * TSF_OFFSET: Insert tsf offset. 316 * AUTORESPONDER: Enable auto responder which include ack & cts. 317 */ 318#define TXCSR1 0x0064 319#define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff) 320#define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00) 321#define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000) 322#define TXCSR1_AUTORESPONDER FIELD32(0x01000000) 323 324/* 325 * TXCSR2: Tx descriptor configuration register. 326 * TXD_SIZE: Tx descriptor size, default is 48. 327 * NUM_TXD: Number of tx entries in ring. 328 * NUM_ATIM: Number of atim entries in ring. 329 * NUM_PRIO: Number of priority entries in ring. 330 */ 331#define TXCSR2 0x0068 332#define TXCSR2_TXD_SIZE FIELD32(0x000000ff) 333#define TXCSR2_NUM_TXD FIELD32(0x0000ff00) 334#define TXCSR2_NUM_ATIM FIELD32(0x00ff0000) 335#define TXCSR2_NUM_PRIO FIELD32(0xff000000) 336 337/* 338 * TXCSR3: TX Ring Base address register. 339 */ 340#define TXCSR3 0x006c 341#define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff) 342 343/* 344 * TXCSR4: TX Atim Ring Base address register. 345 */ 346#define TXCSR4 0x0070 347#define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff) 348 349/* 350 * TXCSR5: TX Prio Ring Base address register. 351 */ 352#define TXCSR5 0x0074 353#define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff) 354 355/* 356 * TXCSR6: Beacon Base address register. 357 */ 358#define TXCSR6 0x0078 359#define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff) 360 361/* 362 * TXCSR7: Auto responder control register. 363 * AR_POWERMANAGEMENT: Auto responder power management bit. 364 */ 365#define TXCSR7 0x007c 366#define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001) 367 368/* 369 * Receive related CSRs. 370 * Some values are set in TU, whereas 1 TU == 1024 us. 371 */ 372 373/* 374 * RXCSR0: RX Control Register. 375 * DISABLE_RX: Disable rx engine. 376 * DROP_CRC: Drop crc error. 377 * DROP_PHYSICAL: Drop physical error. 378 * DROP_CONTROL: Drop control frame. 379 * DROP_NOT_TO_ME: Drop not to me unicast frame. 380 * DROP_TODS: Drop frame tods bit is true. 381 * DROP_VERSION_ERROR: Drop version error frame. 382 * PASS_CRC: Pass all packets with crc attached. 383 */ 384#define RXCSR0 0x0080 385#define RXCSR0_DISABLE_RX FIELD32(0x00000001) 386#define RXCSR0_DROP_CRC FIELD32(0x00000002) 387#define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004) 388#define RXCSR0_DROP_CONTROL FIELD32(0x00000008) 389#define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010) 390#define RXCSR0_DROP_TODS FIELD32(0x00000020) 391#define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040) 392#define RXCSR0_PASS_CRC FIELD32(0x00000080) 393 394/* 395 * RXCSR1: RX descriptor configuration register. 396 * RXD_SIZE: Rx descriptor size, default is 32b. 397 * NUM_RXD: Number of rx entries in ring. 398 */ 399#define RXCSR1 0x0084 400#define RXCSR1_RXD_SIZE FIELD32(0x000000ff) 401#define RXCSR1_NUM_RXD FIELD32(0x0000ff00) 402 403/* 404 * RXCSR2: RX Ring base address register. 405 */ 406#define RXCSR2 0x0088 407#define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff) 408 409/* 410 * RXCSR3: BBP ID register for Rx operation. 411 * BBP_ID#: BBP register # id. 412 * BBP_ID#_VALID: BBP register # id is valid or not. 413 */ 414#define RXCSR3 0x0090 415#define RXCSR3_BBP_ID0 FIELD32(0x0000007f) 416#define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080) 417#define RXCSR3_BBP_ID1 FIELD32(0x00007f00) 418#define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000) 419#define RXCSR3_BBP_ID2 FIELD32(0x007f0000) 420#define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000) 421#define RXCSR3_BBP_ID3 FIELD32(0x7f000000) 422#define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000) 423 424/* 425 * RXCSR4: BBP ID register for Rx operation. 426 * BBP_ID#: BBP register # id. 427 * BBP_ID#_VALID: BBP register # id is valid or not. 428 */ 429#define RXCSR4 0x0094 430#define RXCSR4_BBP_ID4 FIELD32(0x0000007f) 431#define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080) 432#define RXCSR4_BBP_ID5 FIELD32(0x00007f00) 433#define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000) 434 435/* 436 * ARCSR0: Auto Responder PLCP config register 0. 437 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data. 438 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id. 439 */ 440#define ARCSR0 0x0098 441#define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff) 442#define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00) 443#define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000) 444#define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000) 445 446/* 447 * ARCSR1: Auto Responder PLCP config register 1. 448 * ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data. 449 * ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id. 450 */ 451#define ARCSR1 0x009c 452#define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff) 453#define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00) 454#define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000) 455#define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000) 456 457/* 458 * Miscellaneous Registers. 459 * Some values are set in TU, whereas 1 TU == 1024 us. 460 */ 461 462/* 463 * PCICSR: PCI control register. 464 * BIG_ENDIAN: 1: big endian, 0: little endian. 465 * RX_TRESHOLD: Rx threshold in dw to start pci access 466 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw. 467 * TX_TRESHOLD: Tx threshold in dw to start pci access 468 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward. 469 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw. 470 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational. 471 */ 472#define PCICSR 0x008c 473#define PCICSR_BIG_ENDIAN FIELD32(0x00000001) 474#define PCICSR_RX_TRESHOLD FIELD32(0x00000006) 475#define PCICSR_TX_TRESHOLD FIELD32(0x00000018) 476#define PCICSR_BURST_LENTH FIELD32(0x00000060) 477#define PCICSR_ENABLE_CLK FIELD32(0x00000080) 478 479/* 480 * CNT0: FCS error count. 481 * FCS_ERROR: FCS error count, cleared when read. 482 */ 483#define CNT0 0x00a0 484#define CNT0_FCS_ERROR FIELD32(0x0000ffff) 485 486/* 487 * Statistic Register. 488 * CNT1: PLCP error count. 489 * CNT2: Long error count. 490 * CNT3: CCA false alarm count. 491 * CNT4: Rx FIFO overflow count. 492 * CNT5: Tx FIFO underrun count. 493 */ 494#define TIMECSR2 0x00a8 495#define CNT1 0x00ac 496#define CNT2 0x00b0 497#define TIMECSR3 0x00b4 498#define CNT3 0x00b8 499#define CNT4 0x00bc 500#define CNT5 0x00c0 501 502/* 503 * Baseband Control Register. 504 */ 505 506/* 507 * PWRCSR0: Power mode configuration register. 508 */ 509#define PWRCSR0 0x00c4 510 511/* 512 * Power state transition time registers. 513 */ 514#define PSCSR0 0x00c8 515#define PSCSR1 0x00cc 516#define PSCSR2 0x00d0 517#define PSCSR3 0x00d4 518 519/* 520 * PWRCSR1: Manual power control / status register. 521 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. 522 * SET_STATE: Set state. Write 1 to trigger, self cleared. 523 * BBP_DESIRE_STATE: BBP desired state. 524 * RF_DESIRE_STATE: RF desired state. 525 * BBP_CURR_STATE: BBP current state. 526 * RF_CURR_STATE: RF current state. 527 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. 528 */ 529#define PWRCSR1 0x00d8 530#define PWRCSR1_SET_STATE FIELD32(0x00000001) 531#define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006) 532#define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018) 533#define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060) 534#define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180) 535#define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200) 536 537/* 538 * TIMECSR: Timer control register. 539 * US_COUNT: 1 us timer count in units of clock cycles. 540 * US_64_COUNT: 64 us timer count in units of 1 us timer. 541 * BEACON_EXPECT: Beacon expect window. 542 */ 543#define TIMECSR 0x00dc 544#define TIMECSR_US_COUNT FIELD32(0x000000ff) 545#define TIMECSR_US_64_COUNT FIELD32(0x0000ff00) 546#define TIMECSR_BEACON_EXPECT FIELD32(0x00070000) 547 548/* 549 * MACCSR0: MAC configuration register 0. 550 */ 551#define MACCSR0 0x00e0 552 553/* 554 * MACCSR1: MAC configuration register 1. 555 * KICK_RX: Kick one-shot rx in one-shot rx mode. 556 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging. 557 * BBPRX_RESET_MODE: Ralink bbp rx reset mode. 558 * AUTO_TXBBP: Auto tx logic access bbp control register. 559 * AUTO_RXBBP: Auto rx logic access bbp control register. 560 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd. 561 * INTERSIL_IF: Intersil if calibration pin. 562 */ 563#define MACCSR1 0x00e4 564#define MACCSR1_KICK_RX FIELD32(0x00000001) 565#define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002) 566#define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004) 567#define MACCSR1_AUTO_TXBBP FIELD32(0x00000008) 568#define MACCSR1_AUTO_RXBBP FIELD32(0x00000010) 569#define MACCSR1_LOOPBACK FIELD32(0x00000060) 570#define MACCSR1_INTERSIL_IF FIELD32(0x00000080) 571 572/* 573 * RALINKCSR: Ralink Rx auto-reset BBCR. 574 * AR_BBP_DATA#: Auto reset BBP register # data. 575 * AR_BBP_ID#: Auto reset BBP register # id. 576 */ 577#define RALINKCSR 0x00e8 578#define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff) 579#define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00) 580#define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000) 581#define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000) 582 583/* 584 * BCNCSR: Beacon interval control register. 585 * CHANGE: Write one to change beacon interval. 586 * DELTATIME: The delta time value. 587 * NUM_BEACON: Number of beacon according to mode. 588 * MODE: Please refer to asic specs. 589 * PLUS: Plus or minus delta time value. 590 */ 591#define BCNCSR 0x00ec 592#define BCNCSR_CHANGE FIELD32(0x00000001) 593#define BCNCSR_DELTATIME FIELD32(0x0000001e) 594#define BCNCSR_NUM_BEACON FIELD32(0x00001fe0) 595#define BCNCSR_MODE FIELD32(0x00006000) 596#define BCNCSR_PLUS FIELD32(0x00008000) 597 598/* 599 * BBP / RF / IF Control Register. 600 */ 601 602/* 603 * BBPCSR: BBP serial control register. 604 * VALUE: Register value to program into BBP. 605 * REGNUM: Selected BBP register. 606 * BUSY: 1: asic is busy execute BBP programming. 607 * WRITE_CONTROL: 1: write BBP, 0: read BBP. 608 */ 609#define BBPCSR 0x00f0 610#define BBPCSR_VALUE FIELD32(0x000000ff) 611#define BBPCSR_REGNUM FIELD32(0x00007f00) 612#define BBPCSR_BUSY FIELD32(0x00008000) 613#define BBPCSR_WRITE_CONTROL FIELD32(0x00010000) 614 615/* 616 * RFCSR: RF serial control register. 617 * VALUE: Register value + id to program into rf/if. 618 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). 619 * IF_SELECT: Chip to program: 0: rf, 1: if. 620 * PLL_LD: Rf pll_ld status. 621 * BUSY: 1: asic is busy execute rf programming. 622 */ 623#define RFCSR 0x00f4 624#define RFCSR_VALUE FIELD32(0x00ffffff) 625#define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000) 626#define RFCSR_IF_SELECT FIELD32(0x20000000) 627#define RFCSR_PLL_LD FIELD32(0x40000000) 628#define RFCSR_BUSY FIELD32(0x80000000) 629 630/* 631 * LEDCSR: LED control register. 632 * ON_PERIOD: On period, default 70ms. 633 * OFF_PERIOD: Off period, default 30ms. 634 * LINK: 0: linkoff, 1: linkup. 635 * ACTIVITY: 0: idle, 1: active. 636 */ 637#define LEDCSR 0x00f8 638#define LEDCSR_ON_PERIOD FIELD32(0x000000ff) 639#define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00) 640#define LEDCSR_LINK FIELD32(0x00010000) 641#define LEDCSR_ACTIVITY FIELD32(0x00020000) 642 643/* 644 * ASIC pointer information. 645 * RXPTR: Current RX ring address. 646 * TXPTR: Current Tx ring address. 647 * PRIPTR: Current Priority ring address. 648 * ATIMPTR: Current ATIM ring address. 649 */ 650#define RXPTR 0x0100 651#define TXPTR 0x0104 652#define PRIPTR 0x0108 653#define ATIMPTR 0x010c 654 655/* 656 * GPIO and others. 657 */ 658 659/* 660 * GPIOCSR: GPIO control register. 661 * GPIOCSR_VALx: Actual GPIO pin x value 662 * GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input 663 */ 664#define GPIOCSR 0x0120 665#define GPIOCSR_VAL0 FIELD32(0x00000001) 666#define GPIOCSR_VAL1 FIELD32(0x00000002) 667#define GPIOCSR_VAL2 FIELD32(0x00000004) 668#define GPIOCSR_VAL3 FIELD32(0x00000008) 669#define GPIOCSR_VAL4 FIELD32(0x00000010) 670#define GPIOCSR_VAL5 FIELD32(0x00000020) 671#define GPIOCSR_VAL6 FIELD32(0x00000040) 672#define GPIOCSR_VAL7 FIELD32(0x00000080) 673#define GPIOCSR_DIR0 FIELD32(0x00000100) 674#define GPIOCSR_DIR1 FIELD32(0x00000200) 675#define GPIOCSR_DIR2 FIELD32(0x00000400) 676#define GPIOCSR_DIR3 FIELD32(0x00000800) 677#define GPIOCSR_DIR4 FIELD32(0x00001000) 678#define GPIOCSR_DIR5 FIELD32(0x00002000) 679#define GPIOCSR_DIR6 FIELD32(0x00004000) 680#define GPIOCSR_DIR7 FIELD32(0x00008000) 681 682/* 683 * BBPPCSR: BBP Pin control register. 684 */ 685#define BBPPCSR 0x0124 686 687/* 688 * BCNCSR1: Tx BEACON offset time control register. 689 * PRELOAD: Beacon timer offset in units of usec. 690 */ 691#define BCNCSR1 0x0130 692#define BCNCSR1_PRELOAD FIELD32(0x0000ffff) 693 694/* 695 * MACCSR2: TX_PE to RX_PE turn-around time control register 696 * DELAY: RX_PE low width, in units of pci clock cycle. 697 */ 698#define MACCSR2 0x0134 699#define MACCSR2_DELAY FIELD32(0x000000ff) 700 701/* 702 * ARCSR2: 1 Mbps ACK/CTS PLCP. 703 */ 704#define ARCSR2 0x013c 705#define ARCSR2_SIGNAL FIELD32(0x000000ff) 706#define ARCSR2_SERVICE FIELD32(0x0000ff00) 707#define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000) 708#define ARCSR2_LENGTH FIELD32(0xffff0000) 709 710/* 711 * ARCSR3: 2 Mbps ACK/CTS PLCP. 712 */ 713#define ARCSR3 0x0140 714#define ARCSR3_SIGNAL FIELD32(0x000000ff) 715#define ARCSR3_SERVICE FIELD32(0x0000ff00) 716#define ARCSR3_LENGTH FIELD32(0xffff0000) 717 718/* 719 * ARCSR4: 5.5 Mbps ACK/CTS PLCP. 720 */ 721#define ARCSR4 0x0144 722#define ARCSR4_SIGNAL FIELD32(0x000000ff) 723#define ARCSR4_SERVICE FIELD32(0x0000ff00) 724#define ARCSR4_LENGTH FIELD32(0xffff0000) 725 726/* 727 * ARCSR5: 11 Mbps ACK/CTS PLCP. 728 */ 729#define ARCSR5 0x0148 730#define ARCSR5_SIGNAL FIELD32(0x000000ff) 731#define ARCSR5_SERVICE FIELD32(0x0000ff00) 732#define ARCSR5_LENGTH FIELD32(0xffff0000) 733 734/* 735 * BBP registers. 736 * The wordsize of the BBP is 8 bits. 737 */ 738 739/* 740 * R1: TX antenna control 741 */ 742#define BBP_R1_TX_ANTENNA FIELD8(0x03) 743 744/* 745 * R4: RX antenna control 746 */ 747#define BBP_R4_RX_ANTENNA FIELD8(0x06) 748 749/* 750 * RF registers 751 */ 752 753/* 754 * RF 1 755 */ 756#define RF1_TUNER FIELD32(0x00020000) 757 758/* 759 * RF 3 760 */ 761#define RF3_TUNER FIELD32(0x00000100) 762#define RF3_TXPOWER FIELD32(0x00003e00) 763 764/* 765 * EEPROM content. 766 * The wordsize of the EEPROM is 16 bits. 767 */ 768 769/* 770 * HW MAC address. 771 */ 772#define EEPROM_MAC_ADDR_0 0x0002 773#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) 774#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) 775#define EEPROM_MAC_ADDR1 0x0003 776#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) 777#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) 778#define EEPROM_MAC_ADDR_2 0x0004 779#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) 780#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 781 782/* 783 * EEPROM antenna. 784 * ANTENNA_NUM: Number of antenna's. 785 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 786 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 787 * RF_TYPE: Rf_type of this adapter. 788 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd. 789 * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning. 790 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. 791 */ 792#define EEPROM_ANTENNA 0x0b 793#define EEPROM_ANTENNA_NUM FIELD16(0x0003) 794#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) 795#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) 796#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040) 797#define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180) 798#define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200) 799#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) 800 801/* 802 * EEPROM BBP. 803 */ 804#define EEPROM_BBP_START 0x0c 805#define EEPROM_BBP_SIZE 7 806#define EEPROM_BBP_VALUE FIELD16(0x00ff) 807#define EEPROM_BBP_REG_ID FIELD16(0xff00) 808 809/* 810 * EEPROM TXPOWER 811 */ 812#define EEPROM_TXPOWER_START 0x13 813#define EEPROM_TXPOWER_SIZE 7 814#define EEPROM_TXPOWER_1 FIELD16(0x00ff) 815#define EEPROM_TXPOWER_2 FIELD16(0xff00) 816 817/* 818 * DMA descriptor defines. 819 */ 820#define TXD_DESC_SIZE (8 * sizeof(__le32)) 821#define RXD_DESC_SIZE (8 * sizeof(__le32)) 822 823/* 824 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. 825 */ 826 827/* 828 * Word0 829 */ 830#define TXD_W0_OWNER_NIC FIELD32(0x00000001) 831#define TXD_W0_VALID FIELD32(0x00000002) 832#define TXD_W0_RESULT FIELD32(0x0000001c) 833#define TXD_W0_RETRY_COUNT FIELD32(0x000000e0) 834#define TXD_W0_MORE_FRAG FIELD32(0x00000100) 835#define TXD_W0_ACK FIELD32(0x00000200) 836#define TXD_W0_TIMESTAMP FIELD32(0x00000400) 837#define TXD_W0_RTS FIELD32(0x00000800) 838#define TXD_W0_IFS FIELD32(0x00006000) 839#define TXD_W0_RETRY_MODE FIELD32(0x00008000) 840#define TXD_W0_AGC FIELD32(0x00ff0000) 841#define TXD_W0_R2 FIELD32(0xff000000) 842 843/* 844 * Word1 845 */ 846#define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) 847 848/* 849 * Word2 850 */ 851#define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) 852#define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000) 853 854/* 855 * Word3 & 4: PLCP information 856 * The PLCP values should be treated as if they were BBP values. 857 */ 858#define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff) 859#define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00) 860#define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000) 861#define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000) 862#define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000) 863#define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000) 864 865#define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff) 866#define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00) 867#define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000) 868#define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000) 869#define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000) 870#define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000) 871 872/* 873 * Word5 874 */ 875#define TXD_W5_BBCR4 FIELD32(0x0000ffff) 876#define TXD_W5_AGC_REG FIELD32(0x007f0000) 877#define TXD_W5_AGC_REG_VALID FIELD32(0x00800000) 878#define TXD_W5_XXX_REG FIELD32(0x7f000000) 879#define TXD_W5_XXX_REG_VALID FIELD32(0x80000000) 880 881/* 882 * Word6 883 */ 884#define TXD_W6_SK_BUFF FIELD32(0xffffffff) 885 886/* 887 * Word7 888 */ 889#define TXD_W7_RESERVED FIELD32(0xffffffff) 890 891/* 892 * RX descriptor format for RX Ring. 893 */ 894 895/* 896 * Word0 897 */ 898#define RXD_W0_OWNER_NIC FIELD32(0x00000001) 899#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) 900#define RXD_W0_MULTICAST FIELD32(0x00000004) 901#define RXD_W0_BROADCAST FIELD32(0x00000008) 902#define RXD_W0_MY_BSS FIELD32(0x00000010) 903#define RXD_W0_CRC_ERROR FIELD32(0x00000020) 904#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) 905#define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000) 906 907/* 908 * Word1 909 */ 910#define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff) 911 912/* 913 * Word2 914 */ 915#define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff) 916#define RXD_W2_BBR0 FIELD32(0x00ff0000) 917#define RXD_W2_SIGNAL FIELD32(0xff000000) 918 919/* 920 * Word3 921 */ 922#define RXD_W3_RSSI FIELD32(0x000000ff) 923#define RXD_W3_BBR3 FIELD32(0x0000ff00) 924#define RXD_W3_BBR4 FIELD32(0x00ff0000) 925#define RXD_W3_BBR5 FIELD32(0xff000000) 926 927/* 928 * Word4 929 */ 930#define RXD_W4_RX_END_TIME FIELD32(0xffffffff) 931 932/* 933 * Word5 & 6 & 7: Reserved 934 */ 935#define RXD_W5_RESERVED FIELD32(0xffffffff) 936#define RXD_W6_RESERVED FIELD32(0xffffffff) 937#define RXD_W7_RESERVED FIELD32(0xffffffff) 938 939/* 940 * Macros for converting txpower from EEPROM to mac80211 value 941 * and from mac80211 value to register value. 942 * NOTE: Logics in rt2400pci for txpower are reversed 943 * compared to the other rt2x00 drivers. A higher txpower 944 * value means that the txpower must be lowered. This is 945 * important when converting the value coming from the 946 * mac80211 stack to the rt2400 acceptable value. 947 */ 948#define MIN_TXPOWER 31 949#define MAX_TXPOWER 62 950#define DEFAULT_TXPOWER 39 951 952#define __CLAMP_TX(__txpower) \ 953 clamp_t(char, (__txpower), MIN_TXPOWER, MAX_TXPOWER) 954 955#define TXPOWER_FROM_DEV(__txpower) \ 956 ((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER) 957 958#define TXPOWER_TO_DEV(__txpower) \ 959 (MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER)) 960 961#endif /* RT2400PCI_H */ 962