LXR linux/drivers/pinctrl/freescale/pinctrl-imx.h

   1/*
   2 * IMX pinmux core definitions
   3 *
   4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
   5 * Copyright (C) 2012 Linaro Ltd.
   6 *
   7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; either version 2 of the License, or
  12 * (at your option) any later version.
  13 */
  14
  15#ifndef __DRIVERS_PINCTRL_IMX_H
  16#define __DRIVERS_PINCTRL_IMX_H
  17
  18#include <linux/pinctrl/pinconf-generic.h>
  19#include <linux/pinctrl/pinmux.h>
  20
  21struct platform_device;
  22
  23extern struct pinmux_ops imx_pmx_ops;
  24
  25/**
  26 * struct imx_pin - describes a single i.MX pin
  27 * @pin: the pin_id of this pin
  28 * @mux_mode: the mux mode for this pin.
  29 * @input_reg: the select input register offset for this pin if any
  30 *      0 if no select input setting needed.
  31 * @input_val: the select input value for this pin.
  32 * @configs: the config for this pin.
  33 */
  34struct imx_pin {
  35        unsigned int pin;
  36        unsigned int mux_mode;
  37        u16 input_reg;
  38        unsigned int input_val;
  39        unsigned long config;
  40};
  41
  42/**
  43 * struct imx_pin_reg - describe a pin reg map
  44 * @mux_reg: mux register offset
  45 * @conf_reg: config register offset
  46 */
  47struct imx_pin_reg {
  48        s16 mux_reg;
  49        s16 conf_reg;
  50};
  51
  52/* decode a generic config into raw register value */
  53struct imx_cfg_params_decode {
  54        enum pin_config_param param;
  55        u32 mask;
  56        u8 shift;
  57        bool invert;
  58};
  59
  60struct imx_pinctrl_soc_info {
  61        const struct pinctrl_pin_desc *pins;
  62        unsigned int npins;
  63        unsigned int flags;
  64        const char *gpr_compatible;
  65
  66        /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
  67        unsigned int mux_mask;
  68        u8 mux_shift;
  69
  70        /* generic pinconf */
  71        bool generic_pinconf;
  72        const struct pinconf_generic_params *custom_params;
  73        unsigned int num_custom_params;
  74        const struct imx_cfg_params_decode *decodes;
  75        unsigned int num_decodes;
  76        void (*fixup)(unsigned long *configs, unsigned int num_configs,
  77                      u32 *raw_config);
  78
  79        int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
  80                                  struct pinctrl_gpio_range *range,
  81                                  unsigned offset,
  82                                  bool input);
  83};
  84
  85/**
  86 * @dev: a pointer back to containing device
  87 * @base: the offset to the controller in virtual memory
  88 */
  89struct imx_pinctrl {
  90        struct device *dev;
  91        struct pinctrl_dev *pctl;
  92        void __iomem *base;
  93        void __iomem *input_sel_base;
  94        const struct imx_pinctrl_soc_info *info;
  95        struct imx_pin_reg *pin_regs;
  96        unsigned int group_index;
  97        struct mutex mutex;
  98};
  99
 100#define IMX_CFG_PARAMS_DECODE(p, m, o) \
 101        { .param = p, .mask = m, .shift = o, .invert = false, }
 102
 103#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
 104        { .param = p, .mask = m, .shift = o, .invert = true, }
 105
 106#define SHARE_MUX_CONF_REG      0x1
 107#define ZERO_OFFSET_VALID       0x2
 108
 109#define NO_MUX          0x0
 110#define NO_PAD          0x0
 111
 112#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
 113
 114#define PAD_CTL_MASK(len)       ((1 << len) - 1)
 115#define IMX_MUX_MASK    0x7
 116#define IOMUXC_CONFIG_SION      (0x1 << 4)
 117
 118int imx_pinctrl_probe(struct platform_device *pdev,
 119                        const struct imx_pinctrl_soc_info *info);
 120#endif /* __DRIVERS_PINCTRL_IMX_H */
 121