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7#include "qla_def.h"
8#include <linux/delay.h>
9#include <linux/ktime.h>
10#include <linux/pci.h>
11#include <linux/ratelimit.h>
12#include <linux/vmalloc.h>
13#include <linux/bsg-lib.h>
14#include <scsi/scsi_tcq.h>
15#include <linux/utsname.h>
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38
39static int
40qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
41
42{
43 int rval;
44 unsigned long flags = 0;
45 device_reg_t *reg;
46 uint8_t abort_active;
47 uint8_t io_lock_on;
48 uint16_t command = 0;
49 uint32_t *iptr;
50 uint32_t __iomem *optr;
51 uint32_t cnt;
52 uint32_t mboxes;
53 unsigned long wait_time;
54 struct qla_hw_data *ha = vha->hw;
55 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
56
57 if (ha->pdev->error_state > pci_channel_io_frozen) {
58 ql_log(ql_log_warn, vha, 0x115c,
59 "error_state is greater than pci_channel_io_frozen, "
60 "exiting.\n");
61 return QLA_FUNCTION_TIMEOUT;
62 }
63
64 if (vha->device_flags & DFLG_DEV_FAILED) {
65 ql_log(ql_log_warn, vha, 0x115f,
66 "Device in failed state, exiting.\n");
67 return QLA_FUNCTION_TIMEOUT;
68 }
69
70 reg = ha->iobase;
71 io_lock_on = base_vha->flags.init_done;
72
73 rval = QLA_SUCCESS;
74 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
75
76 if (ha->flags.pci_channel_io_perm_failure) {
77 ql_log(ql_log_warn, vha, 0x1175,
78 "Perm failure on EEH timeout MBX, exiting.\n");
79 return QLA_FUNCTION_TIMEOUT;
80 }
81
82 if (ha->flags.isp82xx_fw_hung) {
83
84 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
85 ql_log(ql_log_warn, vha, 0x1176,
86 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
87 rval = QLA_FUNCTION_FAILED;
88 goto premature_exit;
89 }
90
91
92
93
94
95
96 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
97
98 ql_log(ql_log_warn, vha, 0x1177,
99 "Cmd access timeout, cmd=0x%x, Exiting.\n",
100 mcp->mb[0]);
101 return QLA_FUNCTION_TIMEOUT;
102 }
103
104 ha->flags.mbox_busy = 1;
105
106 ha->mcp32 = mcp;
107
108 ql_dbg(ql_dbg_mbx, vha, 0x1178,
109 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
110
111 spin_lock_irqsave(&ha->hardware_lock, flags);
112
113
114 optr = (uint32_t __iomem *)®->ispfx00.mailbox0;
115
116 iptr = mcp->mb;
117 command = mcp->mb[0];
118 mboxes = mcp->out_mb;
119
120 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
121 if (mboxes & BIT_0)
122 WRT_REG_DWORD(optr, *iptr);
123
124 mboxes >>= 1;
125 optr++;
126 iptr++;
127 }
128
129
130 ha->flags.mbox_int = 0;
131 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
132
133 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
134 (uint8_t *)mcp->mb, 16);
135 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
136 ((uint8_t *)mcp->mb + 0x10), 16);
137 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
138 ((uint8_t *)mcp->mb + 0x20), 8);
139
140
141 ql_dbg(ql_dbg_mbx, vha, 0x1179,
142 "Going to unlock irq & waiting for interrupts. "
143 "jiffies=%lx.\n", jiffies);
144
145
146 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
147 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
148
149 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
150 spin_unlock_irqrestore(&ha->hardware_lock, flags);
151
152 wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
153 } else {
154 ql_dbg(ql_dbg_mbx, vha, 0x112c,
155 "Cmd=%x Polling Mode.\n", command);
156
157 QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
158 spin_unlock_irqrestore(&ha->hardware_lock, flags);
159
160 wait_time = jiffies + mcp->tov * HZ;
161 while (!ha->flags.mbox_int) {
162 if (time_after(jiffies, wait_time))
163 break;
164
165
166 qla2x00_poll(ha->rsp_q_map[0]);
167
168 if (!ha->flags.mbox_int &&
169 !(IS_QLA2200(ha) &&
170 command == MBC_LOAD_RISC_RAM_EXTENDED))
171 usleep_range(10000, 11000);
172 }
173 ql_dbg(ql_dbg_mbx, vha, 0x112d,
174 "Waited %d sec.\n",
175 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
176 }
177
178
179 if (ha->flags.mbox_int) {
180 uint32_t *iptr2;
181
182 ql_dbg(ql_dbg_mbx, vha, 0x112e,
183 "Cmd=%x completed.\n", command);
184
185
186 ha->flags.mbox_int = 0;
187 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
188
189 if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
190 rval = QLA_FUNCTION_FAILED;
191
192
193 iptr2 = mcp->mb;
194 iptr = (uint32_t *)&ha->mailbox_out32[0];
195 mboxes = mcp->in_mb;
196 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
197 if (mboxes & BIT_0)
198 *iptr2 = *iptr;
199
200 mboxes >>= 1;
201 iptr2++;
202 iptr++;
203 }
204 } else {
205
206 rval = QLA_FUNCTION_TIMEOUT;
207 }
208
209 ha->flags.mbox_busy = 0;
210
211
212 ha->mcp32 = NULL;
213
214 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
215 ql_dbg(ql_dbg_mbx, vha, 0x113a,
216 "checking for additional resp interrupt.\n");
217
218
219 qla2x00_poll(ha->rsp_q_map[0]);
220 }
221
222 if (rval == QLA_FUNCTION_TIMEOUT &&
223 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
224 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
225 ha->flags.eeh_busy) {
226
227 ql_dbg(ql_dbg_mbx, vha, 0x115d,
228 "Timeout, schedule isp_abort_needed.\n");
229
230 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
231 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
232 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
233
234 ql_log(ql_log_info, base_vha, 0x115e,
235 "Mailbox cmd timeout occurred, cmd=0x%x, "
236 "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
237 "abort.\n", command, mcp->mb[0],
238 ha->flags.eeh_busy);
239 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
240 qla2xxx_wake_dpc(vha);
241 }
242 } else if (!abort_active) {
243
244 ql_dbg(ql_dbg_mbx, vha, 0x1160,
245 "Timeout, calling abort_isp.\n");
246
247 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
248 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
249 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
250
251 ql_log(ql_log_info, base_vha, 0x1161,
252 "Mailbox cmd timeout occurred, cmd=0x%x, "
253 "mb[0]=0x%x. Scheduling ISP abort ",
254 command, mcp->mb[0]);
255
256 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
257 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
258 if (ha->isp_ops->abort_isp(vha)) {
259
260 set_bit(ISP_ABORT_NEEDED,
261 &vha->dpc_flags);
262 }
263 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
264 ql_dbg(ql_dbg_mbx, vha, 0x1162,
265 "Finished abort_isp.\n");
266 }
267 }
268 }
269
270premature_exit:
271
272 complete(&ha->mbx_cmd_comp);
273
274 if (rval) {
275 ql_log(ql_log_warn, base_vha, 0x1163,
276 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
277 "mb[3]=%x, cmd=%x ****.\n",
278 mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
279 } else {
280 ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
281 }
282
283 return rval;
284}
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298
299int
300qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
301{
302 int rval;
303 struct mbx_cmd_32 mc;
304 struct mbx_cmd_32 *mcp = &mc;
305
306 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
307 "Entered %s.\n", __func__);
308
309 mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
310 mcp->out_mb = MBX_0;
311 mcp->in_mb = MBX_0;
312 if (tmo)
313 mcp->tov = tmo;
314 else
315 mcp->tov = MBX_TOV_SECONDS;
316 mcp->flags = 0;
317 rval = qlafx00_mailbox_command(vha, mcp);
318
319 if (rval != QLA_SUCCESS) {
320 ql_dbg(ql_dbg_mbx, vha, 0x1167,
321 "Failed=%x.\n", rval);
322 } else {
323 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
324 "Done %s.\n", __func__);
325 }
326
327 return rval;
328}
329
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342
343
344
345static int
346qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
347{
348 int rval;
349 struct mbx_cmd_32 mc;
350 struct mbx_cmd_32 *mcp = &mc;
351
352 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
353 "Entered %s.\n", __func__);
354
355 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
356 mcp->out_mb = MBX_0;
357 mcp->in_mb = MBX_1|MBX_0;
358 mcp->tov = MBX_TOV_SECONDS;
359 mcp->flags = 0;
360 rval = qlafx00_mailbox_command(vha, mcp);
361
362
363 states[0] = mcp->mb[1];
364
365 if (rval != QLA_SUCCESS) {
366 ql_dbg(ql_dbg_mbx, vha, 0x116a,
367 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
368 } else {
369 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
370 "Done %s.\n", __func__);
371 }
372 return rval;
373}
374
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389
390
391
392int
393qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
394{
395 int rval;
396 struct mbx_cmd_32 mc;
397 struct mbx_cmd_32 *mcp = &mc;
398 struct qla_hw_data *ha = vha->hw;
399
400 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
401 "Entered %s.\n", __func__);
402
403 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
404
405 mcp->mb[1] = 0;
406 mcp->mb[2] = MSD(ha->init_cb_dma);
407 mcp->mb[3] = LSD(ha->init_cb_dma);
408
409 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
410 mcp->in_mb = MBX_0;
411 mcp->buf_size = size;
412 mcp->flags = MBX_DMA_OUT;
413 mcp->tov = MBX_TOV_SECONDS;
414 rval = qlafx00_mailbox_command(vha, mcp);
415
416 if (rval != QLA_SUCCESS) {
417 ql_dbg(ql_dbg_mbx, vha, 0x116d,
418 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
419 } else {
420 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
421 "Done %s.\n", __func__);
422 }
423 return rval;
424}
425
426
427
428
429static int
430qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
431{
432 int rval;
433 struct mbx_cmd_32 mc;
434 struct mbx_cmd_32 *mcp = &mc;
435
436 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
437 "Entered %s.\n", __func__);
438
439
440 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
441 mcp->mb[1] = 0xAAAA;
442 mcp->mb[2] = 0x5555;
443 mcp->mb[3] = 0xAA55;
444 mcp->mb[4] = 0x55AA;
445 mcp->mb[5] = 0xA5A5;
446 mcp->mb[6] = 0x5A5A;
447 mcp->mb[7] = 0x2525;
448 mcp->mb[8] = 0xBBBB;
449 mcp->mb[9] = 0x6666;
450 mcp->mb[10] = 0xBB66;
451 mcp->mb[11] = 0x66BB;
452 mcp->mb[12] = 0xB6B6;
453 mcp->mb[13] = 0x6B6B;
454 mcp->mb[14] = 0x3636;
455 mcp->mb[15] = 0xCCCC;
456
457
458 mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
459 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
460 mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
461 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
462 mcp->buf_size = 0;
463 mcp->flags = MBX_DMA_OUT;
464 mcp->tov = MBX_TOV_SECONDS;
465 rval = qlafx00_mailbox_command(vha, mcp);
466 if (rval == QLA_SUCCESS) {
467 if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
468 mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
469 rval = QLA_FUNCTION_FAILED;
470 if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
471 mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
472 rval = QLA_FUNCTION_FAILED;
473 if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
474 mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
475 rval = QLA_FUNCTION_FAILED;
476 if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
477 mcp->mb[31] != 0xCCCC)
478 rval = QLA_FUNCTION_FAILED;
479 }
480
481 if (rval != QLA_SUCCESS) {
482 ql_dbg(ql_dbg_mbx, vha, 0x1170,
483 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
484 } else {
485 ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
486 "Done %s.\n", __func__);
487 }
488 return rval;
489}
490
491
492
493
494
495
496
497int
498qlafx00_pci_config(scsi_qla_host_t *vha)
499{
500 uint16_t w;
501 struct qla_hw_data *ha = vha->hw;
502
503 pci_set_master(ha->pdev);
504 pci_try_set_mwi(ha->pdev);
505
506 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
507 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
508 w &= ~PCI_COMMAND_INTX_DISABLE;
509 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
510
511
512 if (pci_is_pcie(ha->pdev))
513 pcie_set_readrq(ha->pdev, 2048);
514
515 ha->chip_revision = ha->pdev->revision;
516
517 return QLA_SUCCESS;
518}
519
520
521
522
523
524
525static inline void
526qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
527{
528 unsigned long flags = 0;
529 struct qla_hw_data *ha = vha->hw;
530 int i, core;
531 uint32_t cnt;
532 uint32_t reg_val;
533
534 spin_lock_irqsave(&ha->hardware_lock, flags);
535
536 QLAFX00_SET_HBA_SOC_REG(ha, 0x80004, 0);
537 QLAFX00_SET_HBA_SOC_REG(ha, 0x82004, 0);
538
539
540 QLAFX00_SET_HBA_SOC_REG(ha, 0x60920, 0x02);
541 QLAFX00_SET_HBA_SOC_REG(ha, 0x60924, 0x02);
542 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0920, 0x02);
543 QLAFX00_SET_HBA_SOC_REG(ha, 0xf0924, 0x02);
544
545
546 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60840);
547 reg_val &= ~(1<<12);
548 QLAFX00_SET_HBA_SOC_REG(ha, 0x60840, reg_val);
549
550 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60844);
551 reg_val &= ~(1<<12);
552 QLAFX00_SET_HBA_SOC_REG(ha, 0x60844, reg_val);
553
554 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x60848);
555 reg_val &= ~(1<<12);
556 QLAFX00_SET_HBA_SOC_REG(ha, 0x60848, reg_val);
557
558 reg_val = QLAFX00_GET_HBA_SOC_REG(ha, 0x6084C);
559 reg_val &= ~(1<<12);
560 QLAFX00_SET_HBA_SOC_REG(ha, 0x6084C, reg_val);
561
562 for (i = 0; i < 100000; i++) {
563 if ((QLAFX00_GET_HBA_SOC_REG(ha, 0xd0000) & 0x10000000) == 0 &&
564 (QLAFX00_GET_HBA_SOC_REG(ha, 0x10600) & 0x1) == 0)
565 break;
566 udelay(100);
567 }
568
569
570 for (i = 0; i < 4; i++) {
571 QLAFX00_SET_HBA_SOC_REG(ha,
572 (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
573 QLAFX00_SET_HBA_SOC_REG(ha,
574 (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
575 }
576
577
578 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x011f0101));
579
580
581 QLAFX00_SET_HBA_SOC_REG(ha, 0x10610, 1);
582 QLAFX00_SET_HBA_SOC_REG(ha, 0x10600, 0);
583
584
585 for (i = 0; i < 5; i++) {
586 QLAFX00_SET_HBA_SOC_REG(ha,
587 (SOC_PWR_MANAGEMENT_PWR_DOWN_REG + 4*i), (0x0));
588 }
589
590
591 for (i = 0; i < 115; i++) {
592 QLAFX00_SET_HBA_SOC_REG(ha,
593 (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
594 }
595
596
597 for (core = 0; core < 4; core++)
598 for (i = 0; i < 8; i++)
599 QLAFX00_SET_HBA_SOC_REG(ha,
600 (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
601
602
603 for (core = 0; core < 4; core++)
604 QLAFX00_SET_HBA_SOC_REG(ha,
605 (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
606
607
608 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
609 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
610
611
612 QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
613
614
615 QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
616
617 spin_unlock_irqrestore(&ha->hardware_lock, flags);
618
619
620 for (cnt = 10; cnt; cnt--) {
621 msleep(1000);
622 barrier();
623 }
624}
625
626
627
628
629
630
631
632void
633qlafx00_soft_reset(scsi_qla_host_t *vha)
634{
635 struct qla_hw_data *ha = vha->hw;
636
637 if (unlikely(pci_channel_offline(ha->pdev) &&
638 ha->flags.pci_channel_io_perm_failure))
639 return;
640
641 ha->isp_ops->disable_intrs(ha);
642 qlafx00_soc_cpu_reset(vha);
643}
644
645
646
647
648
649
650
651int
652qlafx00_chip_diag(scsi_qla_host_t *vha)
653{
654 int rval = 0;
655 struct qla_hw_data *ha = vha->hw;
656 struct req_que *req = ha->req_q_map[0];
657
658 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
659
660 rval = qlafx00_mbx_reg_test(vha);
661 if (rval) {
662 ql_log(ql_log_warn, vha, 0x1165,
663 "Failed mailbox send register test\n");
664 } else {
665
666 rval = QLA_SUCCESS;
667 }
668 return rval;
669}
670
671void
672qlafx00_config_rings(struct scsi_qla_host *vha)
673{
674 struct qla_hw_data *ha = vha->hw;
675 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
676
677 WRT_REG_DWORD(®->req_q_in, 0);
678 WRT_REG_DWORD(®->req_q_out, 0);
679
680 WRT_REG_DWORD(®->rsp_q_in, 0);
681 WRT_REG_DWORD(®->rsp_q_out, 0);
682
683
684 RD_REG_DWORD(®->rsp_q_out);
685}
686
687char *
688qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
689{
690 struct qla_hw_data *ha = vha->hw;
691
692 if (pci_is_pcie(ha->pdev)) {
693 strcpy(str, "PCIe iSA");
694 return str;
695 }
696 return str;
697}
698
699char *
700qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
701{
702 struct qla_hw_data *ha = vha->hw;
703
704 snprintf(str, size, "%s", ha->mr.fw_version);
705 return str;
706}
707
708void
709qlafx00_enable_intrs(struct qla_hw_data *ha)
710{
711 unsigned long flags = 0;
712
713 spin_lock_irqsave(&ha->hardware_lock, flags);
714 ha->interrupts_on = 1;
715 QLAFX00_ENABLE_ICNTRL_REG(ha);
716 spin_unlock_irqrestore(&ha->hardware_lock, flags);
717}
718
719void
720qlafx00_disable_intrs(struct qla_hw_data *ha)
721{
722 unsigned long flags = 0;
723
724 spin_lock_irqsave(&ha->hardware_lock, flags);
725 ha->interrupts_on = 0;
726 QLAFX00_DISABLE_ICNTRL_REG(ha);
727 spin_unlock_irqrestore(&ha->hardware_lock, flags);
728}
729
730int
731qlafx00_abort_target(fc_port_t *fcport, uint64_t l, int tag)
732{
733 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
734}
735
736int
737qlafx00_lun_reset(fc_port_t *fcport, uint64_t l, int tag)
738{
739 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
740}
741
742int
743qlafx00_loop_reset(scsi_qla_host_t *vha)
744{
745 int ret;
746 struct fc_port *fcport;
747 struct qla_hw_data *ha = vha->hw;
748
749 if (ql2xtargetreset) {
750 list_for_each_entry(fcport, &vha->vp_fcports, list) {
751 if (fcport->port_type != FCT_TARGET)
752 continue;
753
754 ret = ha->isp_ops->target_reset(fcport, 0, 0);
755 if (ret != QLA_SUCCESS) {
756 ql_dbg(ql_dbg_taskm, vha, 0x803d,
757 "Bus Reset failed: Reset=%d "
758 "d_id=%x.\n", ret, fcport->d_id.b24);
759 }
760 }
761 }
762 return QLA_SUCCESS;
763}
764
765int
766qlafx00_iospace_config(struct qla_hw_data *ha)
767{
768 if (pci_request_selected_regions(ha->pdev, ha->bars,
769 QLA2XXX_DRIVER_NAME)) {
770 ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
771 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
772 pci_name(ha->pdev));
773 goto iospace_error_exit;
774 }
775
776
777 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
778 ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
779 "Invalid pci I/O region size (%s).\n",
780 pci_name(ha->pdev));
781 goto iospace_error_exit;
782 }
783 if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
784 ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
785 "Invalid PCI mem BAR0 region size (%s), aborting\n",
786 pci_name(ha->pdev));
787 goto iospace_error_exit;
788 }
789
790 ha->cregbase =
791 ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
792 if (!ha->cregbase) {
793 ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
794 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
795 goto iospace_error_exit;
796 }
797
798 if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
799 ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
800 "region #2 not an MMIO resource (%s), aborting\n",
801 pci_name(ha->pdev));
802 goto iospace_error_exit;
803 }
804 if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
805 ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
806 "Invalid PCI mem BAR2 region size (%s), aborting\n",
807 pci_name(ha->pdev));
808 goto iospace_error_exit;
809 }
810
811 ha->iobase =
812 ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
813 if (!ha->iobase) {
814 ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
815 "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
816 goto iospace_error_exit;
817 }
818
819
820 ha->max_req_queues = ha->max_rsp_queues = 1;
821
822 ql_log_pci(ql_log_info, ha->pdev, 0x012c,
823 "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
824 ha->bars, ha->cregbase, ha->iobase);
825
826 return 0;
827
828iospace_error_exit:
829 return -ENOMEM;
830}
831
832static void
833qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
834{
835 struct qla_hw_data *ha = vha->hw;
836 struct req_que *req = ha->req_q_map[0];
837 struct rsp_que *rsp = ha->rsp_q_map[0];
838
839 req->length_fx00 = req->length;
840 req->ring_fx00 = req->ring;
841 req->dma_fx00 = req->dma;
842
843 rsp->length_fx00 = rsp->length;
844 rsp->ring_fx00 = rsp->ring;
845 rsp->dma_fx00 = rsp->dma;
846
847 ql_dbg(ql_dbg_init, vha, 0x012d,
848 "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
849 "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
850 req->length_fx00, (u64)req->dma_fx00);
851
852 ql_dbg(ql_dbg_init, vha, 0x012e,
853 "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
854 "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
855 rsp->length_fx00, (u64)rsp->dma_fx00);
856}
857
858static int
859qlafx00_config_queues(struct scsi_qla_host *vha)
860{
861 struct qla_hw_data *ha = vha->hw;
862 struct req_que *req = ha->req_q_map[0];
863 struct rsp_que *rsp = ha->rsp_q_map[0];
864 dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
865
866 req->length = ha->req_que_len;
867 req->ring = (void __force *)ha->iobase + ha->req_que_off;
868 req->dma = bar2_hdl + ha->req_que_off;
869 if ((!req->ring) || (req->length == 0)) {
870 ql_log_pci(ql_log_info, ha->pdev, 0x012f,
871 "Unable to allocate memory for req_ring\n");
872 return QLA_FUNCTION_FAILED;
873 }
874
875 ql_dbg(ql_dbg_init, vha, 0x0130,
876 "req: %p req_ring pointer %p req len 0x%x "
877 "req off 0x%x\n, req->dma: 0x%llx",
878 req, req->ring, req->length,
879 ha->req_que_off, (u64)req->dma);
880
881 rsp->length = ha->rsp_que_len;
882 rsp->ring = (void __force *)ha->iobase + ha->rsp_que_off;
883 rsp->dma = bar2_hdl + ha->rsp_que_off;
884 if ((!rsp->ring) || (rsp->length == 0)) {
885 ql_log_pci(ql_log_info, ha->pdev, 0x0131,
886 "Unable to allocate memory for rsp_ring\n");
887 return QLA_FUNCTION_FAILED;
888 }
889
890 ql_dbg(ql_dbg_init, vha, 0x0132,
891 "rsp: %p rsp_ring pointer %p rsp len 0x%x "
892 "rsp off 0x%x, rsp->dma: 0x%llx\n",
893 rsp, rsp->ring, rsp->length,
894 ha->rsp_que_off, (u64)rsp->dma);
895
896 return QLA_SUCCESS;
897}
898
899static int
900qlafx00_init_fw_ready(scsi_qla_host_t *vha)
901{
902 int rval = 0;
903 unsigned long wtime;
904 uint16_t wait_time;
905 struct qla_hw_data *ha = vha->hw;
906 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
907 uint32_t aenmbx, aenmbx7 = 0;
908 uint32_t pseudo_aen;
909 uint32_t state[5];
910 bool done = false;
911
912
913 wait_time = 30;
914
915 pseudo_aen = RD_REG_DWORD(®->pseudoaen);
916 if (pseudo_aen == 1) {
917 aenmbx7 = RD_REG_DWORD(®->initval7);
918 ha->mbx_intr_code = MSW(aenmbx7);
919 ha->rqstq_intr_code = LSW(aenmbx7);
920 rval = qlafx00_driver_shutdown(vha, 10);
921 if (rval != QLA_SUCCESS)
922 qlafx00_soft_reset(vha);
923 }
924
925
926 wtime = jiffies + (wait_time * HZ);
927 do {
928 aenmbx = RD_REG_DWORD(®->aenmailbox0);
929 barrier();
930 ql_dbg(ql_dbg_mbx, vha, 0x0133,
931 "aenmbx: 0x%x\n", aenmbx);
932
933 switch (aenmbx) {
934 case MBA_FW_NOT_STARTED:
935 case MBA_FW_STARTING:
936 break;
937
938 case MBA_SYSTEM_ERR:
939 case MBA_REQ_TRANSFER_ERR:
940 case MBA_RSP_TRANSFER_ERR:
941 case MBA_FW_INIT_FAILURE:
942 qlafx00_soft_reset(vha);
943 break;
944
945 case MBA_FW_RESTART_CMPLT:
946
947 aenmbx7 = RD_REG_DWORD(®->aenmailbox7);
948 ha->mbx_intr_code = MSW(aenmbx7);
949 ha->rqstq_intr_code = LSW(aenmbx7);
950 ha->req_que_off = RD_REG_DWORD(®->aenmailbox1);
951 ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3);
952 ha->req_que_len = RD_REG_DWORD(®->aenmailbox5);
953 ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6);
954 WRT_REG_DWORD(®->aenmailbox0, 0);
955 RD_REG_DWORD_RELAXED(®->aenmailbox0);
956 ql_dbg(ql_dbg_init, vha, 0x0134,
957 "f/w returned mbx_intr_code: 0x%x, "
958 "rqstq_intr_code: 0x%x\n",
959 ha->mbx_intr_code, ha->rqstq_intr_code);
960 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
961 rval = QLA_SUCCESS;
962 done = true;
963 break;
964
965 default:
966 if ((aenmbx & 0xFF00) == MBA_FW_INIT_INPROGRESS)
967 break;
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985 aenmbx7 = RD_REG_DWORD(®->initval7);
986 ha->mbx_intr_code = MSW(aenmbx7);
987 ha->rqstq_intr_code = LSW(aenmbx7);
988 ha->req_que_off = RD_REG_DWORD(®->initval1);
989 ha->rsp_que_off = RD_REG_DWORD(®->initval3);
990 ha->req_que_len = RD_REG_DWORD(®->initval5);
991 ha->rsp_que_len = RD_REG_DWORD(®->initval6);
992 ql_dbg(ql_dbg_init, vha, 0x0135,
993 "f/w returned mbx_intr_code: 0x%x, "
994 "rqstq_intr_code: 0x%x\n",
995 ha->mbx_intr_code, ha->rqstq_intr_code);
996 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
997
998
999 rval = qlafx00_get_firmware_state(vha, state);
1000 if (rval != QLA_SUCCESS) {
1001
1002 break;
1003 }
1004
1005 if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
1006
1007
1008
1009 rval = QLA_SUCCESS;
1010 done = true;
1011 break;
1012 }
1013
1014
1015
1016
1017
1018 ql_dbg(ql_dbg_init, vha, 0x0136,
1019 "Sending Driver shutdown fw_state 0x%x\n",
1020 state[0]);
1021
1022 rval = qlafx00_driver_shutdown(vha, 10);
1023 if (rval != QLA_SUCCESS) {
1024 rval = QLA_FUNCTION_FAILED;
1025 break;
1026 }
1027 msleep(500);
1028
1029 wtime = jiffies + (wait_time * HZ);
1030 break;
1031 }
1032
1033 if (!done) {
1034 if (time_after_eq(jiffies, wtime)) {
1035 ql_dbg(ql_dbg_init, vha, 0x0137,
1036 "Init f/w failed: aen[7]: 0x%x\n",
1037 RD_REG_DWORD(®->aenmailbox7));
1038 rval = QLA_FUNCTION_FAILED;
1039 done = true;
1040 break;
1041 }
1042
1043 msleep(500);
1044 }
1045 } while (!done);
1046
1047 if (rval)
1048 ql_dbg(ql_dbg_init, vha, 0x0138,
1049 "%s **** FAILED ****.\n", __func__);
1050 else
1051 ql_dbg(ql_dbg_init, vha, 0x0139,
1052 "%s **** SUCCESS ****.\n", __func__);
1053
1054 return rval;
1055}
1056
1057
1058
1059
1060
1061
1062
1063int
1064qlafx00_fw_ready(scsi_qla_host_t *vha)
1065{
1066 int rval;
1067 unsigned long wtime;
1068 uint16_t wait_time;
1069 uint32_t state[5];
1070
1071 rval = QLA_SUCCESS;
1072
1073 wait_time = 10;
1074
1075
1076 wtime = jiffies + (wait_time * HZ);
1077
1078
1079 if (!vha->flags.init_done)
1080 ql_dbg(ql_dbg_init, vha, 0x013a,
1081 "Waiting for init to complete...\n");
1082
1083 do {
1084 rval = qlafx00_get_firmware_state(vha, state);
1085
1086 if (rval == QLA_SUCCESS) {
1087 if (state[0] == FSTATE_FX00_INITIALIZED) {
1088 ql_dbg(ql_dbg_init, vha, 0x013b,
1089 "fw_state=%x\n", state[0]);
1090 rval = QLA_SUCCESS;
1091 break;
1092 }
1093 }
1094 rval = QLA_FUNCTION_FAILED;
1095
1096 if (time_after_eq(jiffies, wtime))
1097 break;
1098
1099
1100 msleep(500);
1101
1102 ql_dbg(ql_dbg_init, vha, 0x013c,
1103 "fw_state=%x curr time=%lx.\n", state[0], jiffies);
1104 } while (1);
1105
1106
1107 if (rval)
1108 ql_dbg(ql_dbg_init, vha, 0x013d,
1109 "Firmware ready **** FAILED ****.\n");
1110 else
1111 ql_dbg(ql_dbg_init, vha, 0x013e,
1112 "Firmware ready **** SUCCESS ****.\n");
1113
1114 return rval;
1115}
1116
1117static int
1118qlafx00_find_all_targets(scsi_qla_host_t *vha,
1119 struct list_head *new_fcports)
1120{
1121 int rval;
1122 uint16_t tgt_id;
1123 fc_port_t *fcport, *new_fcport;
1124 int found;
1125 struct qla_hw_data *ha = vha->hw;
1126
1127 rval = QLA_SUCCESS;
1128
1129 if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1130 return QLA_FUNCTION_FAILED;
1131
1132 if ((atomic_read(&vha->loop_down_timer) ||
1133 STATE_TRANSITION(vha))) {
1134 atomic_set(&vha->loop_down_timer, 0);
1135 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1136 return QLA_FUNCTION_FAILED;
1137 }
1138
1139 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
1140 "Listing Target bit map...\n");
1141 ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
1142 0x2089, (uint8_t *)ha->gid_list, 32);
1143
1144
1145 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1146 if (new_fcport == NULL)
1147 return QLA_MEMORY_ALLOC_FAILED;
1148
1149 for_each_set_bit(tgt_id, (void *)ha->gid_list,
1150 QLAFX00_TGT_NODE_LIST_SIZE) {
1151
1152
1153 new_fcport->tgt_id = tgt_id;
1154 rval = qlafx00_fx_disc(vha, new_fcport,
1155 FXDISC_GET_TGT_NODE_INFO);
1156 if (rval != QLA_SUCCESS) {
1157 ql_log(ql_log_warn, vha, 0x208a,
1158 "Target info scan failed -- assuming zero-entry "
1159 "result...\n");
1160 continue;
1161 }
1162
1163
1164 found = 0;
1165 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1166 if (memcmp(new_fcport->port_name,
1167 fcport->port_name, WWN_SIZE))
1168 continue;
1169
1170 found++;
1171
1172
1173
1174
1175
1176 if (fcport->tgt_id == new_fcport->tgt_id &&
1177 atomic_read(&fcport->state) == FCS_ONLINE)
1178 break;
1179
1180
1181
1182
1183 ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
1184 "TGT-ID Change(%s): Present tgt id: "
1185 "0x%x state: 0x%x "
1186 "wwnn = %llx wwpn = %llx.\n",
1187 __func__, fcport->tgt_id,
1188 atomic_read(&fcport->state),
1189 (unsigned long long)wwn_to_u64(fcport->node_name),
1190 (unsigned long long)wwn_to_u64(fcport->port_name));
1191
1192 ql_log(ql_log_info, vha, 0x208c,
1193 "TGT-ID Announce(%s): Discovered tgt "
1194 "id 0x%x wwnn = %llx "
1195 "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
1196 (unsigned long long)
1197 wwn_to_u64(new_fcport->node_name),
1198 (unsigned long long)
1199 wwn_to_u64(new_fcport->port_name));
1200
1201 if (atomic_read(&fcport->state) != FCS_ONLINE) {
1202 fcport->old_tgt_id = fcport->tgt_id;
1203 fcport->tgt_id = new_fcport->tgt_id;
1204 ql_log(ql_log_info, vha, 0x208d,
1205 "TGT-ID: New fcport Added: %p\n", fcport);
1206 qla2x00_update_fcport(vha, fcport);
1207 } else {
1208 ql_log(ql_log_info, vha, 0x208e,
1209 " Existing TGT-ID %x did not get "
1210 " offline event from firmware.\n",
1211 fcport->old_tgt_id);
1212 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1213 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1214 kfree(new_fcport);
1215 return rval;
1216 }
1217 break;
1218 }
1219
1220 if (found)
1221 continue;
1222
1223
1224 list_add_tail(&new_fcport->list, new_fcports);
1225
1226
1227 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1228 if (new_fcport == NULL)
1229 return QLA_MEMORY_ALLOC_FAILED;
1230 }
1231
1232 kfree(new_fcport);
1233 return rval;
1234}
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247static int
1248qlafx00_configure_all_targets(scsi_qla_host_t *vha)
1249{
1250 int rval;
1251 fc_port_t *fcport, *rmptemp;
1252 LIST_HEAD(new_fcports);
1253
1254 rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1255 FXDISC_GET_TGT_NODE_LIST);
1256 if (rval != QLA_SUCCESS) {
1257 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1258 return rval;
1259 }
1260
1261 rval = qlafx00_find_all_targets(vha, &new_fcports);
1262 if (rval != QLA_SUCCESS) {
1263 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1264 return rval;
1265 }
1266
1267
1268
1269
1270 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1271 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1272 break;
1273
1274 if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
1275 if (fcport->port_type != FCT_INITIATOR)
1276 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1277 }
1278 }
1279
1280
1281
1282
1283 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1284 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
1285 break;
1286
1287 qla2x00_update_fcport(vha, fcport);
1288 list_move_tail(&fcport->list, &vha->vp_fcports);
1289 ql_log(ql_log_info, vha, 0x208f,
1290 "Attach new target id 0x%x wwnn = %llx "
1291 "wwpn = %llx.\n",
1292 fcport->tgt_id,
1293 (unsigned long long)wwn_to_u64(fcport->node_name),
1294 (unsigned long long)wwn_to_u64(fcport->port_name));
1295 }
1296
1297
1298 list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
1299 list_del(&fcport->list);
1300 kfree(fcport);
1301 }
1302
1303 return rval;
1304}
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318int
1319qlafx00_configure_devices(scsi_qla_host_t *vha)
1320{
1321 int rval;
1322 unsigned long flags;
1323 rval = QLA_SUCCESS;
1324
1325 flags = vha->dpc_flags;
1326
1327 ql_dbg(ql_dbg_disc, vha, 0x2090,
1328 "Configure devices -- dpc flags =0x%lx\n", flags);
1329
1330 rval = qlafx00_configure_all_targets(vha);
1331
1332 if (rval == QLA_SUCCESS) {
1333 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1334 rval = QLA_FUNCTION_FAILED;
1335 } else {
1336 atomic_set(&vha->loop_state, LOOP_READY);
1337 ql_log(ql_log_info, vha, 0x2091,
1338 "Device Ready\n");
1339 }
1340 }
1341
1342 if (rval) {
1343 ql_dbg(ql_dbg_disc, vha, 0x2092,
1344 "%s *** FAILED ***.\n", __func__);
1345 } else {
1346 ql_dbg(ql_dbg_disc, vha, 0x2093,
1347 "%s: exiting normally.\n", __func__);
1348 }
1349 return rval;
1350}
1351
1352static void
1353qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha, bool critemp)
1354{
1355 struct qla_hw_data *ha = vha->hw;
1356 fc_port_t *fcport;
1357
1358 vha->flags.online = 0;
1359 ha->mr.fw_hbt_en = 0;
1360
1361 if (!critemp) {
1362 ha->flags.chip_reset_done = 0;
1363 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1364 vha->qla_stats.total_isp_aborts++;
1365 ql_log(ql_log_info, vha, 0x013f,
1366 "Performing ISP error recovery - ha = %p.\n", ha);
1367 ha->isp_ops->reset_chip(vha);
1368 }
1369
1370 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
1371 atomic_set(&vha->loop_state, LOOP_DOWN);
1372 atomic_set(&vha->loop_down_timer,
1373 QLAFX00_LOOP_DOWN_TIME);
1374 } else {
1375 if (!atomic_read(&vha->loop_down_timer))
1376 atomic_set(&vha->loop_down_timer,
1377 QLAFX00_LOOP_DOWN_TIME);
1378 }
1379
1380
1381 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1382 fcport->flags = 0;
1383 if (atomic_read(&fcport->state) == FCS_ONLINE)
1384 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1385 }
1386
1387 if (!ha->flags.eeh_busy) {
1388 if (critemp) {
1389 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
1390 } else {
1391
1392 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
1393 }
1394 }
1395
1396 qla2x00_free_irqs(vha);
1397 if (critemp)
1398 set_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags);
1399 else
1400 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1401
1402
1403 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1404
1405 ql_log(ql_log_info, vha, 0x0140,
1406 "%s Done done - ha=%p.\n", __func__, ha);
1407}
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418void
1419qlafx00_init_response_q_entries(struct rsp_que *rsp)
1420{
1421 uint16_t cnt;
1422 response_t *pkt;
1423
1424 rsp->ring_ptr = rsp->ring;
1425 rsp->ring_index = 0;
1426 rsp->status_srb = NULL;
1427 pkt = rsp->ring_ptr;
1428 for (cnt = 0; cnt < rsp->length; cnt++) {
1429 pkt->signature = RESPONSE_PROCESSED;
1430 WRT_REG_DWORD((void __force __iomem *)&pkt->signature,
1431 RESPONSE_PROCESSED);
1432 pkt++;
1433 }
1434}
1435
1436int
1437qlafx00_rescan_isp(scsi_qla_host_t *vha)
1438{
1439 uint32_t status = QLA_FUNCTION_FAILED;
1440 struct qla_hw_data *ha = vha->hw;
1441 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1442 uint32_t aenmbx7;
1443
1444 qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
1445
1446 aenmbx7 = RD_REG_DWORD(®->aenmailbox7);
1447 ha->mbx_intr_code = MSW(aenmbx7);
1448 ha->rqstq_intr_code = LSW(aenmbx7);
1449 ha->req_que_off = RD_REG_DWORD(®->aenmailbox1);
1450 ha->rsp_que_off = RD_REG_DWORD(®->aenmailbox3);
1451 ha->req_que_len = RD_REG_DWORD(®->aenmailbox5);
1452 ha->rsp_que_len = RD_REG_DWORD(®->aenmailbox6);
1453
1454 ql_dbg(ql_dbg_disc, vha, 0x2094,
1455 "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
1456 " Req que offset 0x%x Rsp que offset 0x%x\n",
1457 ha->mbx_intr_code, ha->rqstq_intr_code,
1458 ha->req_que_off, ha->rsp_que_len);
1459
1460
1461 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1462
1463 status = qla2x00_init_rings(vha);
1464 if (!status) {
1465 vha->flags.online = 1;
1466
1467
1468 if ((vha->device_flags & DFLG_NO_CABLE))
1469 status = 0;
1470
1471 if (qlafx00_fx_disc(vha,
1472 &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
1473 ql_dbg(ql_dbg_disc, vha, 0x2095,
1474 "failed to register host info\n");
1475 }
1476 scsi_unblock_requests(vha->host);
1477 return status;
1478}
1479
1480void
1481qlafx00_timer_routine(scsi_qla_host_t *vha)
1482{
1483 struct qla_hw_data *ha = vha->hw;
1484 uint32_t fw_heart_beat;
1485 uint32_t aenmbx0;
1486 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
1487 uint32_t tempc;
1488
1489
1490 if (ha->mr.fw_hbt_cnt)
1491 ha->mr.fw_hbt_cnt--;
1492 else {
1493 if ((!ha->flags.mr_reset_hdlr_active) &&
1494 (!test_bit(UNLOADING, &vha->dpc_flags)) &&
1495 (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
1496 (ha->mr.fw_hbt_en)) {
1497 fw_heart_beat = RD_REG_DWORD(®->fwheartbeat);
1498 if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
1499 ha->mr.old_fw_hbt_cnt = fw_heart_beat;
1500 ha->mr.fw_hbt_miss_cnt = 0;
1501 } else {
1502 ha->mr.fw_hbt_miss_cnt++;
1503 if (ha->mr.fw_hbt_miss_cnt ==
1504 QLAFX00_HEARTBEAT_MISS_CNT) {
1505 set_bit(ISP_ABORT_NEEDED,
1506 &vha->dpc_flags);
1507 qla2xxx_wake_dpc(vha);
1508 ha->mr.fw_hbt_miss_cnt = 0;
1509 }
1510 }
1511 }
1512 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
1513 }
1514
1515 if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
1516
1517 aenmbx0 = RD_REG_DWORD(®->aenmailbox0);
1518 if (ha->mr.fw_reset_timer_exp) {
1519 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1520 qla2xxx_wake_dpc(vha);
1521 ha->mr.fw_reset_timer_exp = 0;
1522 } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
1523
1524 set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
1525 clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1526 qla2xxx_wake_dpc(vha);
1527 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1528 } else if ((aenmbx0 == MBA_FW_STARTING) &&
1529 (!ha->mr.fw_hbt_en)) {
1530 ha->mr.fw_hbt_en = 1;
1531 } else if (!ha->mr.fw_reset_timer_tick) {
1532 if (aenmbx0 == ha->mr.old_aenmbx0_state)
1533 ha->mr.fw_reset_timer_exp = 1;
1534 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1535 } else if (aenmbx0 == 0xFFFFFFFF) {
1536 uint32_t data0, data1;
1537
1538 data0 = QLAFX00_RD_REG(ha,
1539 QLAFX00_BAR1_BASE_ADDR_REG);
1540 data1 = QLAFX00_RD_REG(ha,
1541 QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
1542
1543 data0 &= 0xffff0000;
1544 data1 &= 0x0000ffff;
1545
1546 QLAFX00_WR_REG(ha,
1547 QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
1548 (data0 | data1));
1549 } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
1550 ha->mr.fw_reset_timer_tick =
1551 QLAFX00_MAX_RESET_INTERVAL;
1552 } else if (aenmbx0 == MBA_FW_RESET_FCT) {
1553 ha->mr.fw_reset_timer_tick =
1554 QLAFX00_MAX_RESET_INTERVAL;
1555 }
1556 if (ha->mr.old_aenmbx0_state != aenmbx0) {
1557 ha->mr.old_aenmbx0_state = aenmbx0;
1558 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
1559 }
1560 ha->mr.fw_reset_timer_tick--;
1561 }
1562 if (test_bit(FX00_CRITEMP_RECOVERY, &vha->dpc_flags)) {
1563
1564
1565
1566
1567 if (ha->mr.fw_critemp_timer_tick == 0) {
1568 tempc = QLAFX00_GET_TEMPERATURE(ha);
1569 ql_dbg(ql_dbg_timer, vha, 0x6012,
1570 "ISPFx00(%s): Critical temp timer, "
1571 "current SOC temperature: %d\n",
1572 __func__, tempc);
1573 if (tempc < ha->mr.critical_temperature) {
1574 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1575 clear_bit(FX00_CRITEMP_RECOVERY,
1576 &vha->dpc_flags);
1577 qla2xxx_wake_dpc(vha);
1578 }
1579 ha->mr.fw_critemp_timer_tick =
1580 QLAFX00_CRITEMP_INTERVAL;
1581 } else {
1582 ha->mr.fw_critemp_timer_tick--;
1583 }
1584 }
1585 if (ha->mr.host_info_resend) {
1586
1587
1588
1589
1590 if (ha->mr.hinfo_resend_timer_tick == 0) {
1591 ha->mr.host_info_resend = false;
1592 set_bit(FX00_HOST_INFO_RESEND, &vha->dpc_flags);
1593 ha->mr.hinfo_resend_timer_tick =
1594 QLAFX00_HINFO_RESEND_INTERVAL;
1595 qla2xxx_wake_dpc(vha);
1596 } else {
1597 ha->mr.hinfo_resend_timer_tick--;
1598 }
1599 }
1600
1601}
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613int
1614qlafx00_reset_initialize(scsi_qla_host_t *vha)
1615{
1616 struct qla_hw_data *ha = vha->hw;
1617
1618 if (vha->device_flags & DFLG_DEV_FAILED) {
1619 ql_dbg(ql_dbg_init, vha, 0x0142,
1620 "Device in failed state\n");
1621 return QLA_SUCCESS;
1622 }
1623
1624 ha->flags.mr_reset_hdlr_active = 1;
1625
1626 if (vha->flags.online) {
1627 scsi_block_requests(vha->host);
1628 qlafx00_abort_isp_cleanup(vha, false);
1629 }
1630
1631 ql_log(ql_log_info, vha, 0x0143,
1632 "(%s): succeeded.\n", __func__);
1633 ha->flags.mr_reset_hdlr_active = 0;
1634 return QLA_SUCCESS;
1635}
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647int
1648qlafx00_abort_isp(scsi_qla_host_t *vha)
1649{
1650 struct qla_hw_data *ha = vha->hw;
1651
1652 if (vha->flags.online) {
1653 if (unlikely(pci_channel_offline(ha->pdev) &&
1654 ha->flags.pci_channel_io_perm_failure)) {
1655 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1656 return QLA_SUCCESS;
1657 }
1658
1659 scsi_block_requests(vha->host);
1660 qlafx00_abort_isp_cleanup(vha, false);
1661 } else {
1662 scsi_block_requests(vha->host);
1663 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1664 vha->qla_stats.total_isp_aborts++;
1665 ha->isp_ops->reset_chip(vha);
1666 set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
1667
1668 QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
1669 }
1670
1671 ql_log(ql_log_info, vha, 0x0145,
1672 "(%s): succeeded.\n", __func__);
1673
1674 return QLA_SUCCESS;
1675}
1676
1677static inline fc_port_t*
1678qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
1679{
1680 fc_port_t *fcport;
1681
1682
1683 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1684 if (fcport->tgt_id == tgt_id) {
1685 ql_dbg(ql_dbg_async, vha, 0x5072,
1686 "Matching fcport(%p) found with TGT-ID: 0x%x "
1687 "and Remote TGT_ID: 0x%x\n",
1688 fcport, fcport->tgt_id, tgt_id);
1689 return fcport;
1690 }
1691 }
1692 return NULL;
1693}
1694
1695static void
1696qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
1697{
1698 fc_port_t *fcport;
1699
1700 ql_log(ql_log_info, vha, 0x5073,
1701 "Detach TGT-ID: 0x%x\n", tgt_id);
1702
1703 fcport = qlafx00_get_fcport(vha, tgt_id);
1704 if (!fcport)
1705 return;
1706
1707 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1708
1709 return;
1710}
1711
1712int
1713qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
1714{
1715 int rval = 0;
1716 uint32_t aen_code, aen_data;
1717
1718 aen_code = FCH_EVT_VENDOR_UNIQUE;
1719 aen_data = evt->u.aenfx.evtcode;
1720
1721 switch (evt->u.aenfx.evtcode) {
1722 case QLAFX00_MBA_PORT_UPDATE:
1723 if (evt->u.aenfx.mbx[1] == 0) {
1724 if (evt->u.aenfx.mbx[2] == 1) {
1725 if (!vha->flags.fw_tgt_reported)
1726 vha->flags.fw_tgt_reported = 1;
1727 atomic_set(&vha->loop_down_timer, 0);
1728 atomic_set(&vha->loop_state, LOOP_UP);
1729 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1730 qla2xxx_wake_dpc(vha);
1731 } else if (evt->u.aenfx.mbx[2] == 2) {
1732 qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
1733 }
1734 } else if (evt->u.aenfx.mbx[1] == 0xffff) {
1735 if (evt->u.aenfx.mbx[2] == 1) {
1736 if (!vha->flags.fw_tgt_reported)
1737 vha->flags.fw_tgt_reported = 1;
1738 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1739 } else if (evt->u.aenfx.mbx[2] == 2) {
1740 vha->device_flags |= DFLG_NO_CABLE;
1741 qla2x00_mark_all_devices_lost(vha, 1);
1742 }
1743 }
1744 break;
1745 case QLAFX00_MBA_LINK_UP:
1746 aen_code = FCH_EVT_LINKUP;
1747 aen_data = 0;
1748 break;
1749 case QLAFX00_MBA_LINK_DOWN:
1750 aen_code = FCH_EVT_LINKDOWN;
1751 aen_data = 0;
1752 break;
1753 case QLAFX00_MBA_TEMP_CRIT:
1754 ql_log(ql_log_info, vha, 0x5082,
1755 "Process critical temperature event "
1756 "aenmb[0]: %x\n",
1757 evt->u.aenfx.evtcode);
1758 scsi_block_requests(vha->host);
1759 qlafx00_abort_isp_cleanup(vha, true);
1760 scsi_unblock_requests(vha->host);
1761 break;
1762 }
1763
1764 fc_host_post_event(vha->host, fc_get_event_number(),
1765 aen_code, aen_data);
1766
1767 return rval;
1768}
1769
1770static void
1771qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
1772{
1773 u64 port_name = 0, node_name = 0;
1774
1775 port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
1776 node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
1777
1778 fc_host_node_name(vha->host) = node_name;
1779 fc_host_port_name(vha->host) = port_name;
1780 if (!pinfo->port_type)
1781 vha->hw->current_topology = ISP_CFG_F;
1782 if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
1783 atomic_set(&vha->loop_state, LOOP_READY);
1784 else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
1785 atomic_set(&vha->loop_state, LOOP_DOWN);
1786 vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
1787}
1788
1789static void
1790qla2x00_fxdisc_iocb_timeout(void *data)
1791{
1792 srb_t *sp = data;
1793 struct srb_iocb *lio = &sp->u.iocb_cmd;
1794
1795 complete(&lio->u.fxiocb.fxiocb_comp);
1796}
1797
1798static void
1799qla2x00_fxdisc_sp_done(void *ptr, int res)
1800{
1801 srb_t *sp = ptr;
1802 struct srb_iocb *lio = &sp->u.iocb_cmd;
1803
1804 complete(&lio->u.fxiocb.fxiocb_comp);
1805}
1806
1807int
1808qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
1809{
1810 srb_t *sp;
1811 struct srb_iocb *fdisc;
1812 int rval = QLA_FUNCTION_FAILED;
1813 struct qla_hw_data *ha = vha->hw;
1814 struct host_system_info *phost_info;
1815 struct register_host_info *preg_hsi;
1816 struct new_utsname *p_sysid = NULL;
1817
1818 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1819 if (!sp)
1820 goto done;
1821
1822 sp->type = SRB_FXIOCB_DCMD;
1823 sp->name = "fxdisc";
1824 qla2x00_init_timer(sp, FXDISC_TIMEOUT);
1825
1826 fdisc = &sp->u.iocb_cmd;
1827 switch (fx_type) {
1828 case FXDISC_GET_CONFIG_INFO:
1829 fdisc->u.fxiocb.flags =
1830 SRB_FXDISC_RESP_DMA_VALID;
1831 fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
1832 break;
1833 case FXDISC_GET_PORT_INFO:
1834 fdisc->u.fxiocb.flags =
1835 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1836 fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
1837 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
1838 break;
1839 case FXDISC_GET_TGT_NODE_INFO:
1840 fdisc->u.fxiocb.flags =
1841 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1842 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
1843 fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
1844 break;
1845 case FXDISC_GET_TGT_NODE_LIST:
1846 fdisc->u.fxiocb.flags =
1847 SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
1848 fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
1849 break;
1850 case FXDISC_REG_HOST_INFO:
1851 fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
1852 fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
1853 p_sysid = utsname();
1854 if (!p_sysid) {
1855 ql_log(ql_log_warn, vha, 0x303c,
1856 "Not able to get the system information\n");
1857 goto done_free_sp;
1858 }
1859 break;
1860 case FXDISC_ABORT_IOCTL:
1861 default:
1862 break;
1863 }
1864
1865 if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
1866 fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
1867 fdisc->u.fxiocb.req_len,
1868 &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
1869 if (!fdisc->u.fxiocb.req_addr)
1870 goto done_free_sp;
1871
1872 if (fx_type == FXDISC_REG_HOST_INFO) {
1873 preg_hsi = (struct register_host_info *)
1874 fdisc->u.fxiocb.req_addr;
1875 phost_info = &preg_hsi->hsi;
1876 memset(preg_hsi, 0, sizeof(struct register_host_info));
1877 phost_info->os_type = OS_TYPE_LINUX;
1878 strncpy(phost_info->sysname,
1879 p_sysid->sysname, SYSNAME_LENGTH);
1880 strncpy(phost_info->nodename,
1881 p_sysid->nodename, NODENAME_LENGTH);
1882 if (!strcmp(phost_info->nodename, "(none)"))
1883 ha->mr.host_info_resend = true;
1884 strncpy(phost_info->release,
1885 p_sysid->release, RELEASE_LENGTH);
1886 strncpy(phost_info->version,
1887 p_sysid->version, VERSION_LENGTH);
1888 strncpy(phost_info->machine,
1889 p_sysid->machine, MACHINE_LENGTH);
1890 strncpy(phost_info->domainname,
1891 p_sysid->domainname, DOMNAME_LENGTH);
1892 strncpy(phost_info->hostdriver,
1893 QLA2XXX_VERSION, VERSION_LENGTH);
1894 preg_hsi->utc = (uint64_t)ktime_get_real_seconds();
1895 ql_dbg(ql_dbg_init, vha, 0x0149,
1896 "ISP%04X: Host registration with firmware\n",
1897 ha->pdev->device);
1898 ql_dbg(ql_dbg_init, vha, 0x014a,
1899 "os_type = '%d', sysname = '%s', nodname = '%s'\n",
1900 phost_info->os_type,
1901 phost_info->sysname,
1902 phost_info->nodename);
1903 ql_dbg(ql_dbg_init, vha, 0x014b,
1904 "release = '%s', version = '%s'\n",
1905 phost_info->release,
1906 phost_info->version);
1907 ql_dbg(ql_dbg_init, vha, 0x014c,
1908 "machine = '%s' "
1909 "domainname = '%s', hostdriver = '%s'\n",
1910 phost_info->machine,
1911 phost_info->domainname,
1912 phost_info->hostdriver);
1913 ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
1914 (uint8_t *)phost_info,
1915 sizeof(struct host_system_info));
1916 }
1917 }
1918
1919 if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
1920 fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
1921 fdisc->u.fxiocb.rsp_len,
1922 &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
1923 if (!fdisc->u.fxiocb.rsp_addr)
1924 goto done_unmap_req;
1925 }
1926
1927 fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
1928 fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
1929 sp->done = qla2x00_fxdisc_sp_done;
1930
1931 rval = qla2x00_start_sp(sp);
1932 if (rval != QLA_SUCCESS)
1933 goto done_unmap_dma;
1934
1935 wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
1936
1937 if (fx_type == FXDISC_GET_CONFIG_INFO) {
1938 struct config_info_data *pinfo =
1939 (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
1940 strcpy(vha->hw->model_number, pinfo->model_num);
1941 strcpy(vha->hw->model_desc, pinfo->model_description);
1942 memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
1943 sizeof(vha->hw->mr.symbolic_name));
1944 memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
1945 sizeof(vha->hw->mr.serial_num));
1946 memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
1947 sizeof(vha->hw->mr.hw_version));
1948 memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
1949 sizeof(vha->hw->mr.fw_version));
1950 strim(vha->hw->mr.fw_version);
1951 memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
1952 sizeof(vha->hw->mr.uboot_version));
1953 memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
1954 sizeof(vha->hw->mr.fru_serial_num));
1955 vha->hw->mr.critical_temperature =
1956 (pinfo->nominal_temp_value) ?
1957 pinfo->nominal_temp_value : QLAFX00_CRITEMP_THRSHLD;
1958 ha->mr.extended_io_enabled = (pinfo->enabled_capabilities &
1959 QLAFX00_EXTENDED_IO_EN_MASK) != 0;
1960 } else if (fx_type == FXDISC_GET_PORT_INFO) {
1961 struct port_info_data *pinfo =
1962 (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
1963 memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
1964 memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
1965 vha->d_id.b.domain = pinfo->port_id[0];
1966 vha->d_id.b.area = pinfo->port_id[1];
1967 vha->d_id.b.al_pa = pinfo->port_id[2];
1968 qlafx00_update_host_attr(vha, pinfo);
1969 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
1970 (uint8_t *)pinfo, 16);
1971 } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
1972 struct qlafx00_tgt_node_info *pinfo =
1973 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1974 memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
1975 memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
1976 fcport->port_type = FCT_TARGET;
1977 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
1978 (uint8_t *)pinfo, 16);
1979 } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
1980 struct qlafx00_tgt_node_info *pinfo =
1981 (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
1982 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
1983 (uint8_t *)pinfo, 16);
1984 memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
1985 } else if (fx_type == FXDISC_ABORT_IOCTL)
1986 fdisc->u.fxiocb.result =
1987 (fdisc->u.fxiocb.result ==
1988 cpu_to_le32(QLAFX00_IOCTL_ICOB_ABORT_SUCCESS)) ?
1989 cpu_to_le32(QLA_SUCCESS) : cpu_to_le32(QLA_FUNCTION_FAILED);
1990
1991 rval = le32_to_cpu(fdisc->u.fxiocb.result);
1992
1993done_unmap_dma:
1994 if (fdisc->u.fxiocb.rsp_addr)
1995 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
1996 fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
1997
1998done_unmap_req:
1999 if (fdisc->u.fxiocb.req_addr)
2000 dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
2001 fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
2002done_free_sp:
2003 sp->free(sp);
2004done:
2005 return rval;
2006}
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018int
2019qlafx00_initialize_adapter(scsi_qla_host_t *vha)
2020{
2021 int rval;
2022 struct qla_hw_data *ha = vha->hw;
2023 uint32_t tempc;
2024
2025
2026 vha->flags.online = 0;
2027 ha->flags.chip_reset_done = 0;
2028 vha->flags.reset_active = 0;
2029 ha->flags.pci_channel_io_perm_failure = 0;
2030 ha->flags.eeh_busy = 0;
2031 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2032 atomic_set(&vha->loop_state, LOOP_DOWN);
2033 vha->device_flags = DFLG_NO_CABLE;
2034 vha->dpc_flags = 0;
2035 vha->flags.management_server_logged_in = 0;
2036 ha->isp_abort_cnt = 0;
2037 ha->beacon_blink_led = 0;
2038
2039 set_bit(0, ha->req_qid_map);
2040 set_bit(0, ha->rsp_qid_map);
2041
2042 ql_dbg(ql_dbg_init, vha, 0x0147,
2043 "Configuring PCI space...\n");
2044
2045 rval = ha->isp_ops->pci_config(vha);
2046 if (rval) {
2047 ql_log(ql_log_warn, vha, 0x0148,
2048 "Unable to configure PCI space.\n");
2049 return rval;
2050 }
2051
2052 rval = qlafx00_init_fw_ready(vha);
2053 if (rval != QLA_SUCCESS)
2054 return rval;
2055
2056 qlafx00_save_queue_ptrs(vha);
2057
2058 rval = qlafx00_config_queues(vha);
2059 if (rval != QLA_SUCCESS)
2060 return rval;
2061
2062
2063
2064
2065
2066 rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
2067 if (rval != QLA_SUCCESS)
2068 return rval;
2069
2070 rval = qla2x00_init_rings(vha);
2071 ha->flags.chip_reset_done = 1;
2072
2073 tempc = QLAFX00_GET_TEMPERATURE(ha);
2074 ql_dbg(ql_dbg_init, vha, 0x0152,
2075 "ISPFx00(%s): Critical temp timer, current SOC temperature: 0x%x\n",
2076 __func__, tempc);
2077
2078 return rval;
2079}
2080
2081uint32_t
2082qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
2083 char *buf)
2084{
2085 scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
2086 int rval = QLA_FUNCTION_FAILED;
2087 uint32_t state[1];
2088
2089 if (qla2x00_reset_active(vha))
2090 ql_log(ql_log_warn, vha, 0x70ce,
2091 "ISP reset active.\n");
2092 else if (!vha->hw->flags.eeh_busy) {
2093 rval = qlafx00_get_firmware_state(vha, state);
2094 }
2095 if (rval != QLA_SUCCESS)
2096 memset(state, -1, sizeof(state));
2097
2098 return state[0];
2099}
2100
2101void
2102qlafx00_get_host_speed(struct Scsi_Host *shost)
2103{
2104 struct qla_hw_data *ha = ((struct scsi_qla_host *)
2105 (shost_priv(shost)))->hw;
2106 u32 speed = FC_PORTSPEED_UNKNOWN;
2107
2108 switch (ha->link_data_rate) {
2109 case QLAFX00_PORT_SPEED_2G:
2110 speed = FC_PORTSPEED_2GBIT;
2111 break;
2112 case QLAFX00_PORT_SPEED_4G:
2113 speed = FC_PORTSPEED_4GBIT;
2114 break;
2115 case QLAFX00_PORT_SPEED_8G:
2116 speed = FC_PORTSPEED_8GBIT;
2117 break;
2118 case QLAFX00_PORT_SPEED_10G:
2119 speed = FC_PORTSPEED_10GBIT;
2120 break;
2121 }
2122 fc_host_speed(shost) = speed;
2123}
2124
2125
2126
2127static inline void
2128qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
2129 uint32_t sense_len, struct rsp_que *rsp, int res)
2130{
2131 struct scsi_qla_host *vha = sp->vha;
2132 struct scsi_cmnd *cp = GET_CMD_SP(sp);
2133 uint32_t track_sense_len;
2134
2135 SET_FW_SENSE_LEN(sp, sense_len);
2136
2137 if (sense_len >= SCSI_SENSE_BUFFERSIZE)
2138 sense_len = SCSI_SENSE_BUFFERSIZE;
2139
2140 SET_CMD_SENSE_LEN(sp, sense_len);
2141 SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
2142 track_sense_len = sense_len;
2143
2144 if (sense_len > par_sense_len)
2145 sense_len = par_sense_len;
2146
2147 memcpy(cp->sense_buffer, sense_data, sense_len);
2148
2149 SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
2150
2151 SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
2152 track_sense_len -= sense_len;
2153 SET_CMD_SENSE_LEN(sp, track_sense_len);
2154
2155 ql_dbg(ql_dbg_io, vha, 0x304d,
2156 "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
2157 sense_len, par_sense_len, track_sense_len);
2158 if (GET_FW_SENSE_LEN(sp) > 0) {
2159 rsp->status_srb = sp;
2160 cp->result = res;
2161 }
2162
2163 if (sense_len) {
2164 ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
2165 "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
2166 sp->vha->host_no, cp->device->id, cp->device->lun,
2167 cp);
2168 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
2169 cp->sense_buffer, sense_len);
2170 }
2171}
2172
2173static void
2174qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2175 struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
2176 __le16 sstatus, __le16 cpstatus)
2177{
2178 struct srb_iocb *tmf;
2179
2180 tmf = &sp->u.iocb_cmd;
2181 if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
2182 (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
2183 cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
2184 tmf->u.tmf.comp_status = cpstatus;
2185 sp->done(sp, 0);
2186}
2187
2188static void
2189qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
2190 struct abort_iocb_entry_fx00 *pkt)
2191{
2192 const char func[] = "ABT_IOCB";
2193 srb_t *sp;
2194 struct srb_iocb *abt;
2195
2196 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2197 if (!sp)
2198 return;
2199
2200 abt = &sp->u.iocb_cmd;
2201 abt->u.abt.comp_status = pkt->tgt_id_sts;
2202 sp->done(sp, 0);
2203}
2204
2205static void
2206qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
2207 struct ioctl_iocb_entry_fx00 *pkt)
2208{
2209 const char func[] = "IOSB_IOCB";
2210 srb_t *sp;
2211 struct bsg_job *bsg_job;
2212 struct fc_bsg_reply *bsg_reply;
2213 struct srb_iocb *iocb_job;
2214 int res;
2215 struct qla_mt_iocb_rsp_fx00 fstatus;
2216 uint8_t *fw_sts_ptr;
2217
2218 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2219 if (!sp)
2220 return;
2221
2222 if (sp->type == SRB_FXIOCB_DCMD) {
2223 iocb_job = &sp->u.iocb_cmd;
2224 iocb_job->u.fxiocb.seq_number = pkt->seq_no;
2225 iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
2226 iocb_job->u.fxiocb.result = pkt->status;
2227 if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
2228 iocb_job->u.fxiocb.req_data =
2229 pkt->dataword_r;
2230 } else {
2231 bsg_job = sp->u.bsg_job;
2232 bsg_reply = bsg_job->reply;
2233
2234 memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
2235
2236 fstatus.reserved_1 = pkt->reserved_0;
2237 fstatus.func_type = pkt->comp_func_num;
2238 fstatus.ioctl_flags = pkt->fw_iotcl_flags;
2239 fstatus.ioctl_data = pkt->dataword_r;
2240 fstatus.adapid = pkt->adapid;
2241 fstatus.reserved_2 = pkt->dataword_r_extra;
2242 fstatus.res_count = pkt->residuallen;
2243 fstatus.status = pkt->status;
2244 fstatus.seq_number = pkt->seq_no;
2245 memcpy(fstatus.reserved_3,
2246 pkt->reserved_2, 20 * sizeof(uint8_t));
2247
2248 fw_sts_ptr = bsg_job->reply + sizeof(struct fc_bsg_reply);
2249
2250 memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
2251 sizeof(struct qla_mt_iocb_rsp_fx00));
2252 bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
2253 sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
2254
2255 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2256 sp->fcport->vha, 0x5080,
2257 (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
2258
2259 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
2260 sp->fcport->vha, 0x5074,
2261 (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
2262
2263 res = bsg_reply->result = DID_OK << 16;
2264 bsg_reply->reply_payload_rcv_len =
2265 bsg_job->reply_payload.payload_len;
2266 }
2267 sp->done(sp, res);
2268}
2269
2270
2271
2272
2273
2274
2275static void
2276qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
2277{
2278 srb_t *sp;
2279 fc_port_t *fcport;
2280 struct scsi_cmnd *cp;
2281 struct sts_entry_fx00 *sts;
2282 __le16 comp_status;
2283 __le16 scsi_status;
2284 __le16 lscsi_status;
2285 int32_t resid;
2286 uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
2287 fw_resid_len;
2288 uint8_t *rsp_info = NULL, *sense_data = NULL;
2289 struct qla_hw_data *ha = vha->hw;
2290 uint32_t hindex, handle;
2291 uint16_t que;
2292 struct req_que *req;
2293 int logit = 1;
2294 int res = 0;
2295
2296 sts = (struct sts_entry_fx00 *) pkt;
2297
2298 comp_status = sts->comp_status;
2299 scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
2300 hindex = sts->handle;
2301 handle = LSW(hindex);
2302
2303 que = MSW(hindex);
2304 req = ha->req_q_map[que];
2305
2306
2307 if (handle < req->num_outstanding_cmds)
2308 sp = req->outstanding_cmds[handle];
2309 else
2310 sp = NULL;
2311
2312 if (sp == NULL) {
2313 ql_dbg(ql_dbg_io, vha, 0x3034,
2314 "Invalid status handle (0x%x).\n", handle);
2315
2316 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2317 qla2xxx_wake_dpc(vha);
2318 return;
2319 }
2320
2321 if (sp->type == SRB_TM_CMD) {
2322 req->outstanding_cmds[handle] = NULL;
2323 qlafx00_tm_iocb_entry(vha, req, pkt, sp,
2324 scsi_status, comp_status);
2325 return;
2326 }
2327
2328
2329 if (comp_status == CS_COMPLETE && scsi_status == 0) {
2330 qla2x00_process_completed_request(vha, req, handle);
2331 return;
2332 }
2333
2334 req->outstanding_cmds[handle] = NULL;
2335 cp = GET_CMD_SP(sp);
2336 if (cp == NULL) {
2337 ql_dbg(ql_dbg_io, vha, 0x3048,
2338 "Command already returned (0x%x/%p).\n",
2339 handle, sp);
2340
2341 return;
2342 }
2343
2344 lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
2345
2346 fcport = sp->fcport;
2347
2348 sense_len = par_sense_len = rsp_info_len = resid_len =
2349 fw_resid_len = 0;
2350 if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
2351 sense_len = sts->sense_len;
2352 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2353 | (uint16_t)SS_RESIDUAL_OVER)))
2354 resid_len = le32_to_cpu(sts->residual_len);
2355 if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
2356 fw_resid_len = le32_to_cpu(sts->residual_len);
2357 rsp_info = sense_data = sts->data;
2358 par_sense_len = sizeof(sts->data);
2359
2360
2361 if (comp_status == CS_COMPLETE &&
2362 scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
2363 comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
2364
2365
2366
2367
2368 switch (le16_to_cpu(comp_status)) {
2369 case CS_COMPLETE:
2370 case CS_QUEUE_FULL:
2371 if (scsi_status == 0) {
2372 res = DID_OK << 16;
2373 break;
2374 }
2375 if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
2376 | (uint16_t)SS_RESIDUAL_OVER))) {
2377 resid = resid_len;
2378 scsi_set_resid(cp, resid);
2379
2380 if (!lscsi_status &&
2381 ((unsigned)(scsi_bufflen(cp) - resid) <
2382 cp->underflow)) {
2383 ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
2384 "Mid-layer underflow "
2385 "detected (0x%x of 0x%x bytes).\n",
2386 resid, scsi_bufflen(cp));
2387
2388 res = DID_ERROR << 16;
2389 break;
2390 }
2391 }
2392 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2393
2394 if (lscsi_status ==
2395 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2396 ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
2397 "QUEUE FULL detected.\n");
2398 break;
2399 }
2400 logit = 0;
2401 if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2402 break;
2403
2404 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2405 if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2406 break;
2407
2408 qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
2409 rsp, res);
2410 break;
2411
2412 case CS_DATA_UNDERRUN:
2413
2414 if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2415 resid = fw_resid_len;
2416 else
2417 resid = resid_len;
2418 scsi_set_resid(cp, resid);
2419 if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
2420 if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
2421 && fw_resid_len != resid_len) {
2422 ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
2423 "Dropped frame(s) detected "
2424 "(0x%x of 0x%x bytes).\n",
2425 resid, scsi_bufflen(cp));
2426
2427 res = DID_ERROR << 16 |
2428 le16_to_cpu(lscsi_status);
2429 goto check_scsi_status;
2430 }
2431
2432 if (!lscsi_status &&
2433 ((unsigned)(scsi_bufflen(cp) - resid) <
2434 cp->underflow)) {
2435 ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
2436 "Mid-layer underflow "
2437 "detected (0x%x of 0x%x bytes, "
2438 "cp->underflow: 0x%x).\n",
2439 resid, scsi_bufflen(cp), cp->underflow);
2440
2441 res = DID_ERROR << 16;
2442 break;
2443 }
2444 } else if (lscsi_status !=
2445 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
2446 lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
2447
2448
2449
2450
2451
2452 ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
2453 "Dropped frame(s) detected (0x%x "
2454 "of 0x%x bytes).\n", resid,
2455 scsi_bufflen(cp));
2456
2457 res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
2458 goto check_scsi_status;
2459 } else {
2460 ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
2461 "scsi_status: 0x%x, lscsi_status: 0x%x\n",
2462 scsi_status, lscsi_status);
2463 }
2464
2465 res = DID_OK << 16 | le16_to_cpu(lscsi_status);
2466 logit = 0;
2467
2468check_scsi_status:
2469
2470
2471
2472
2473 if (lscsi_status != 0) {
2474 if (lscsi_status ==
2475 cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
2476 ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
2477 "QUEUE FULL detected.\n");
2478 logit = 1;
2479 break;
2480 }
2481 if (lscsi_status !=
2482 cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
2483 break;
2484
2485 memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
2486 if (!(scsi_status &
2487 cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
2488 break;
2489
2490 qlafx00_handle_sense(sp, sense_data, par_sense_len,
2491 sense_len, rsp, res);
2492 }
2493 break;
2494
2495 case CS_PORT_LOGGED_OUT:
2496 case CS_PORT_CONFIG_CHG:
2497 case CS_PORT_BUSY:
2498 case CS_INCOMPLETE:
2499 case CS_PORT_UNAVAILABLE:
2500 case CS_TIMEOUT:
2501 case CS_RESET:
2502
2503
2504
2505
2506
2507
2508 res = DID_TRANSPORT_DISRUPTED << 16;
2509
2510 ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
2511 "Port down status: port-state=0x%x.\n",
2512 atomic_read(&fcport->state));
2513
2514 if (atomic_read(&fcport->state) == FCS_ONLINE)
2515 qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
2516 break;
2517
2518 case CS_ABORTED:
2519 res = DID_RESET << 16;
2520 break;
2521
2522 default:
2523 res = DID_ERROR << 16;
2524 break;
2525 }
2526
2527 if (logit)
2528 ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
2529 "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
2530 "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
2531 "rsp_info=%p resid=0x%x fw_resid=0x%x sense_len=0x%x, "
2532 "par_sense_len=0x%x, rsp_info_len=0x%x\n",
2533 comp_status, scsi_status, res, vha->host_no,
2534 cp->device->id, cp->device->lun, fcport->tgt_id,
2535 lscsi_status, cp->cmnd, scsi_bufflen(cp),
2536 rsp_info, resid_len, fw_resid_len, sense_len,
2537 par_sense_len, rsp_info_len);
2538
2539 if (rsp->status_srb == NULL)
2540 sp->done(sp, res);
2541}
2542
2543
2544
2545
2546
2547
2548
2549
2550static void
2551qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
2552{
2553 uint8_t sense_sz = 0;
2554 struct qla_hw_data *ha = rsp->hw;
2555 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
2556 srb_t *sp = rsp->status_srb;
2557 struct scsi_cmnd *cp;
2558 uint32_t sense_len;
2559 uint8_t *sense_ptr;
2560
2561 if (!sp) {
2562 ql_dbg(ql_dbg_io, vha, 0x3037,
2563 "no SP, sp = %p\n", sp);
2564 return;
2565 }
2566
2567 if (!GET_FW_SENSE_LEN(sp)) {
2568 ql_dbg(ql_dbg_io, vha, 0x304b,
2569 "no fw sense data, sp = %p\n", sp);
2570 return;
2571 }
2572 cp = GET_CMD_SP(sp);
2573 if (cp == NULL) {
2574 ql_log(ql_log_warn, vha, 0x303b,
2575 "cmd is NULL: already returned to OS (sp=%p).\n", sp);
2576
2577 rsp->status_srb = NULL;
2578 return;
2579 }
2580
2581 if (!GET_CMD_SENSE_LEN(sp)) {
2582 ql_dbg(ql_dbg_io, vha, 0x304c,
2583 "no sense data, sp = %p\n", sp);
2584 } else {
2585 sense_len = GET_CMD_SENSE_LEN(sp);
2586 sense_ptr = GET_CMD_SENSE_PTR(sp);
2587 ql_dbg(ql_dbg_io, vha, 0x304f,
2588 "sp=%p sense_len=0x%x sense_ptr=%p.\n",
2589 sp, sense_len, sense_ptr);
2590
2591 if (sense_len > sizeof(pkt->data))
2592 sense_sz = sizeof(pkt->data);
2593 else
2594 sense_sz = sense_len;
2595
2596
2597 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
2598 (uint8_t *)pkt, sizeof(sts_cont_entry_t));
2599 memcpy(sense_ptr, pkt->data, sense_sz);
2600 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
2601 sense_ptr, sense_sz);
2602
2603 sense_len -= sense_sz;
2604 sense_ptr += sense_sz;
2605
2606 SET_CMD_SENSE_PTR(sp, sense_ptr);
2607 SET_CMD_SENSE_LEN(sp, sense_len);
2608 }
2609 sense_len = GET_FW_SENSE_LEN(sp);
2610 sense_len = (sense_len > sizeof(pkt->data)) ?
2611 (sense_len - sizeof(pkt->data)) : 0;
2612 SET_FW_SENSE_LEN(sp, sense_len);
2613
2614
2615 if (sense_len == 0) {
2616 rsp->status_srb = NULL;
2617 sp->done(sp, cp->result);
2618 }
2619}
2620
2621
2622
2623
2624
2625static void
2626qlafx00_multistatus_entry(struct scsi_qla_host *vha,
2627 struct rsp_que *rsp, void *pkt)
2628{
2629 srb_t *sp;
2630 struct multi_sts_entry_fx00 *stsmfx;
2631 struct qla_hw_data *ha = vha->hw;
2632 uint32_t handle, hindex, handle_count, i;
2633 uint16_t que;
2634 struct req_que *req;
2635 __le32 *handle_ptr;
2636
2637 stsmfx = (struct multi_sts_entry_fx00 *) pkt;
2638
2639 handle_count = stsmfx->handle_count;
2640
2641 if (handle_count > MAX_HANDLE_COUNT) {
2642 ql_dbg(ql_dbg_io, vha, 0x3035,
2643 "Invalid handle count (0x%x).\n", handle_count);
2644 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2645 qla2xxx_wake_dpc(vha);
2646 return;
2647 }
2648
2649 handle_ptr = &stsmfx->handles[0];
2650
2651 for (i = 0; i < handle_count; i++) {
2652 hindex = le32_to_cpu(*handle_ptr);
2653 handle = LSW(hindex);
2654 que = MSW(hindex);
2655 req = ha->req_q_map[que];
2656
2657
2658 if (handle < req->num_outstanding_cmds)
2659 sp = req->outstanding_cmds[handle];
2660 else
2661 sp = NULL;
2662
2663 if (sp == NULL) {
2664 ql_dbg(ql_dbg_io, vha, 0x3044,
2665 "Invalid status handle (0x%x).\n", handle);
2666 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2667 qla2xxx_wake_dpc(vha);
2668 return;
2669 }
2670 qla2x00_process_completed_request(vha, req, handle);
2671 handle_ptr++;
2672 }
2673}
2674
2675
2676
2677
2678
2679
2680static void
2681qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
2682 struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
2683{
2684 srb_t *sp;
2685 struct qla_hw_data *ha = vha->hw;
2686 const char func[] = "ERROR-IOCB";
2687 uint16_t que = 0;
2688 struct req_que *req = NULL;
2689 int res = DID_ERROR << 16;
2690
2691 ql_dbg(ql_dbg_async, vha, 0x507f,
2692 "type of error status in response: 0x%x\n", estatus);
2693
2694 req = ha->req_q_map[que];
2695
2696 sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
2697 if (sp) {
2698 sp->done(sp, res);
2699 return;
2700 }
2701
2702 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2703 qla2xxx_wake_dpc(vha);
2704}
2705
2706
2707
2708
2709
2710static void
2711qlafx00_process_response_queue(struct scsi_qla_host *vha,
2712 struct rsp_que *rsp)
2713{
2714 struct sts_entry_fx00 *pkt;
2715 response_t *lptr;
2716 uint16_t lreq_q_in = 0;
2717 uint16_t lreq_q_out = 0;
2718
2719 lreq_q_in = RD_REG_DWORD(rsp->rsp_q_in);
2720 lreq_q_out = rsp->ring_index;
2721
2722 while (lreq_q_in != lreq_q_out) {
2723 lptr = rsp->ring_ptr;
2724 memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
2725 sizeof(rsp->rsp_pkt));
2726 pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
2727
2728 rsp->ring_index++;
2729 lreq_q_out++;
2730 if (rsp->ring_index == rsp->length) {
2731 lreq_q_out = 0;
2732 rsp->ring_index = 0;
2733 rsp->ring_ptr = rsp->ring;
2734 } else {
2735 rsp->ring_ptr++;
2736 }
2737
2738 if (pkt->entry_status != 0 &&
2739 pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
2740 qlafx00_error_entry(vha, rsp,
2741 (struct sts_entry_fx00 *)pkt, pkt->entry_status,
2742 pkt->entry_type);
2743 continue;
2744 }
2745
2746 switch (pkt->entry_type) {
2747 case STATUS_TYPE_FX00:
2748 qlafx00_status_entry(vha, rsp, pkt);
2749 break;
2750
2751 case STATUS_CONT_TYPE_FX00:
2752 qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
2753 break;
2754
2755 case MULTI_STATUS_TYPE_FX00:
2756 qlafx00_multistatus_entry(vha, rsp, pkt);
2757 break;
2758
2759 case ABORT_IOCB_TYPE_FX00:
2760 qlafx00_abort_iocb_entry(vha, rsp->req,
2761 (struct abort_iocb_entry_fx00 *)pkt);
2762 break;
2763
2764 case IOCTL_IOSB_TYPE_FX00:
2765 qlafx00_ioctl_iosb_entry(vha, rsp->req,
2766 (struct ioctl_iocb_entry_fx00 *)pkt);
2767 break;
2768 default:
2769
2770 ql_dbg(ql_dbg_async, vha, 0x5081,
2771 "Received unknown response pkt type %x "
2772 "entry status=%x.\n",
2773 pkt->entry_type, pkt->entry_status);
2774 break;
2775 }
2776 }
2777
2778
2779 WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
2780}
2781
2782
2783
2784
2785
2786static void
2787qlafx00_async_event(scsi_qla_host_t *vha)
2788{
2789 struct qla_hw_data *ha = vha->hw;
2790 struct device_reg_fx00 __iomem *reg;
2791 int data_size = 1;
2792
2793 reg = &ha->iobase->ispfx00;
2794
2795 switch (ha->aenmb[0]) {
2796 case QLAFX00_MBA_SYSTEM_ERR:
2797 ql_log(ql_log_warn, vha, 0x5079,
2798 "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
2799 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2800 break;
2801
2802 case QLAFX00_MBA_SHUTDOWN_RQSTD:
2803 ql_dbg(ql_dbg_async, vha, 0x5076,
2804 "Asynchronous FW shutdown requested.\n");
2805 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2806 qla2xxx_wake_dpc(vha);
2807 break;
2808
2809 case QLAFX00_MBA_PORT_UPDATE:
2810 ha->aenmb[1] = RD_REG_DWORD(®->aenmailbox1);
2811 ha->aenmb[2] = RD_REG_DWORD(®->aenmailbox2);
2812 ha->aenmb[3] = RD_REG_DWORD(®->aenmailbox3);
2813 ql_dbg(ql_dbg_async, vha, 0x5077,
2814 "Asynchronous port Update received "
2815 "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
2816 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
2817 data_size = 4;
2818 break;
2819
2820 case QLAFX00_MBA_TEMP_OVER:
2821 ql_log(ql_log_info, vha, 0x5085,
2822 "Asynchronous over temperature event received "
2823 "aenmb[0]: %x\n",
2824 ha->aenmb[0]);
2825 break;
2826
2827 case QLAFX00_MBA_TEMP_NORM:
2828 ql_log(ql_log_info, vha, 0x5086,
2829 "Asynchronous normal temperature event received "
2830 "aenmb[0]: %x\n",
2831 ha->aenmb[0]);
2832 break;
2833
2834 case QLAFX00_MBA_TEMP_CRIT:
2835 ql_log(ql_log_info, vha, 0x5083,
2836 "Asynchronous critical temperature event received "
2837 "aenmb[0]: %x\n",
2838 ha->aenmb[0]);
2839 break;
2840
2841 default:
2842 ha->aenmb[1] = RD_REG_WORD(®->aenmailbox1);
2843 ha->aenmb[2] = RD_REG_WORD(®->aenmailbox2);
2844 ha->aenmb[3] = RD_REG_WORD(®->aenmailbox3);
2845 ha->aenmb[4] = RD_REG_WORD(®->aenmailbox4);
2846 ha->aenmb[5] = RD_REG_WORD(®->aenmailbox5);
2847 ha->aenmb[6] = RD_REG_WORD(®->aenmailbox6);
2848 ha->aenmb[7] = RD_REG_WORD(®->aenmailbox7);
2849 ql_dbg(ql_dbg_async, vha, 0x5078,
2850 "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
2851 ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
2852 ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
2853 break;
2854 }
2855 qlafx00_post_aenfx_work(vha, ha->aenmb[0],
2856 (uint32_t *)ha->aenmb, data_size);
2857}
2858
2859
2860
2861
2862
2863
2864
2865static void
2866qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
2867{
2868 uint16_t cnt;
2869 uint32_t __iomem *wptr;
2870 struct qla_hw_data *ha = vha->hw;
2871 struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
2872
2873 if (!ha->mcp32)
2874 ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
2875
2876
2877 ha->flags.mbox_int = 1;
2878 ha->mailbox_out32[0] = mb0;
2879 wptr = (uint32_t __iomem *)®->mailbox17;
2880
2881 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2882 ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr);
2883 wptr++;
2884 }
2885}
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896irqreturn_t
2897qlafx00_intr_handler(int irq, void *dev_id)
2898{
2899 scsi_qla_host_t *vha;
2900 struct qla_hw_data *ha;
2901 struct device_reg_fx00 __iomem *reg;
2902 int status;
2903 unsigned long iter;
2904 uint32_t stat;
2905 uint32_t mb[8];
2906 struct rsp_que *rsp;
2907 unsigned long flags;
2908 uint32_t clr_intr = 0;
2909 uint32_t intr_stat = 0;
2910
2911 rsp = (struct rsp_que *) dev_id;
2912 if (!rsp) {
2913 ql_log(ql_log_info, NULL, 0x507d,
2914 "%s: NULL response queue pointer.\n", __func__);
2915 return IRQ_NONE;
2916 }
2917
2918 ha = rsp->hw;
2919 reg = &ha->iobase->ispfx00;
2920 status = 0;
2921
2922 if (unlikely(pci_channel_offline(ha->pdev)))
2923 return IRQ_HANDLED;
2924
2925 spin_lock_irqsave(&ha->hardware_lock, flags);
2926 vha = pci_get_drvdata(ha->pdev);
2927 for (iter = 50; iter--; clr_intr = 0) {
2928 stat = QLAFX00_RD_INTR_REG(ha);
2929 if (qla2x00_check_reg32_for_disconnect(vha, stat))
2930 break;
2931 intr_stat = stat & QLAFX00_HST_INT_STS_BITS;
2932 if (!intr_stat)
2933 break;
2934
2935 if (stat & QLAFX00_INTR_MB_CMPLT) {
2936 mb[0] = RD_REG_WORD(®->mailbox16);
2937 qlafx00_mbx_completion(vha, mb[0]);
2938 status |= MBX_INTERRUPT;
2939 clr_intr |= QLAFX00_INTR_MB_CMPLT;
2940 }
2941 if (intr_stat & QLAFX00_INTR_ASYNC_CMPLT) {
2942 ha->aenmb[0] = RD_REG_WORD(®->aenmailbox0);
2943 qlafx00_async_event(vha);
2944 clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
2945 }
2946 if (intr_stat & QLAFX00_INTR_RSP_CMPLT) {
2947 qlafx00_process_response_queue(vha, rsp);
2948 clr_intr |= QLAFX00_INTR_RSP_CMPLT;
2949 }
2950
2951 QLAFX00_CLR_INTR_REG(ha, clr_intr);
2952 QLAFX00_RD_INTR_REG(ha);
2953 }
2954
2955 qla2x00_handle_mbx_completion(ha, status);
2956 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2957
2958 return IRQ_HANDLED;
2959}
2960
2961
2962
2963static inline cont_a64_entry_t *
2964qlafx00_prep_cont_type1_iocb(struct req_que *req,
2965 cont_a64_entry_t *lcont_pkt)
2966{
2967 cont_a64_entry_t *cont_pkt;
2968
2969
2970 req->ring_index++;
2971 if (req->ring_index == req->length) {
2972 req->ring_index = 0;
2973 req->ring_ptr = req->ring;
2974 } else {
2975 req->ring_ptr++;
2976 }
2977
2978 cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
2979
2980
2981 lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
2982
2983 return cont_pkt;
2984}
2985
2986static inline void
2987qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
2988 uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
2989{
2990 uint16_t avail_dsds;
2991 __le32 *cur_dsd;
2992 scsi_qla_host_t *vha;
2993 struct scsi_cmnd *cmd;
2994 struct scatterlist *sg;
2995 int i, cont;
2996 struct req_que *req;
2997 cont_a64_entry_t lcont_pkt;
2998 cont_a64_entry_t *cont_pkt;
2999
3000 vha = sp->vha;
3001 req = vha->req;
3002
3003 cmd = GET_CMD_SP(sp);
3004 cont = 0;
3005 cont_pkt = NULL;
3006
3007
3008 lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
3009
3010
3011 if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
3012 lcmd_pkt->byte_count = cpu_to_le32(0);
3013 return;
3014 }
3015
3016
3017 if (cmd->sc_data_direction == DMA_TO_DEVICE) {
3018 lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
3019 vha->qla_stats.output_bytes += scsi_bufflen(cmd);
3020 } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
3021 lcmd_pkt->cntrl_flags = TMF_READ_DATA;
3022 vha->qla_stats.input_bytes += scsi_bufflen(cmd);
3023 }
3024
3025
3026 avail_dsds = 1;
3027 cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
3028
3029
3030 scsi_for_each_sg(cmd, sg, tot_dsds, i) {
3031 dma_addr_t sle_dma;
3032
3033
3034 if (avail_dsds == 0) {
3035
3036
3037
3038
3039 memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
3040 cont_pkt =
3041 qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
3042 cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
3043 avail_dsds = 5;
3044 cont = 1;
3045 }
3046
3047 sle_dma = sg_dma_address(sg);
3048 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
3049 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
3050 *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
3051 avail_dsds--;
3052 if (avail_dsds == 0 && cont == 1) {
3053 cont = 0;
3054 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3055 REQUEST_ENTRY_SIZE);
3056 }
3057
3058 }
3059 if (avail_dsds != 0 && cont == 1) {
3060 memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
3061 REQUEST_ENTRY_SIZE);
3062 }
3063}
3064
3065
3066
3067
3068
3069
3070
3071int
3072qlafx00_start_scsi(srb_t *sp)
3073{
3074 int nseg;
3075 unsigned long flags;
3076 uint32_t index;
3077 uint32_t handle;
3078 uint16_t cnt;
3079 uint16_t req_cnt;
3080 uint16_t tot_dsds;
3081 struct req_que *req = NULL;
3082 struct rsp_que *rsp = NULL;
3083 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
3084 struct scsi_qla_host *vha = sp->vha;
3085 struct qla_hw_data *ha = vha->hw;
3086 struct cmd_type_7_fx00 *cmd_pkt;
3087 struct cmd_type_7_fx00 lcmd_pkt;
3088 struct scsi_lun llun;
3089
3090
3091 rsp = ha->rsp_q_map[0];
3092 req = vha->req;
3093
3094
3095 tot_dsds = 0;
3096
3097
3098 spin_lock_irqsave(&ha->hardware_lock, flags);
3099
3100
3101 handle = req->current_outstanding_cmd;
3102 for (index = 1; index < req->num_outstanding_cmds; index++) {
3103 handle++;
3104 if (handle == req->num_outstanding_cmds)
3105 handle = 1;
3106 if (!req->outstanding_cmds[handle])
3107 break;
3108 }
3109 if (index == req->num_outstanding_cmds)
3110 goto queuing_error;
3111
3112
3113 if (scsi_sg_count(cmd)) {
3114 nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
3115 scsi_sg_count(cmd), cmd->sc_data_direction);
3116 if (unlikely(!nseg))
3117 goto queuing_error;
3118 } else
3119 nseg = 0;
3120
3121 tot_dsds = nseg;
3122 req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
3123 if (req->cnt < (req_cnt + 2)) {
3124 cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
3125
3126 if (req->ring_index < cnt)
3127 req->cnt = cnt - req->ring_index;
3128 else
3129 req->cnt = req->length -
3130 (req->ring_index - cnt);
3131 if (req->cnt < (req_cnt + 2))
3132 goto queuing_error;
3133 }
3134
3135
3136 req->current_outstanding_cmd = handle;
3137 req->outstanding_cmds[handle] = sp;
3138 sp->handle = handle;
3139 cmd->host_scribble = (unsigned char *)(unsigned long)handle;
3140 req->cnt -= req_cnt;
3141
3142 cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
3143
3144 memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
3145
3146 lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
3147 lcmd_pkt.reserved_0 = 0;
3148 lcmd_pkt.port_path_ctrl = 0;
3149 lcmd_pkt.reserved_1 = 0;
3150 lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
3151 lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
3152
3153 int_to_scsilun(cmd->device->lun, &llun);
3154 host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
3155 sizeof(lcmd_pkt.lun));
3156
3157
3158 host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
3159 lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
3160
3161
3162 qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
3163
3164
3165 lcmd_pkt.entry_count = (uint8_t)req_cnt;
3166
3167
3168 lcmd_pkt.entry_status = (uint8_t) rsp->id;
3169
3170 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
3171 (uint8_t *)cmd->cmnd, cmd->cmd_len);
3172 ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
3173 (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
3174
3175 memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
3176 wmb();
3177
3178
3179 req->ring_index++;
3180 if (req->ring_index == req->length) {
3181 req->ring_index = 0;
3182 req->ring_ptr = req->ring;
3183 } else
3184 req->ring_ptr++;
3185
3186 sp->flags |= SRB_DMA_VALID;
3187
3188
3189 WRT_REG_DWORD(req->req_q_in, req->ring_index);
3190 QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
3191
3192 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3193 return QLA_SUCCESS;
3194
3195queuing_error:
3196 if (tot_dsds)
3197 scsi_dma_unmap(cmd);
3198
3199 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3200
3201 return QLA_FUNCTION_FAILED;
3202}
3203
3204void
3205qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
3206{
3207 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3208 scsi_qla_host_t *vha = sp->vha;
3209 struct req_que *req = vha->req;
3210 struct tsk_mgmt_entry_fx00 tm_iocb;
3211 struct scsi_lun llun;
3212
3213 memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
3214 tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
3215 tm_iocb.entry_count = 1;
3216 tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
3217 tm_iocb.reserved_0 = 0;
3218 tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
3219 tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
3220 if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
3221 int_to_scsilun(fxio->u.tmf.lun, &llun);
3222 host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
3223 sizeof(struct scsi_lun));
3224 }
3225
3226 memcpy((void *)ptm_iocb, &tm_iocb,
3227 sizeof(struct tsk_mgmt_entry_fx00));
3228 wmb();
3229}
3230
3231void
3232qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
3233{
3234 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3235 scsi_qla_host_t *vha = sp->vha;
3236 struct req_que *req = vha->req;
3237 struct abort_iocb_entry_fx00 abt_iocb;
3238
3239 memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
3240 abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
3241 abt_iocb.entry_count = 1;
3242 abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
3243 abt_iocb.abort_handle =
3244 cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
3245 abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
3246 abt_iocb.req_que_no = cpu_to_le16(req->id);
3247
3248 memcpy((void *)pabt_iocb, &abt_iocb,
3249 sizeof(struct abort_iocb_entry_fx00));
3250 wmb();
3251}
3252
3253void
3254qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
3255{
3256 struct srb_iocb *fxio = &sp->u.iocb_cmd;
3257 struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
3258 struct bsg_job *bsg_job;
3259 struct fc_bsg_request *bsg_request;
3260 struct fxdisc_entry_fx00 fx_iocb;
3261 uint8_t entry_cnt = 1;
3262
3263 memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
3264 fx_iocb.entry_type = FX00_IOCB_TYPE;
3265 fx_iocb.handle = cpu_to_le32(sp->handle);
3266 fx_iocb.entry_count = entry_cnt;
3267
3268 if (sp->type == SRB_FXIOCB_DCMD) {
3269 fx_iocb.func_num =
3270 sp->u.iocb_cmd.u.fxiocb.req_func_type;
3271 fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
3272 fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
3273 fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
3274 fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
3275 fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
3276
3277 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
3278 fx_iocb.req_dsdcnt = cpu_to_le16(1);
3279 fx_iocb.req_xfrcnt =
3280 cpu_to_le16(fxio->u.fxiocb.req_len);
3281 fx_iocb.dseg_rq_address[0] =
3282 cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
3283 fx_iocb.dseg_rq_address[1] =
3284 cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
3285 fx_iocb.dseg_rq_len =
3286 cpu_to_le32(fxio->u.fxiocb.req_len);
3287 }
3288
3289 if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
3290 fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
3291 fx_iocb.rsp_xfrcnt =
3292 cpu_to_le16(fxio->u.fxiocb.rsp_len);
3293 fx_iocb.dseg_rsp_address[0] =
3294 cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
3295 fx_iocb.dseg_rsp_address[1] =
3296 cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
3297 fx_iocb.dseg_rsp_len =
3298 cpu_to_le32(fxio->u.fxiocb.rsp_len);
3299 }
3300
3301 if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
3302 fx_iocb.dataword = fxio->u.fxiocb.req_data;
3303 }
3304 fx_iocb.flags = fxio->u.fxiocb.flags;
3305 } else {
3306 struct scatterlist *sg;
3307 bsg_job = sp->u.bsg_job;
3308 bsg_request = bsg_job->request;
3309 piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
3310 &bsg_request->rqst_data.h_vendor.vendor_cmd[1];
3311
3312 fx_iocb.func_num = piocb_rqst->func_type;
3313 fx_iocb.adapid = piocb_rqst->adapid;
3314 fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
3315 fx_iocb.reserved_0 = piocb_rqst->reserved_0;
3316 fx_iocb.reserved_1 = piocb_rqst->reserved_1;
3317 fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
3318 fx_iocb.dataword = piocb_rqst->dataword;
3319 fx_iocb.req_xfrcnt = piocb_rqst->req_len;
3320 fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
3321
3322 if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
3323 int avail_dsds, tot_dsds;
3324 cont_a64_entry_t lcont_pkt;
3325 cont_a64_entry_t *cont_pkt = NULL;
3326 __le32 *cur_dsd;
3327 int index = 0, cont = 0;
3328
3329 fx_iocb.req_dsdcnt =
3330 cpu_to_le16(bsg_job->request_payload.sg_cnt);
3331 tot_dsds =
3332 bsg_job->request_payload.sg_cnt;
3333 cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
3334 avail_dsds = 1;
3335 for_each_sg(bsg_job->request_payload.sg_list, sg,
3336 tot_dsds, index) {
3337 dma_addr_t sle_dma;
3338
3339
3340 if (avail_dsds == 0) {
3341
3342
3343
3344
3345 memset(&lcont_pkt, 0,
3346 REQUEST_ENTRY_SIZE);
3347 cont_pkt =
3348 qlafx00_prep_cont_type1_iocb(
3349 sp->vha->req, &lcont_pkt);
3350 cur_dsd = (__le32 *)
3351 lcont_pkt.dseg_0_address;
3352 avail_dsds = 5;
3353 cont = 1;
3354 entry_cnt++;
3355 }
3356
3357 sle_dma = sg_dma_address(sg);
3358 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
3359 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
3360 *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
3361 avail_dsds--;
3362
3363 if (avail_dsds == 0 && cont == 1) {
3364 cont = 0;
3365 memcpy_toio(
3366 (void __iomem *)cont_pkt,
3367 &lcont_pkt, REQUEST_ENTRY_SIZE);
3368 ql_dump_buffer(
3369 ql_dbg_user + ql_dbg_verbose,
3370 sp->vha, 0x3042,
3371 (uint8_t *)&lcont_pkt,
3372 REQUEST_ENTRY_SIZE);
3373 }
3374 }
3375 if (avail_dsds != 0 && cont == 1) {
3376 memcpy_toio((void __iomem *)cont_pkt,
3377 &lcont_pkt, REQUEST_ENTRY_SIZE);
3378 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3379 sp->vha, 0x3043,
3380 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3381 }
3382 }
3383
3384 if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
3385 int avail_dsds, tot_dsds;
3386 cont_a64_entry_t lcont_pkt;
3387 cont_a64_entry_t *cont_pkt = NULL;
3388 __le32 *cur_dsd;
3389 int index = 0, cont = 0;
3390
3391 fx_iocb.rsp_dsdcnt =
3392 cpu_to_le16(bsg_job->reply_payload.sg_cnt);
3393 tot_dsds = bsg_job->reply_payload.sg_cnt;
3394 cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
3395 avail_dsds = 1;
3396
3397 for_each_sg(bsg_job->reply_payload.sg_list, sg,
3398 tot_dsds, index) {
3399 dma_addr_t sle_dma;
3400
3401
3402 if (avail_dsds == 0) {
3403
3404
3405
3406
3407 memset(&lcont_pkt, 0,
3408 REQUEST_ENTRY_SIZE);
3409 cont_pkt =
3410 qlafx00_prep_cont_type1_iocb(
3411 sp->vha->req, &lcont_pkt);
3412 cur_dsd = (__le32 *)
3413 lcont_pkt.dseg_0_address;
3414 avail_dsds = 5;
3415 cont = 1;
3416 entry_cnt++;
3417 }
3418
3419 sle_dma = sg_dma_address(sg);
3420 *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
3421 *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
3422 *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
3423 avail_dsds--;
3424
3425 if (avail_dsds == 0 && cont == 1) {
3426 cont = 0;
3427 memcpy_toio((void __iomem *)cont_pkt,
3428 &lcont_pkt,
3429 REQUEST_ENTRY_SIZE);
3430 ql_dump_buffer(
3431 ql_dbg_user + ql_dbg_verbose,
3432 sp->vha, 0x3045,
3433 (uint8_t *)&lcont_pkt,
3434 REQUEST_ENTRY_SIZE);
3435 }
3436 }
3437 if (avail_dsds != 0 && cont == 1) {
3438 memcpy_toio((void __iomem *)cont_pkt,
3439 &lcont_pkt, REQUEST_ENTRY_SIZE);
3440 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3441 sp->vha, 0x3046,
3442 (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
3443 }
3444 }
3445
3446 if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
3447 fx_iocb.dataword = piocb_rqst->dataword;
3448 fx_iocb.flags = piocb_rqst->flags;
3449 fx_iocb.entry_count = entry_cnt;
3450 }
3451
3452 ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
3453 sp->vha, 0x3047,
3454 (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
3455
3456 memcpy_toio((void __iomem *)pfxiocb, &fx_iocb,
3457 sizeof(struct fxdisc_entry_fx00));
3458 wmb();
3459}
3460
