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16#include <linux/slab.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/i2c.h>
20#include <linux/wait.h>
21#include <linux/delay.h>
22#include <linux/mutex.h>
23#include <linux/io.h>
24
25#include "cxd2099.h"
26
27static int buffermode;
28module_param(buffermode, int, 0444);
29MODULE_PARM_DESC(buffermode, "Enable CXD2099AR buffer mode (default: disabled)");
30
31static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount);
32
33struct cxd {
34 struct dvb_ca_en50221 en;
35
36 struct i2c_adapter *i2c;
37 struct cxd2099_cfg cfg;
38
39 u8 regs[0x23];
40 u8 lastaddress;
41 u8 clk_reg_f;
42 u8 clk_reg_b;
43 int mode;
44 int ready;
45 int dr;
46 int write_busy;
47 int slot_stat;
48
49 u8 amem[1024];
50 int amem_read;
51
52 int cammode;
53 struct mutex lock;
54
55 u8 rbuf[1028];
56 u8 wbuf[1028];
57};
58
59static int i2c_write_reg(struct i2c_adapter *adapter, u8 adr,
60 u8 reg, u8 data)
61{
62 u8 m[2] = {reg, data};
63 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};
64
65 if (i2c_transfer(adapter, &msg, 1) != 1) {
66 dev_err(&adapter->dev,
67 "Failed to write to I2C register %02x@%02x!\n",
68 reg, adr);
69 return -1;
70 }
71 return 0;
72}
73
74static int i2c_write(struct i2c_adapter *adapter, u8 adr,
75 u8 *data, u16 len)
76{
77 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len};
78
79 if (i2c_transfer(adapter, &msg, 1) != 1) {
80 dev_err(&adapter->dev, "Failed to write to I2C!\n");
81 return -1;
82 }
83 return 0;
84}
85
86static int i2c_read_reg(struct i2c_adapter *adapter, u8 adr,
87 u8 reg, u8 *val)
88{
89 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
90 .buf = ®, .len = 1},
91 {.addr = adr, .flags = I2C_M_RD,
92 .buf = val, .len = 1} };
93
94 if (i2c_transfer(adapter, msgs, 2) != 2) {
95 dev_err(&adapter->dev, "error in %s()\n", __func__);
96 return -1;
97 }
98 return 0;
99}
100
101static int i2c_read(struct i2c_adapter *adapter, u8 adr,
102 u8 reg, u8 *data, u16 n)
103{
104 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,
105 .buf = ®, .len = 1},
106 {.addr = adr, .flags = I2C_M_RD,
107 .buf = data, .len = n} };
108
109 if (i2c_transfer(adapter, msgs, 2) != 2) {
110 dev_err(&adapter->dev, "error in %s()\n", __func__);
111 return -1;
112 }
113 return 0;
114}
115
116static int read_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
117{
118 int status = 0;
119
120 if (ci->lastaddress != adr)
121 status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
122 if (!status) {
123 ci->lastaddress = adr;
124
125 while (n) {
126 int len = n;
127
128 if (ci->cfg.max_i2c && len > ci->cfg.max_i2c)
129 len = ci->cfg.max_i2c;
130 status = i2c_read(ci->i2c, ci->cfg.adr, 1, data, len);
131 if (status)
132 return status;
133 data += len;
134 n -= len;
135 }
136 }
137 return status;
138}
139
140static int read_reg(struct cxd *ci, u8 reg, u8 *val)
141{
142 return read_block(ci, reg, val, 1);
143}
144
145static int read_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
146{
147 int status;
148 u8 addr[3] = {2, address & 0xff, address >> 8};
149
150 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
151 if (!status)
152 status = i2c_read(ci->i2c, ci->cfg.adr, 3, data, n);
153 return status;
154}
155
156static int write_pccard(struct cxd *ci, u16 address, u8 *data, u8 n)
157{
158 int status;
159 u8 addr[3] = {2, address & 0xff, address >> 8};
160
161 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
162 if (!status) {
163 u8 buf[256] = {3};
164
165 memcpy(buf + 1, data, n);
166 status = i2c_write(ci->i2c, ci->cfg.adr, buf, n + 1);
167 }
168 return status;
169}
170
171static int read_io(struct cxd *ci, u16 address, u8 *val)
172{
173 int status;
174 u8 addr[3] = {2, address & 0xff, address >> 8};
175
176 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
177 if (!status)
178 status = i2c_read(ci->i2c, ci->cfg.adr, 3, val, 1);
179 return status;
180}
181
182static int write_io(struct cxd *ci, u16 address, u8 val)
183{
184 int status;
185 u8 addr[3] = {2, address & 0xff, address >> 8};
186 u8 buf[2] = {3, val};
187
188 status = i2c_write(ci->i2c, ci->cfg.adr, addr, 3);
189 if (!status)
190 status = i2c_write(ci->i2c, ci->cfg.adr, buf, 2);
191 return status;
192}
193
194static int write_regm(struct cxd *ci, u8 reg, u8 val, u8 mask)
195{
196 int status = 0;
197
198 if (ci->lastaddress != reg)
199 status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, reg);
200 if (!status && reg >= 6 && reg <= 8 && mask != 0xff)
201 status = i2c_read_reg(ci->i2c, ci->cfg.adr, 1, &ci->regs[reg]);
202 ci->lastaddress = reg;
203 ci->regs[reg] = (ci->regs[reg] & (~mask)) | val;
204 if (!status)
205 status = i2c_write_reg(ci->i2c, ci->cfg.adr, 1, ci->regs[reg]);
206 if (reg == 0x20)
207 ci->regs[reg] &= 0x7f;
208 return status;
209}
210
211static int write_reg(struct cxd *ci, u8 reg, u8 val)
212{
213 return write_regm(ci, reg, val, 0xff);
214}
215
216static int write_block(struct cxd *ci, u8 adr, u8 *data, u16 n)
217{
218 int status = 0;
219 u8 *buf = ci->wbuf;
220
221 if (ci->lastaddress != adr)
222 status = i2c_write_reg(ci->i2c, ci->cfg.adr, 0, adr);
223 if (status)
224 return status;
225
226 ci->lastaddress = adr;
227 buf[0] = 1;
228 while (n) {
229 int len = n;
230
231 if (ci->cfg.max_i2c && (len + 1 > ci->cfg.max_i2c))
232 len = ci->cfg.max_i2c - 1;
233 memcpy(buf + 1, data, len);
234 status = i2c_write(ci->i2c, ci->cfg.adr, buf, len + 1);
235 if (status)
236 return status;
237 n -= len;
238 data += len;
239 }
240 return status;
241}
242
243static void set_mode(struct cxd *ci, int mode)
244{
245 if (mode == ci->mode)
246 return;
247
248 switch (mode) {
249 case 0x00:
250 write_regm(ci, 0x06, 0x00, 0x07);
251 break;
252 case 0x01:
253 write_regm(ci, 0x06, 0x02, 0x07);
254 break;
255 default:
256 break;
257 }
258 ci->mode = mode;
259}
260
261static void cam_mode(struct cxd *ci, int mode)
262{
263 u8 dummy;
264
265 if (mode == ci->cammode)
266 return;
267
268 switch (mode) {
269 case 0x00:
270 write_regm(ci, 0x20, 0x80, 0x80);
271 break;
272 case 0x01:
273 if (!ci->en.read_data)
274 return;
275 ci->write_busy = 0;
276 dev_info(&ci->i2c->dev, "enable cam buffer mode\n");
277 write_reg(ci, 0x0d, 0x00);
278 write_reg(ci, 0x0e, 0x01);
279 write_regm(ci, 0x08, 0x40, 0x40);
280 read_reg(ci, 0x12, &dummy);
281 write_regm(ci, 0x08, 0x80, 0x80);
282 break;
283 default:
284 break;
285 }
286 ci->cammode = mode;
287}
288
289static int init(struct cxd *ci)
290{
291 int status;
292
293 mutex_lock(&ci->lock);
294 ci->mode = -1;
295 do {
296 status = write_reg(ci, 0x00, 0x00);
297 if (status < 0)
298 break;
299 status = write_reg(ci, 0x01, 0x00);
300 if (status < 0)
301 break;
302 status = write_reg(ci, 0x02, 0x10);
303 if (status < 0)
304 break;
305 status = write_reg(ci, 0x03, 0x00);
306 if (status < 0)
307 break;
308 status = write_reg(ci, 0x05, 0xFF);
309 if (status < 0)
310 break;
311 status = write_reg(ci, 0x06, 0x1F);
312 if (status < 0)
313 break;
314 status = write_reg(ci, 0x07, 0x1F);
315 if (status < 0)
316 break;
317 status = write_reg(ci, 0x08, 0x28);
318 if (status < 0)
319 break;
320 status = write_reg(ci, 0x14, 0x20);
321 if (status < 0)
322 break;
323
324
325
326
327 status = write_reg(ci, 0x0A, 0xA7);
328 if (status < 0)
329 break;
330
331 status = write_reg(ci, 0x0B, 0x33);
332 if (status < 0)
333 break;
334 status = write_reg(ci, 0x0C, 0x33);
335 if (status < 0)
336 break;
337
338 status = write_regm(ci, 0x14, 0x00, 0x0F);
339 if (status < 0)
340 break;
341 status = write_reg(ci, 0x15, ci->clk_reg_b);
342 if (status < 0)
343 break;
344 status = write_regm(ci, 0x16, 0x00, 0x0F);
345 if (status < 0)
346 break;
347 status = write_reg(ci, 0x17, ci->clk_reg_f);
348 if (status < 0)
349 break;
350
351 if (ci->cfg.clock_mode == 2) {
352
353 u32 reg = ((ci->cfg.bitrate << 13) + 71999) / 72000;
354
355 if (ci->cfg.polarity) {
356 status = write_reg(ci, 0x09, 0x6f);
357 if (status < 0)
358 break;
359 } else {
360 status = write_reg(ci, 0x09, 0x6d);
361 if (status < 0)
362 break;
363 }
364 status = write_reg(ci, 0x20, 0x08);
365 if (status < 0)
366 break;
367 status = write_reg(ci, 0x21, (reg >> 8) & 0xff);
368 if (status < 0)
369 break;
370 status = write_reg(ci, 0x22, reg & 0xff);
371 if (status < 0)
372 break;
373 } else if (ci->cfg.clock_mode == 1) {
374 if (ci->cfg.polarity) {
375 status = write_reg(ci, 0x09, 0x6f);
376 if (status < 0)
377 break;
378 } else {
379 status = write_reg(ci, 0x09, 0x6d);
380 if (status < 0)
381 break;
382 }
383 status = write_reg(ci, 0x20, 0x68);
384 if (status < 0)
385 break;
386 status = write_reg(ci, 0x21, 0x00);
387 if (status < 0)
388 break;
389 status = write_reg(ci, 0x22, 0x02);
390 if (status < 0)
391 break;
392 } else {
393 if (ci->cfg.polarity) {
394 status = write_reg(ci, 0x09, 0x4f);
395 if (status < 0)
396 break;
397 } else {
398 status = write_reg(ci, 0x09, 0x4d);
399 if (status < 0)
400 break;
401 }
402 status = write_reg(ci, 0x20, 0x28);
403 if (status < 0)
404 break;
405 status = write_reg(ci, 0x21, 0x00);
406 if (status < 0)
407 break;
408 status = write_reg(ci, 0x22, 0x07);
409 if (status < 0)
410 break;
411 }
412
413 status = write_regm(ci, 0x20, 0x80, 0x80);
414 if (status < 0)
415 break;
416 status = write_regm(ci, 0x03, 0x02, 0x02);
417 if (status < 0)
418 break;
419 status = write_reg(ci, 0x01, 0x04);
420 if (status < 0)
421 break;
422 status = write_reg(ci, 0x00, 0x31);
423 if (status < 0)
424 break;
425
426
427 status = write_regm(ci, 0x09, 0x08, 0x08);
428 if (status < 0)
429 break;
430 ci->cammode = -1;
431 cam_mode(ci, 0);
432 } while (0);
433 mutex_unlock(&ci->lock);
434
435 return 0;
436}
437
438static int read_attribute_mem(struct dvb_ca_en50221 *ca,
439 int slot, int address)
440{
441 struct cxd *ci = ca->data;
442 u8 val;
443
444 mutex_lock(&ci->lock);
445 set_mode(ci, 1);
446 read_pccard(ci, address, &val, 1);
447 mutex_unlock(&ci->lock);
448 return val;
449}
450
451static int write_attribute_mem(struct dvb_ca_en50221 *ca, int slot,
452 int address, u8 value)
453{
454 struct cxd *ci = ca->data;
455
456 mutex_lock(&ci->lock);
457 set_mode(ci, 1);
458 write_pccard(ci, address, &value, 1);
459 mutex_unlock(&ci->lock);
460 return 0;
461}
462
463static int read_cam_control(struct dvb_ca_en50221 *ca,
464 int slot, u8 address)
465{
466 struct cxd *ci = ca->data;
467 u8 val;
468
469 mutex_lock(&ci->lock);
470 set_mode(ci, 0);
471 read_io(ci, address, &val);
472 mutex_unlock(&ci->lock);
473 return val;
474}
475
476static int write_cam_control(struct dvb_ca_en50221 *ca, int slot,
477 u8 address, u8 value)
478{
479 struct cxd *ci = ca->data;
480
481 mutex_lock(&ci->lock);
482 set_mode(ci, 0);
483 write_io(ci, address, value);
484 mutex_unlock(&ci->lock);
485 return 0;
486}
487
488static int slot_reset(struct dvb_ca_en50221 *ca, int slot)
489{
490 struct cxd *ci = ca->data;
491
492 if (ci->cammode)
493 read_data(ca, slot, ci->rbuf, 0);
494
495 mutex_lock(&ci->lock);
496 cam_mode(ci, 0);
497 write_reg(ci, 0x00, 0x21);
498 write_reg(ci, 0x06, 0x1F);
499 write_reg(ci, 0x00, 0x31);
500 write_regm(ci, 0x20, 0x80, 0x80);
501 write_reg(ci, 0x03, 0x02);
502 ci->ready = 0;
503 ci->mode = -1;
504 {
505 int i;
506
507 for (i = 0; i < 100; i++) {
508 usleep_range(10000, 11000);
509 if (ci->ready)
510 break;
511 }
512 }
513 mutex_unlock(&ci->lock);
514 return 0;
515}
516
517static int slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
518{
519 struct cxd *ci = ca->data;
520
521 dev_dbg(&ci->i2c->dev, "%s\n", __func__);
522 if (ci->cammode)
523 read_data(ca, slot, ci->rbuf, 0);
524 mutex_lock(&ci->lock);
525 write_reg(ci, 0x00, 0x21);
526 write_reg(ci, 0x06, 0x1F);
527 msleep(300);
528
529 write_regm(ci, 0x09, 0x08, 0x08);
530 write_regm(ci, 0x20, 0x80, 0x80);
531 write_regm(ci, 0x06, 0x07, 0x07);
532
533 ci->mode = -1;
534 ci->write_busy = 0;
535 mutex_unlock(&ci->lock);
536 return 0;
537}
538
539static int slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
540{
541 struct cxd *ci = ca->data;
542
543 mutex_lock(&ci->lock);
544 write_regm(ci, 0x09, 0x00, 0x08);
545 set_mode(ci, 0);
546 cam_mode(ci, 1);
547 mutex_unlock(&ci->lock);
548 return 0;
549}
550
551static int campoll(struct cxd *ci)
552{
553 u8 istat;
554
555 read_reg(ci, 0x04, &istat);
556 if (!istat)
557 return 0;
558 write_reg(ci, 0x05, istat);
559
560 if (istat & 0x40)
561 ci->dr = 1;
562 if (istat & 0x20)
563 ci->write_busy = 0;
564
565 if (istat & 2) {
566 u8 slotstat;
567
568 read_reg(ci, 0x01, &slotstat);
569 if (!(2 & slotstat)) {
570 if (!ci->slot_stat) {
571 ci->slot_stat |=
572 DVB_CA_EN50221_POLL_CAM_PRESENT;
573 write_regm(ci, 0x03, 0x08, 0x08);
574 }
575
576 } else {
577 if (ci->slot_stat) {
578 ci->slot_stat = 0;
579 write_regm(ci, 0x03, 0x00, 0x08);
580 dev_info(&ci->i2c->dev, "NO CAM\n");
581 ci->ready = 0;
582 }
583 }
584 if ((istat & 8) &&
585 ci->slot_stat == DVB_CA_EN50221_POLL_CAM_PRESENT) {
586 ci->ready = 1;
587 ci->slot_stat |= DVB_CA_EN50221_POLL_CAM_READY;
588 }
589 }
590 return 0;
591}
592
593static int poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
594{
595 struct cxd *ci = ca->data;
596 u8 slotstat;
597
598 mutex_lock(&ci->lock);
599 campoll(ci);
600 read_reg(ci, 0x01, &slotstat);
601 mutex_unlock(&ci->lock);
602
603 return ci->slot_stat;
604}
605
606static int read_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
607{
608 struct cxd *ci = ca->data;
609 u8 msb, lsb;
610 u16 len;
611
612 mutex_lock(&ci->lock);
613 campoll(ci);
614 mutex_unlock(&ci->lock);
615
616 if (!ci->dr)
617 return 0;
618
619 mutex_lock(&ci->lock);
620 read_reg(ci, 0x0f, &msb);
621 read_reg(ci, 0x10, &lsb);
622 len = ((u16)msb << 8) | lsb;
623 if (len > ecount || len < 2) {
624
625 read_block(ci, 0x12, ci->rbuf, len);
626 mutex_unlock(&ci->lock);
627 return -EIO;
628 }
629 read_block(ci, 0x12, ebuf, len);
630 ci->dr = 0;
631 mutex_unlock(&ci->lock);
632 return len;
633}
634
635static int write_data(struct dvb_ca_en50221 *ca, int slot, u8 *ebuf, int ecount)
636{
637 struct cxd *ci = ca->data;
638
639 if (ci->write_busy)
640 return -EAGAIN;
641 mutex_lock(&ci->lock);
642 write_reg(ci, 0x0d, ecount >> 8);
643 write_reg(ci, 0x0e, ecount & 0xff);
644 write_block(ci, 0x11, ebuf, ecount);
645 ci->write_busy = 1;
646 mutex_unlock(&ci->lock);
647 return ecount;
648}
649
650static struct dvb_ca_en50221 en_templ = {
651 .read_attribute_mem = read_attribute_mem,
652 .write_attribute_mem = write_attribute_mem,
653 .read_cam_control = read_cam_control,
654 .write_cam_control = write_cam_control,
655 .slot_reset = slot_reset,
656 .slot_shutdown = slot_shutdown,
657 .slot_ts_enable = slot_ts_enable,
658 .poll_slot_status = poll_slot_status,
659 .read_data = read_data,
660 .write_data = write_data,
661};
662
663struct dvb_ca_en50221 *cxd2099_attach(struct cxd2099_cfg *cfg,
664 void *priv,
665 struct i2c_adapter *i2c)
666{
667 struct cxd *ci;
668 u8 val;
669
670 if (i2c_read_reg(i2c, cfg->adr, 0, &val) < 0) {
671 dev_info(&i2c->dev, "No CXD2099AR detected at 0x%02x\n",
672 cfg->adr);
673 return NULL;
674 }
675
676 ci = kzalloc(sizeof(*ci), GFP_KERNEL);
677 if (!ci)
678 return NULL;
679
680 mutex_init(&ci->lock);
681 ci->cfg = *cfg;
682 ci->i2c = i2c;
683 ci->lastaddress = 0xff;
684 ci->clk_reg_b = 0x4a;
685 ci->clk_reg_f = 0x1b;
686
687 ci->en = en_templ;
688 ci->en.data = ci;
689 init(ci);
690 dev_info(&i2c->dev, "Attached CXD2099AR at 0x%02x\n", ci->cfg.adr);
691
692 if (!buffermode) {
693 ci->en.read_data = NULL;
694 ci->en.write_data = NULL;
695 } else {
696 dev_info(&i2c->dev, "Using CXD2099AR buffer mode");
697 }
698
699 return &ci->en;
700}
701EXPORT_SYMBOL(cxd2099_attach);
702
703MODULE_DESCRIPTION("CXD2099AR Common Interface controller driver");
704MODULE_AUTHOR("Ralph Metzler");
705MODULE_LICENSE("GPL");
706
