LXR linux/include/uapi/drm/etnaviv

   1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2/*
   3 * Copyright (C) 2015 Etnaviv Project
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of the GNU General Public License version 2 as published by
   7 * the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * You should have received a copy of the GNU General Public License along with
  15 * this program.  If not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#ifndef __ETNAVIV_DRM_H__
  19#define __ETNAVIV_DRM_H__
  20
  21#include "drm.h"
  22
  23#if defined(__cplusplus)
  24extern "C" {
  25#endif
  26
  27/* Please note that modifications to all structs defined here are
  28 * subject to backwards-compatibility constraints:
  29 *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
  30 *     user/kernel compatibility
  31 *  2) Keep fields aligned to their size
  32 *  3) Because of how drm_ioctl() works, we can add new fields at
  33 *     the end of an ioctl if some care is taken: drm_ioctl() will
  34 *     zero out the new fields at the tail of the ioctl, so a zero
  35 *     value should have a backwards compatible meaning.  And for
  36 *     output params, userspace won't see the newly added output
  37 *     fields.. so that has to be somehow ok.
  38 */
  39
  40/* timeouts are specified in clock-monotonic absolute times (to simplify
  41 * restarting interrupted ioctls).  The following struct is logically the
  42 * same as 'struct timespec' but 32/64b ABI safe.
  43 */
  44struct drm_etnaviv_timespec {
  45        __s64 tv_sec;          /* seconds */
  46        __s64 tv_nsec;         /* nanoseconds */
  47};
  48
  49#define ETNAVIV_PARAM_GPU_MODEL                     0x01
  50#define ETNAVIV_PARAM_GPU_REVISION                  0x02
  51#define ETNAVIV_PARAM_GPU_FEATURES_0                0x03
  52#define ETNAVIV_PARAM_GPU_FEATURES_1                0x04
  53#define ETNAVIV_PARAM_GPU_FEATURES_2                0x05
  54#define ETNAVIV_PARAM_GPU_FEATURES_3                0x06
  55#define ETNAVIV_PARAM_GPU_FEATURES_4                0x07
  56#define ETNAVIV_PARAM_GPU_FEATURES_5                0x08
  57#define ETNAVIV_PARAM_GPU_FEATURES_6                0x09
  58
  59#define ETNAVIV_PARAM_GPU_STREAM_COUNT              0x10
  60#define ETNAVIV_PARAM_GPU_REGISTER_MAX              0x11
  61#define ETNAVIV_PARAM_GPU_THREAD_COUNT              0x12
  62#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE         0x13
  63#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT         0x14
  64#define ETNAVIV_PARAM_GPU_PIXEL_PIPES               0x15
  65#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
  66#define ETNAVIV_PARAM_GPU_BUFFER_SIZE               0x17
  67#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT         0x18
  68#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS             0x19
  69#define ETNAVIV_PARAM_GPU_NUM_VARYINGS              0x1a
  70
  71#define ETNA_MAX_PIPES 4
  72
  73struct drm_etnaviv_param {
  74        __u32 pipe;           /* in */
  75        __u32 param;          /* in, ETNAVIV_PARAM_x */
  76        __u64 value;          /* out (get_param) or in (set_param) */
  77};
  78
  79/*
  80 * GEM buffers:
  81 */
  82
  83#define ETNA_BO_CACHE_MASK   0x000f0000
  84/* cache modes */
  85#define ETNA_BO_CACHED       0x00010000
  86#define ETNA_BO_WC           0x00020000
  87#define ETNA_BO_UNCACHED     0x00040000
  88/* map flags */
  89#define ETNA_BO_FORCE_MMU    0x00100000
  90
  91struct drm_etnaviv_gem_new {
  92        __u64 size;           /* in */
  93        __u32 flags;          /* in, mask of ETNA_BO_x */
  94        __u32 handle;         /* out */
  95};
  96
  97struct drm_etnaviv_gem_info {
  98        __u32 handle;         /* in */
  99        __u32 pad;
 100        __u64 offset;         /* out, offset to pass to mmap() */
 101};
 102
 103#define ETNA_PREP_READ        0x01
 104#define ETNA_PREP_WRITE       0x02
 105#define ETNA_PREP_NOSYNC      0x04
 106
 107struct drm_etnaviv_gem_cpu_prep {
 108        __u32 handle;         /* in */
 109        __u32 op;             /* in, mask of ETNA_PREP_x */
 110        struct drm_etnaviv_timespec timeout;   /* in */
 111};
 112
 113struct drm_etnaviv_gem_cpu_fini {
 114        __u32 handle;         /* in */
 115        __u32 flags;          /* in, placeholder for now, no defined values */
 116};
 117
 118/*
 119 * Cmdstream Submission:
 120 */
 121
 122/* The value written into the cmdstream is logically:
 123 * relocbuf->gpuaddr + reloc_offset
 124 *
 125 * NOTE that reloc's must be sorted by order of increasing submit_offset,
 126 * otherwise EINVAL.
 127 */
 128struct drm_etnaviv_gem_submit_reloc {
 129        __u32 submit_offset;  /* in, offset from submit_bo */
 130        __u32 reloc_idx;      /* in, index of reloc_bo buffer */
 131        __u64 reloc_offset;   /* in, offset from start of reloc_bo */
 132        __u32 flags;          /* in, placeholder for now, no defined values */
 133};
 134
 135/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
 136 * cmdstream buffer(s) themselves or reloc entries) has one (and only
 137 * one) entry in the submit->bos[] table.
 138 *
 139 * As a optimization, the current buffer (gpu virtual address) can be
 140 * passed back through the 'presumed' field.  If on a subsequent reloc,
 141 * userspace passes back a 'presumed' address that is still valid,
 142 * then patching the cmdstream for this entry is skipped.  This can
 143 * avoid kernel needing to map/access the cmdstream bo in the common
 144 * case.
 145 */
 146#define ETNA_SUBMIT_BO_READ             0x0001
 147#define ETNA_SUBMIT_BO_WRITE            0x0002
 148struct drm_etnaviv_gem_submit_bo {
 149        __u32 flags;          /* in, mask of ETNA_SUBMIT_BO_x */
 150        __u32 handle;         /* in, GEM handle */
 151        __u64 presumed;       /* in/out, presumed buffer address */
 152};
 153
 154/* performance monitor request (pmr) */
 155#define ETNA_PM_PROCESS_PRE             0x0001
 156#define ETNA_PM_PROCESS_POST            0x0002
 157struct drm_etnaviv_gem_submit_pmr {
 158        __u32 flags;          /* in, when to process request (ETNA_PM_PROCESS_x) */
 159        __u8  domain;         /* in, pm domain */
 160        __u8  pad;
 161        __u16 signal;         /* in, pm signal */
 162        __u32 sequence;       /* in, sequence number */
 163        __u32 read_offset;    /* in, offset from read_bo */
 164        __u32 read_idx;       /* in, index of read_bo buffer */
 165};
 166
 167/* Each cmdstream submit consists of a table of buffers involved, and
 168 * one or more cmdstream buffers.  This allows for conditional execution
 169 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
 170 */
 171#define ETNA_SUBMIT_NO_IMPLICIT         0x0001
 172#define ETNA_SUBMIT_FENCE_FD_IN         0x0002
 173#define ETNA_SUBMIT_FENCE_FD_OUT        0x0004
 174#define ETNA_SUBMIT_FLAGS               (ETNA_SUBMIT_NO_IMPLICIT | \
 175                                         ETNA_SUBMIT_FENCE_FD_IN | \
 176                                         ETNA_SUBMIT_FENCE_FD_OUT)
 177#define ETNA_PIPE_3D      0x00
 178#define ETNA_PIPE_2D      0x01
 179#define ETNA_PIPE_VG      0x02
 180struct drm_etnaviv_gem_submit {
 181        __u32 fence;          /* out */
 182        __u32 pipe;           /* in */
 183        __u32 exec_state;     /* in, initial execution state (ETNA_PIPE_x) */
 184        __u32 nr_bos;         /* in, number of submit_bo's */
 185        __u32 nr_relocs;      /* in, number of submit_reloc's */
 186        __u32 stream_size;    /* in, cmdstream size */
 187        __u64 bos;            /* in, ptr to array of submit_bo's */
 188        __u64 relocs;         /* in, ptr to array of submit_reloc's */
 189        __u64 stream;         /* in, ptr to cmdstream */
 190        __u32 flags;          /* in, mask of ETNA_SUBMIT_x */
 191        __s32 fence_fd;       /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
 192        __u64 pmrs;           /* in, ptr to array of submit_pmr's */
 193        __u32 nr_pmrs;        /* in, number of submit_pmr's */
 194        __u32 pad;
 195};
 196
 197/* The normal way to synchronize with the GPU is just to CPU_PREP on
 198 * a buffer if you need to access it from the CPU (other cmdstream
 199 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
 200 * handle the required synchronization under the hood).  This ioctl
 201 * mainly just exists as a way to implement the gallium pipe_fence
 202 * APIs without requiring a dummy bo to synchronize on.
 203 */
 204#define ETNA_WAIT_NONBLOCK      0x01
 205struct drm_etnaviv_wait_fence {
 206        __u32 pipe;           /* in */
 207        __u32 fence;          /* in */
 208        __u32 flags;          /* in, mask of ETNA_WAIT_x */
 209        __u32 pad;
 210        struct drm_etnaviv_timespec timeout;   /* in */
 211};
 212
 213#define ETNA_USERPTR_READ       0x01
 214#define ETNA_USERPTR_WRITE      0x02
 215struct drm_etnaviv_gem_userptr {
 216        __u64 user_ptr; /* in, page aligned user pointer */
 217        __u64 user_size;        /* in, page aligned user size */
 218        __u32 flags;            /* in, flags */
 219        __u32 handle;   /* out, non-zero handle */
 220};
 221
 222struct drm_etnaviv_gem_wait {
 223        __u32 pipe;                             /* in */
 224        __u32 handle;                           /* in, bo to be waited for */
 225        __u32 flags;                            /* in, mask of ETNA_WAIT_x  */
 226        __u32 pad;
 227        struct drm_etnaviv_timespec timeout;    /* in */
 228};
 229
 230/*
 231 * Performance Monitor (PM):
 232 */
 233
 234struct drm_etnaviv_pm_domain {
 235        __u32 pipe;       /* in */
 236        __u8  iter;       /* in/out, select pm domain at index iter */
 237        __u8  id;         /* out, id of domain */
 238        __u16 nr_signals; /* out, how many signals does this domain provide */
 239        char  name[64];   /* out, name of domain */
 240};
 241
 242struct drm_etnaviv_pm_signal {
 243        __u32 pipe;       /* in */
 244        __u8  domain;     /* in, pm domain index */
 245        __u8  pad;
 246        __u16 iter;       /* in/out, select pm source at index iter */
 247        __u16 id;         /* out, id of signal */
 248        char  name[64];   /* out, name of domain */
 249};
 250
 251#define DRM_ETNAVIV_GET_PARAM          0x00
 252/* placeholder:
 253#define DRM_ETNAVIV_SET_PARAM          0x01
 254 */
 255#define DRM_ETNAVIV_GEM_NEW            0x02
 256#define DRM_ETNAVIV_GEM_INFO           0x03
 257#define DRM_ETNAVIV_GEM_CPU_PREP       0x04
 258#define DRM_ETNAVIV_GEM_CPU_FINI       0x05
 259#define DRM_ETNAVIV_GEM_SUBMIT         0x06
 260#define DRM_ETNAVIV_WAIT_FENCE         0x07
 261#define DRM_ETNAVIV_GEM_USERPTR        0x08
 262#define DRM_ETNAVIV_GEM_WAIT           0x09
 263#define DRM_ETNAVIV_PM_QUERY_DOM       0x0a
 264#define DRM_ETNAVIV_PM_QUERY_SIG       0x0b
 265#define DRM_ETNAVIV_NUM_IOCTLS         0x0c
 266
 267#define DRM_IOCTL_ETNAVIV_GET_PARAM    DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
 268#define DRM_IOCTL_ETNAVIV_GEM_NEW      DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
 269#define DRM_IOCTL_ETNAVIV_GEM_INFO     DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
 270#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
 271#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
 272#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
 273#define DRM_IOCTL_ETNAVIV_WAIT_FENCE   DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
 274#define DRM_IOCTL_ETNAVIV_GEM_USERPTR  DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
 275#define DRM_IOCTL_ETNAVIV_GEM_WAIT     DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
 276#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
 277#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
 278
 279#if defined(__cplusplus)
 280}
 281#endif
 282
 283#endif /* __ETNAVIV_DRM_H__ */
 284