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17#include <linux/irqchip/arm-gic.h>
18#include <linux/kvm.h>
19#include <linux/kvm_host.h>
20#include <kvm/arm_vgic.h>
21#include <asm/kvm_mmu.h>
22
23#include "vgic.h"
24
25static inline void vgic_v2_write_lr(int lr, u32 val)
26{
27 void __iomem *base = kvm_vgic_global_state.vctrl_base;
28
29 writel_relaxed(val, base + GICH_LR0 + (lr * 4));
30}
31
32void vgic_v2_init_lrs(void)
33{
34 int i;
35
36 for (i = 0; i < kvm_vgic_global_state.nr_lr; i++)
37 vgic_v2_write_lr(i, 0);
38}
39
40void vgic_v2_set_npie(struct kvm_vcpu *vcpu)
41{
42 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
43
44 cpuif->vgic_hcr |= GICH_HCR_NPIE;
45}
46
47void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
48{
49 struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
50
51 cpuif->vgic_hcr |= GICH_HCR_UIE;
52}
53
54static bool lr_signals_eoi_mi(u32 lr_val)
55{
56 return !(lr_val & GICH_LR_STATE) && (lr_val & GICH_LR_EOI) &&
57 !(lr_val & GICH_LR_HW);
58}
59
60
61
62
63
64
65
66
67void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu)
68{
69 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
70 struct vgic_v2_cpu_if *cpuif = &vgic_cpu->vgic_v2;
71 int lr;
72 unsigned long flags;
73
74 cpuif->vgic_hcr &= ~(GICH_HCR_UIE | GICH_HCR_NPIE);
75
76 for (lr = 0; lr < vgic_cpu->used_lrs; lr++) {
77 u32 val = cpuif->vgic_lr[lr];
78 u32 intid = val & GICH_LR_VIRTUALID;
79 struct vgic_irq *irq;
80
81
82 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
83 kvm_notify_acked_irq(vcpu->kvm, 0,
84 intid - VGIC_NR_PRIVATE_IRQS);
85
86 irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
87
88 spin_lock_irqsave(&irq->irq_lock, flags);
89
90
91 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
92
93
94 if (irq->config == VGIC_CONFIG_EDGE &&
95 (val & GICH_LR_PENDING_BIT)) {
96 irq->pending_latch = true;
97
98 if (vgic_irq_is_sgi(intid)) {
99 u32 cpuid = val & GICH_LR_PHYSID_CPUID;
100
101 cpuid >>= GICH_LR_PHYSID_CPUID_SHIFT;
102 irq->source |= (1 << cpuid);
103 }
104 }
105
106
107
108
109
110 if (irq->config == VGIC_CONFIG_LEVEL) {
111 if (!(val & GICH_LR_PENDING_BIT))
112 irq->pending_latch = false;
113 }
114
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125
126
127
128 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT)) {
129 irq->line_level = vgic_get_phys_line_level(irq);
130
131 if (!irq->line_level)
132 vgic_irq_set_phys_active(irq, false);
133 }
134
135 spin_unlock_irqrestore(&irq->irq_lock, flags);
136 vgic_put_irq(vcpu->kvm, irq);
137 }
138
139 vgic_cpu->used_lrs = 0;
140}
141
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151
152
153void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr)
154{
155 u32 val = irq->intid;
156
157 if (irq_is_pending(irq)) {
158 val |= GICH_LR_PENDING_BIT;
159
160 if (irq->config == VGIC_CONFIG_EDGE)
161 irq->pending_latch = false;
162
163 if (vgic_irq_is_sgi(irq->intid)) {
164 u32 src = ffs(irq->source);
165
166 BUG_ON(!src);
167 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
168 irq->source &= ~(1 << (src - 1));
169 if (irq->source)
170 irq->pending_latch = true;
171 }
172 }
173
174 if (irq->active)
175 val |= GICH_LR_ACTIVE_BIT;
176
177 if (irq->hw) {
178 val |= GICH_LR_HW;
179 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
180
181
182
183
184
185 if (irq->active && irq_is_pending(irq))
186 val &= ~GICH_LR_PENDING_BIT;
187 } else {
188 if (irq->config == VGIC_CONFIG_LEVEL)
189 val |= GICH_LR_EOI;
190 }
191
192
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195
196
197
198 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
199 irq->line_level = false;
200
201
202 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
203
204 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;
205}
206
207void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr)
208{
209 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = 0;
210}
211
212void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
213{
214 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
215 u32 vmcr;
216
217 vmcr = (vmcrp->grpen0 << GICH_VMCR_ENABLE_GRP0_SHIFT) &
218 GICH_VMCR_ENABLE_GRP0_MASK;
219 vmcr |= (vmcrp->grpen1 << GICH_VMCR_ENABLE_GRP1_SHIFT) &
220 GICH_VMCR_ENABLE_GRP1_MASK;
221 vmcr |= (vmcrp->ackctl << GICH_VMCR_ACK_CTL_SHIFT) &
222 GICH_VMCR_ACK_CTL_MASK;
223 vmcr |= (vmcrp->fiqen << GICH_VMCR_FIQ_EN_SHIFT) &
224 GICH_VMCR_FIQ_EN_MASK;
225 vmcr |= (vmcrp->cbpr << GICH_VMCR_CBPR_SHIFT) &
226 GICH_VMCR_CBPR_MASK;
227 vmcr |= (vmcrp->eoim << GICH_VMCR_EOI_MODE_SHIFT) &
228 GICH_VMCR_EOI_MODE_MASK;
229 vmcr |= (vmcrp->abpr << GICH_VMCR_ALIAS_BINPOINT_SHIFT) &
230 GICH_VMCR_ALIAS_BINPOINT_MASK;
231 vmcr |= (vmcrp->bpr << GICH_VMCR_BINPOINT_SHIFT) &
232 GICH_VMCR_BINPOINT_MASK;
233 vmcr |= ((vmcrp->pmr >> GICV_PMR_PRIORITY_SHIFT) <<
234 GICH_VMCR_PRIMASK_SHIFT) & GICH_VMCR_PRIMASK_MASK;
235
236 cpu_if->vgic_vmcr = vmcr;
237}
238
239void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcrp)
240{
241 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
242 u32 vmcr;
243
244 vmcr = cpu_if->vgic_vmcr;
245
246 vmcrp->grpen0 = (vmcr & GICH_VMCR_ENABLE_GRP0_MASK) >>
247 GICH_VMCR_ENABLE_GRP0_SHIFT;
248 vmcrp->grpen1 = (vmcr & GICH_VMCR_ENABLE_GRP1_MASK) >>
249 GICH_VMCR_ENABLE_GRP1_SHIFT;
250 vmcrp->ackctl = (vmcr & GICH_VMCR_ACK_CTL_MASK) >>
251 GICH_VMCR_ACK_CTL_SHIFT;
252 vmcrp->fiqen = (vmcr & GICH_VMCR_FIQ_EN_MASK) >>
253 GICH_VMCR_FIQ_EN_SHIFT;
254 vmcrp->cbpr = (vmcr & GICH_VMCR_CBPR_MASK) >>
255 GICH_VMCR_CBPR_SHIFT;
256 vmcrp->eoim = (vmcr & GICH_VMCR_EOI_MODE_MASK) >>
257 GICH_VMCR_EOI_MODE_SHIFT;
258
259 vmcrp->abpr = (vmcr & GICH_VMCR_ALIAS_BINPOINT_MASK) >>
260 GICH_VMCR_ALIAS_BINPOINT_SHIFT;
261 vmcrp->bpr = (vmcr & GICH_VMCR_BINPOINT_MASK) >>
262 GICH_VMCR_BINPOINT_SHIFT;
263 vmcrp->pmr = ((vmcr & GICH_VMCR_PRIMASK_MASK) >>
264 GICH_VMCR_PRIMASK_SHIFT) << GICV_PMR_PRIORITY_SHIFT;
265}
266
267void vgic_v2_enable(struct kvm_vcpu *vcpu)
268{
269
270
271
272
273
274 vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0;
275 vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;
276
277
278 vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN;
279}
280
281
282static bool vgic_v2_check_base(gpa_t dist_base, gpa_t cpu_base)
283{
284 if (dist_base + KVM_VGIC_V2_DIST_SIZE < dist_base)
285 return false;
286 if (cpu_base + KVM_VGIC_V2_CPU_SIZE < cpu_base)
287 return false;
288
289 if (dist_base + KVM_VGIC_V2_DIST_SIZE <= cpu_base)
290 return true;
291 if (cpu_base + KVM_VGIC_V2_CPU_SIZE <= dist_base)
292 return true;
293
294 return false;
295}
296
297int vgic_v2_map_resources(struct kvm *kvm)
298{
299 struct vgic_dist *dist = &kvm->arch.vgic;
300 int ret = 0;
301
302 if (vgic_ready(kvm))
303 goto out;
304
305 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base) ||
306 IS_VGIC_ADDR_UNDEF(dist->vgic_cpu_base)) {
307 kvm_err("Need to set vgic cpu and dist addresses first\n");
308 ret = -ENXIO;
309 goto out;
310 }
311
312 if (!vgic_v2_check_base(dist->vgic_dist_base, dist->vgic_cpu_base)) {
313 kvm_err("VGIC CPU and dist frames overlap\n");
314 ret = -EINVAL;
315 goto out;
316 }
317
318
319
320
321
322 ret = vgic_init(kvm);
323 if (ret) {
324 kvm_err("Unable to initialize VGIC dynamic data structures\n");
325 goto out;
326 }
327
328 ret = vgic_register_dist_iodev(kvm, dist->vgic_dist_base, VGIC_V2);
329 if (ret) {
330 kvm_err("Unable to register VGIC MMIO regions\n");
331 goto out;
332 }
333
334 if (!static_branch_unlikely(&vgic_v2_cpuif_trap)) {
335 ret = kvm_phys_addr_ioremap(kvm, dist->vgic_cpu_base,
336 kvm_vgic_global_state.vcpu_base,
337 KVM_VGIC_V2_CPU_SIZE, true);
338 if (ret) {
339 kvm_err("Unable to remap VGIC CPU to VCPU\n");
340 goto out;
341 }
342 }
343
344 dist->ready = true;
345
346out:
347 return ret;
348}
349
350DEFINE_STATIC_KEY_FALSE(vgic_v2_cpuif_trap);
351
352
353
354
355
356
357
358int vgic_v2_probe(const struct gic_kvm_info *info)
359{
360 int ret;
361 u32 vtr;
362
363 if (!info->vctrl.start) {
364 kvm_err("GICH not present in the firmware table\n");
365 return -ENXIO;
366 }
367
368 if (!PAGE_ALIGNED(info->vcpu.start) ||
369 !PAGE_ALIGNED(resource_size(&info->vcpu))) {
370 kvm_info("GICV region size/alignment is unsafe, using trapping (reduced performance)\n");
371 kvm_vgic_global_state.vcpu_base_va = ioremap(info->vcpu.start,
372 resource_size(&info->vcpu));
373 if (!kvm_vgic_global_state.vcpu_base_va) {
374 kvm_err("Cannot ioremap GICV\n");
375 return -ENOMEM;
376 }
377
378 ret = create_hyp_io_mappings(kvm_vgic_global_state.vcpu_base_va,
379 kvm_vgic_global_state.vcpu_base_va + resource_size(&info->vcpu),
380 info->vcpu.start);
381 if (ret) {
382 kvm_err("Cannot map GICV into hyp\n");
383 goto out;
384 }
385
386 static_branch_enable(&vgic_v2_cpuif_trap);
387 }
388
389 kvm_vgic_global_state.vctrl_base = ioremap(info->vctrl.start,
390 resource_size(&info->vctrl));
391 if (!kvm_vgic_global_state.vctrl_base) {
392 kvm_err("Cannot ioremap GICH\n");
393 ret = -ENOMEM;
394 goto out;
395 }
396
397 vtr = readl_relaxed(kvm_vgic_global_state.vctrl_base + GICH_VTR);
398 kvm_vgic_global_state.nr_lr = (vtr & 0x3f) + 1;
399
400 ret = create_hyp_io_mappings(kvm_vgic_global_state.vctrl_base,
401 kvm_vgic_global_state.vctrl_base +
402 resource_size(&info->vctrl),
403 info->vctrl.start);
404 if (ret) {
405 kvm_err("Cannot map VCTRL into hyp\n");
406 goto out;
407 }
408
409 ret = kvm_register_vgic_device(KVM_DEV_TYPE_ARM_VGIC_V2);
410 if (ret) {
411 kvm_err("Cannot register GICv2 KVM device\n");
412 goto out;
413 }
414
415 kvm_vgic_global_state.can_emulate_gicv2 = true;
416 kvm_vgic_global_state.vcpu_base = info->vcpu.start;
417 kvm_vgic_global_state.type = VGIC_V2;
418 kvm_vgic_global_state.max_gic_vcpus = VGIC_V2_MAX_CPUS;
419
420 kvm_debug("vgic-v2@%llx\n", info->vctrl.start);
421
422 return 0;
423out:
424 if (kvm_vgic_global_state.vctrl_base)
425 iounmap(kvm_vgic_global_state.vctrl_base);
426 if (kvm_vgic_global_state.vcpu_base_va)
427 iounmap(kvm_vgic_global_state.vcpu_base_va);
428
429 return ret;
430}
431
432void vgic_v2_load(struct kvm_vcpu *vcpu)
433{
434 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
435 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
436
437 writel_relaxed(cpu_if->vgic_vmcr, vgic->vctrl_base + GICH_VMCR);
438}
439
440void vgic_v2_put(struct kvm_vcpu *vcpu)
441{
442 struct vgic_v2_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v2;
443 struct vgic_dist *vgic = &vcpu->kvm->arch.vgic;
444
445 cpu_if->vgic_vmcr = readl_relaxed(vgic->vctrl_base + GICH_VMCR);
446}
447