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16#include <linux/string.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/ioport.h>
20#include <linux/kernel.h>
21#include <linux/bootmem.h>
22#include <linux/module.h>
23#include <linux/cache.h>
24#include <linux/slab.h>
25#include <linux/syscalls.h>
26#include <asm/machvec.h>
27
28#include "proto.h"
29#include "pci_impl.h"
30
31
32
33
34
35
36const char *const pci_io_names[] = {
37 "PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
38 "PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
39};
40
41const char *const pci_mem_names[] = {
42 "PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
43 "PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
44};
45
46const char pci_hae0_name[] = "HAE0";
47
48
49
50
51
52
53
54
55
56
57struct pci_controller *hose_head, **hose_tail = &hose_head;
58struct pci_controller *pci_isa_hose;
59
60
61
62
63
64static void quirk_isa_bridge(struct pci_dev *dev)
65{
66 dev->class = PCI_CLASS_BRIDGE_ISA << 8;
67}
68DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
69
70static void quirk_cypress(struct pci_dev *dev)
71{
72
73
74
75
76
77 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
78 dev->resource[2].start = dev->resource[3].start = 0;
79 dev->resource[2].end = dev->resource[3].end = 0;
80 dev->resource[2].flags = dev->resource[3].flags = 0;
81 if (PCI_FUNC(dev->devfn) == 2) {
82 dev->resource[0].start = 0x170;
83 dev->resource[0].end = 0x177;
84 dev->resource[1].start = 0x376;
85 dev->resource[1].end = 0x376;
86 }
87 }
88
89
90
91
92
93
94
95 if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
96 if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
97 __direct_map_size = 0xfff00000UL - __direct_map_base;
98 else {
99 struct pci_controller *hose = dev->sysdata;
100 struct pci_iommu_arena *pci = hose->sg_pci;
101 if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
102 pci->size = 0xfff00000UL - pci->dma_base;
103 }
104 }
105}
106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
107
108
109static void pcibios_fixup_final(struct pci_dev *dev)
110{
111 unsigned int class = dev->class >> 8;
112
113 if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
114 dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
115 isa_bridge = dev;
116 }
117}
118DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
119
120
121
122#define KB 1024
123#define MB (1024*KB)
124#define GB (1024*MB)
125
126resource_size_t
127pcibios_align_resource(void *data, const struct resource *res,
128 resource_size_t size, resource_size_t align)
129{
130 struct pci_dev *dev = data;
131 struct pci_controller *hose = dev->sysdata;
132 unsigned long alignto;
133 resource_size_t start = res->start;
134
135 if (res->flags & IORESOURCE_IO) {
136
137 if (start - hose->io_space->start < PCIBIOS_MIN_IO)
138 start = PCIBIOS_MIN_IO + hose->io_space->start;
139
140
141
142
143 if (start & 0x300)
144 start = (start + 0x3ff) & ~0x3ff;
145 }
146 else if (res->flags & IORESOURCE_MEM) {
147
148 if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
149 start = PCIBIOS_MIN_MEM + hose->mem_space->start;
150
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166
167
168 alignto = max_t(resource_size_t, 0x1000, align);
169 start = ALIGN(start, alignto);
170 if (hose->sparse_mem_base && size <= 7 * 16*MB) {
171 if (((start / (16*MB)) & 0x7) == 0) {
172 start &= ~(128*MB - 1);
173 start += 16*MB;
174 start = ALIGN(start, alignto);
175 }
176 if (start/(128*MB) != (start + size - 1)/(128*MB)) {
177 start &= ~(128*MB - 1);
178 start += (128 + 16)*MB;
179 start = ALIGN(start, alignto);
180 }
181 }
182 }
183
184 return start;
185}
186#undef KB
187#undef MB
188#undef GB
189
190static int __init
191pcibios_init(void)
192{
193 if (alpha_mv.init_pci)
194 alpha_mv.init_pci();
195 return 0;
196}
197
198subsys_initcall(pcibios_init);
199
200#ifdef ALPHA_RESTORE_SRM_SETUP
201
202struct pdev_srm_saved_conf
203{
204 struct pdev_srm_saved_conf *next;
205 struct pci_dev *dev;
206};
207
208static struct pdev_srm_saved_conf *srm_saved_configs;
209
210static void pdev_save_srm_config(struct pci_dev *dev)
211{
212 struct pdev_srm_saved_conf *tmp;
213 static int printed = 0;
214
215 if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
216 return;
217
218 if (!printed) {
219 printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
220 printed = 1;
221 }
222
223 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
224 if (!tmp) {
225 printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
226 return;
227 }
228 tmp->next = srm_saved_configs;
229 tmp->dev = dev;
230
231 pci_save_state(dev);
232
233 srm_saved_configs = tmp;
234}
235
236void
237pci_restore_srm_config(void)
238{
239 struct pdev_srm_saved_conf *tmp;
240
241
242 if (pci_has_flag(PCI_PROBE_ONLY))
243 return;
244
245
246 for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
247 pci_restore_state(tmp->dev);
248 }
249}
250#else
251#define pdev_save_srm_config(dev) do {} while (0)
252#endif
253
254void pcibios_fixup_bus(struct pci_bus *bus)
255{
256 struct pci_dev *dev = bus->self;
257
258 if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
259 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
260 pci_read_bridge_bases(bus);
261 }
262
263 list_for_each_entry(dev, &bus->devices, bus_list) {
264 pdev_save_srm_config(dev);
265 }
266}
267
268
269
270
271
272
273void
274pcibios_set_master(struct pci_dev *dev)
275{
276 u8 lat;
277 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
278 if (lat >= 16) return;
279 printk("PCI: Setting latency timer of device %s to 64\n",
280 pci_name(dev));
281 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
282}
283
284void __init
285pcibios_claim_one_bus(struct pci_bus *b)
286{
287 struct pci_dev *dev;
288 struct pci_bus *child_bus;
289
290 list_for_each_entry(dev, &b->devices, bus_list) {
291 int i;
292
293 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
294 struct resource *r = &dev->resource[i];
295
296 if (r->parent || !r->start || !r->flags)
297 continue;
298 if (pci_has_flag(PCI_PROBE_ONLY) ||
299 (r->flags & IORESOURCE_PCI_FIXED)) {
300 if (pci_claim_resource(dev, i) == 0)
301 continue;
302
303 pci_claim_bridge_resource(dev, i);
304 }
305 }
306 }
307
308 list_for_each_entry(child_bus, &b->children, node)
309 pcibios_claim_one_bus(child_bus);
310}
311
312static void __init
313pcibios_claim_console_setup(void)
314{
315 struct pci_bus *b;
316
317 list_for_each_entry(b, &pci_root_buses, node)
318 pcibios_claim_one_bus(b);
319}
320
321void __init
322common_init_pci(void)
323{
324 struct pci_controller *hose;
325 struct list_head resources;
326 struct pci_host_bridge *bridge;
327 struct pci_bus *bus;
328 int ret, next_busno;
329 int need_domain_info = 0;
330 u32 pci_mem_end;
331 u32 sg_base;
332 unsigned long end;
333
334
335 for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
336 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
337
338
339
340 pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
341 end = hose->mem_space->start + pci_mem_end;
342 if (hose->mem_space->end > end)
343 hose->mem_space->end = end;
344
345 INIT_LIST_HEAD(&resources);
346 pci_add_resource_offset(&resources, hose->io_space,
347 hose->io_space->start);
348 pci_add_resource_offset(&resources, hose->mem_space,
349 hose->mem_space->start);
350
351 bridge = pci_alloc_host_bridge(0);
352 if (!bridge)
353 continue;
354
355 list_splice_init(&resources, &bridge->windows);
356 bridge->dev.parent = NULL;
357 bridge->sysdata = hose;
358 bridge->busnr = next_busno;
359 bridge->ops = alpha_mv.pci_ops;
360 bridge->swizzle_irq = alpha_mv.pci_swizzle;
361 bridge->map_irq = alpha_mv.pci_map_irq;
362
363 ret = pci_scan_root_bus_bridge(bridge);
364 if (ret) {
365 pci_free_host_bridge(bridge);
366 continue;
367 }
368
369 bus = hose->bus = bridge->bus;
370 hose->need_domain_info = need_domain_info;
371 next_busno = bus->busn_res.end + 1;
372
373
374 if (next_busno > 224) {
375 next_busno = 0;
376 need_domain_info = 1;
377 }
378 }
379
380 pcibios_claim_console_setup();
381
382 pci_assign_unassigned_resources();
383 for (hose = hose_head; hose; hose = hose->next) {
384 bus = hose->bus;
385 if (bus)
386 pci_bus_add_devices(bus);
387 }
388}
389
390struct pci_controller * __init
391alloc_pci_controller(void)
392{
393 struct pci_controller *hose;
394
395 hose = alloc_bootmem(sizeof(*hose));
396
397 *hose_tail = hose;
398 hose_tail = &hose->next;
399
400 return hose;
401}
402
403struct resource * __init
404alloc_resource(void)
405{
406 return alloc_bootmem(sizeof(struct resource));
407}
408
409
410
411
412
413SYSCALL_DEFINE3(pciconfig_iobase, long, which, unsigned long, bus,
414 unsigned long, dfn)
415{
416 struct pci_controller *hose;
417 struct pci_dev *dev;
418
419
420 if (which & IOBASE_FROM_HOSE) {
421 for(hose = hose_head; hose; hose = hose->next)
422 if (hose->index == bus) break;
423 if (!hose) return -ENODEV;
424 } else {
425
426 if (bus == 0 && dfn == 0) {
427 hose = pci_isa_hose;
428 } else {
429 dev = pci_get_domain_bus_and_slot(0, bus, dfn);
430 if (!dev)
431 return -ENODEV;
432 hose = dev->sysdata;
433 pci_dev_put(dev);
434 }
435 }
436
437 switch (which & ~IOBASE_FROM_HOSE) {
438 case IOBASE_HOSE:
439 return hose->index;
440 case IOBASE_SPARSE_MEM:
441 return hose->sparse_mem_base;
442 case IOBASE_DENSE_MEM:
443 return hose->dense_mem_base;
444 case IOBASE_SPARSE_IO:
445 return hose->sparse_io_base;
446 case IOBASE_DENSE_IO:
447 return hose->dense_io_base;
448 case IOBASE_ROOT_BUS:
449 return hose->bus->number;
450 }
451
452 return -EOPNOTSUPP;
453}
454
455
456
457void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
458{
459 if (__is_mmio(addr))
460 iounmap(addr);
461}
462
463EXPORT_SYMBOL(pci_iounmap);
464
465
466struct pci_dev *isa_bridge;
467EXPORT_SYMBOL(isa_bridge);
468