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28#include <linux/linkage.h>
29#include <linux/init.h>
30#include <asm/assembler.h>
31#include <asm/hwcap.h>
32#include <asm/pgtable-hwdef.h>
33#include <asm/pgtable.h>
34#include <asm/page.h>
35#include <asm/ptrace.h>
36#include "proc-macros.S"
37
38
39
40
41#define CACHE_DLINESIZE 32
42
43
44
45
46#define CACHE_DSEGMENTS 8
47
48
49
50
51#define CACHE_DENTRIES 64
52
53
54
55
56
57
58#define CACHE_DLIMIT 65536
59
60
61 .text
62
63
64
65ENTRY(cpu_arm920_proc_init)
66 ret lr
67
68
69
70
71ENTRY(cpu_arm920_proc_fin)
72 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
73 bic r0, r0,
74 bic r0, r0,
75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
76 ret lr
77
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83
84
85
86
87 .align 5
88 .pushsection .idmap.text, "ax"
89ENTRY(cpu_arm920_reset)
90 mov ip,
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
92 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93#ifdef CONFIG_MMU
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
95#endif
96 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
97 bic ip, ip,
98 bic ip, ip,
99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
100 ret r0
101ENDPROC(cpu_arm920_reset)
102 .popsection
103
104
105
106
107 .align 5
108ENTRY(cpu_arm920_do_idle)
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
110 ret lr
111
112
113#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
114
115
116
117
118
119
120ENTRY(arm920_flush_icache_all)
121 mov r0,
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
123 ret lr
124ENDPROC(arm920_flush_icache_all)
125
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130
131
132ENTRY(arm920_flush_user_cache_all)
133
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139
140ENTRY(arm920_flush_kern_cache_all)
141 mov r2,
142 mov ip,
143__flush_whole_cache:
144 mov r1,
1451: orr r3, r1,
1462: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
147 subs r3, r3,
148 bcs 2b @ entries 63 to 0
149 subs r1, r1,
150 bcs 1b @ segments 7 to 0
151 tst r2,
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
154 ret lr
155
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163
164
165
166ENTRY(arm920_flush_user_cache_range)
167 mov ip,
168 sub r3, r1, r0 @ calculate total size
169 cmp r3,
170 bhs __flush_whole_cache
171
1721: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
173 tst r2,
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0,
176 cmp r0, r1
177 blo 1b
178 tst r2,
179 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
180 ret lr
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190
191
192ENTRY(arm920_coherent_kern_range)
193
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205ENTRY(arm920_coherent_user_range)
206 bic r0, r0,
2071: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 add r0, r0,
210 cmp r0, r1
211 blo 1b
212 mcr p15, 0, r0, c7, c10, 4 @ drain WB
213 mov r0,
214 ret lr
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224
225ENTRY(arm920_flush_kern_dcache_area)
226 add r1, r0, r1
2271: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
228 add r0, r0,
229 cmp r0, r1
230 blo 1b
231 mov r0,
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
233 mcr p15, 0, r0, c7, c10, 4 @ drain WB
234 ret lr
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248
249arm920_dma_inv_range:
250 tst r0,
251 bic r0, r0,
252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
253 tst r1,
254 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
2551: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
256 add r0, r0,
257 cmp r0, r1
258 blo 1b
259 mcr p15, 0, r0, c7, c10, 4 @ drain WB
260 ret lr
261
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271
272arm920_dma_clean_range:
273 bic r0, r0,
2741: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
275 add r0, r0,
276 cmp r0, r1
277 blo 1b
278 mcr p15, 0, r0, c7, c10, 4 @ drain WB
279 ret lr
280
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288
289ENTRY(arm920_dma_flush_range)
290 bic r0, r0,
2911: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
292 add r0, r0,
293 cmp r0, r1
294 blo 1b
295 mcr p15, 0, r0, c7, c10, 4 @ drain WB
296 ret lr
297
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301
302
303
304ENTRY(arm920_dma_map_area)
305 add r1, r1, r0
306 cmp r2,
307 beq arm920_dma_clean_range
308 bcs arm920_dma_inv_range
309 b arm920_dma_flush_range
310ENDPROC(arm920_dma_map_area)
311
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318ENTRY(arm920_dma_unmap_area)
319 ret lr
320ENDPROC(arm920_dma_unmap_area)
321
322 .globl arm920_flush_kern_cache_louis
323 .equ arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all
324
325 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
326 define_cache_functions arm920
327#endif
328
329
330ENTRY(cpu_arm920_dcache_clean_area)
3311: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
332 add r0, r0,
333 subs r1, r1,
334 bhi 1b
335 ret lr
336
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344
345
346 .align 5
347ENTRY(cpu_arm920_switch_mm)
348#ifdef CONFIG_MMU
349 mov ip,
350#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
351 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
352#else
353@ && 'Clean & Invalidate whole DCache'
354@ && Re-written to use Index Ops.
355@ && Uses registers r1, r3 and ip
356
357 mov r1,
3581: orr r3, r1,
3592: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
360 subs r3, r3,
361 bcs 2b @ entries 63 to 0
362 subs r1, r1,
363 bcs 1b @ segments 7 to 0
364#endif
365 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
366 mcr p15, 0, ip, c7, c10, 4 @ drain WB
367 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
368 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
369#endif
370 ret lr
371
372
373
374
375
376
377 .align 5
378ENTRY(cpu_arm920_set_pte_ext)
379#ifdef CONFIG_MMU
380 armv3_set_pte_ext
381 mov r0, r0
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
383 mcr p15, 0, r0, c7, c10, 4 @ drain WB
384#endif
385 ret lr
386
387
388.globl cpu_arm920_suspend_size
389.equ cpu_arm920_suspend_size, 4 * 3
390#ifdef CONFIG_ARM_CPU_SUSPEND
391ENTRY(cpu_arm920_do_suspend)
392 stmfd sp!, {r4 - r6, lr}
393 mrc p15, 0, r4, c13, c0, 0 @ PID
394 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
395 mrc p15, 0, r6, c1, c0, 0 @ Control register
396 stmia r0, {r4 - r6}
397 ldmfd sp!, {r4 - r6, pc}
398ENDPROC(cpu_arm920_do_suspend)
399
400ENTRY(cpu_arm920_do_resume)
401 mov ip,
402 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
403 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
404 ldmia r0, {r4 - r6}
405 mcr p15, 0, r4, c13, c0, 0 @ PID
406 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
407 mcr p15, 0, r1, c2, c0, 0 @ TTB address
408 mov r0, r6 @ control register
409 b cpu_resume_mmu
410ENDPROC(cpu_arm920_do_resume)
411#endif
412
413 .type __arm920_setup,
414__arm920_setup:
415 mov r0,
416 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
417 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
418#ifdef CONFIG_MMU
419 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
420#endif
421 adr r5, arm920_crval
422 ldmia r5, {r5, r6}
423 mrc p15, 0, r0, c1, c0 @ get control register v4
424 bic r0, r0, r5
425 orr r0, r0, r6
426 ret lr
427 .size __arm920_setup, . - __arm920_setup
428
429
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431
432
433
434
435 .type arm920_crval,
436arm920_crval:
437 crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
438
439 __INITDATA
440 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
441 define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1
442
443 .section ".rodata"
444
445 string cpu_arch_name, "armv4t"
446 string cpu_elf_name, "v4"
447 string cpu_arm920_name, "ARM920T"
448
449 .align
450
451 .section ".proc.info.init",
452
453 .type __arm920_proc_info,
454__arm920_proc_info:
455 .long 0x41009200
456 .long 0xff00fff0
457 .long PMD_TYPE_SECT | \
458 PMD_SECT_BUFFERABLE | \
459 PMD_SECT_CACHEABLE | \
460 PMD_BIT4 | \
461 PMD_SECT_AP_WRITE | \
462 PMD_SECT_AP_READ
463 .long PMD_TYPE_SECT | \
464 PMD_BIT4 | \
465 PMD_SECT_AP_WRITE | \
466 PMD_SECT_AP_READ
467 initfn __arm920_setup, __arm920_proc_info
468 .long cpu_arch_name
469 .long cpu_elf_name
470 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
471 .long cpu_arm920_name
472 .long arm920_processor_functions
473 .long v4wbi_tlb_fns
474 .long v4wb_user_fns
475#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
476 .long arm920_cache_fns
477#else
478 .long v4wt_cache_fns
479#endif
480 .size __arm920_proc_info, . - __arm920_proc_info
481