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23#include <linux/linkage.h>
24#include <linux/init.h>
25#include <asm/assembler.h>
26#include <asm/hwcap.h>
27#include <asm/pgtable-hwdef.h>
28#include <asm/pgtable.h>
29#include <asm/page.h>
30#include <asm/ptrace.h>
31#include "proc-macros.S"
32
33
34
35
36
37#define CACHE_DLIMIT 32768
38
39
40
41
42#define CACHE_DLINESIZE 32
43
44
45
46
47ENTRY(cpu_mohawk_proc_init)
48 ret lr
49
50
51
52
53ENTRY(cpu_mohawk_proc_fin)
54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
55 bic r0, r0,
56 bic r0, r0,
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 ret lr
59
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69
70
71 .align 5
72 .pushsection .idmap.text, "ax"
73ENTRY(cpu_mohawk_reset)
74 mov ip,
75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
76 mcr p15, 0, ip, c7, c10, 4 @ drain WB
77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
79 bic ip, ip,
80 bic ip, ip,
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
82 ret r0
83ENDPROC(cpu_mohawk_reset)
84 .popsection
85
86
87
88
89
90
91 .align 5
92ENTRY(cpu_mohawk_do_idle)
93 mov r0,
94 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
95 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
96 ret lr
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102
103ENTRY(mohawk_flush_icache_all)
104 mov r0,
105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
106 ret lr
107ENDPROC(mohawk_flush_icache_all)
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114
115ENTRY(mohawk_flush_user_cache_all)
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122
123ENTRY(mohawk_flush_kern_cache_all)
124 mov r2,
125 mov ip,
126__flush_whole_cache:
127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
128 tst r2,
129 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
130 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer
131 ret lr
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144
145ENTRY(mohawk_flush_user_cache_range)
146 mov ip,
147 sub r3, r1, r0 @ calculate total size
148 cmp r3,
149 bgt __flush_whole_cache
1501: tst r2,
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
153 add r0, r0,
154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
156 add r0, r0,
157 cmp r0, r1
158 blo 1b
159 tst r2,
160 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
161 ret lr
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172
173ENTRY(mohawk_coherent_kern_range)
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188ENTRY(mohawk_coherent_user_range)
189 bic r0, r0,
1901: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
191 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
192 add r0, r0,
193 cmp r0, r1
194 blo 1b
195 mcr p15, 0, r0, c7, c10, 4 @ drain WB
196 mov r0,
197 ret lr
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207
208ENTRY(mohawk_flush_kern_dcache_area)
209 add r1, r0, r1
2101: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
211 add r0, r0,
212 cmp r0, r1
213 blo 1b
214 mov r0,
215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
216 mcr p15, 0, r0, c7, c10, 4 @ drain WB
217 ret lr
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231
232mohawk_dma_inv_range:
233 tst r0,
234 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
235 tst r1,
236 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
237 bic r0, r0,
2381: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
239 add r0, r0,
240 cmp r0, r1
241 blo 1b
242 mcr p15, 0, r0, c7, c10, 4 @ drain WB
243 ret lr
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254
255mohawk_dma_clean_range:
256 bic r0, r0,
2571: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
258 add r0, r0,
259 cmp r0, r1
260 blo 1b
261 mcr p15, 0, r0, c7, c10, 4 @ drain WB
262 ret lr
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271
272ENTRY(mohawk_dma_flush_range)
273 bic r0, r0,
2741:
275 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
276 add r0, r0,
277 cmp r0, r1
278 blo 1b
279 mcr p15, 0, r0, c7, c10, 4 @ drain WB
280 ret lr
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287
288ENTRY(mohawk_dma_map_area)
289 add r1, r1, r0
290 cmp r2,
291 beq mohawk_dma_clean_range
292 bcs mohawk_dma_inv_range
293 b mohawk_dma_flush_range
294ENDPROC(mohawk_dma_map_area)
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302ENTRY(mohawk_dma_unmap_area)
303 ret lr
304ENDPROC(mohawk_dma_unmap_area)
305
306 .globl mohawk_flush_kern_cache_louis
307 .equ mohawk_flush_kern_cache_louis, mohawk_flush_kern_cache_all
308
309 @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
310 define_cache_functions mohawk
311
312ENTRY(cpu_mohawk_dcache_clean_area)
3131: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
314 add r0, r0,
315 subs r1, r1,
316 bhi 1b
317 mcr p15, 0, r0, c7, c10, 4 @ drain WB
318 ret lr
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326
327 .align 5
328ENTRY(cpu_mohawk_switch_mm)
329 mov ip,
330 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
331 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
332 mcr p15, 0, ip, c7, c10, 4 @ drain WB
333 orr r0, r0,
334 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
335 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
336 ret lr
337
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341
342
343 .align 5
344ENTRY(cpu_mohawk_set_pte_ext)
345#ifdef CONFIG_MMU
346 armv3_set_pte_ext
347 mov r0, r0
348 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
349 mcr p15, 0, r0, c7, c10, 4 @ drain WB
350 ret lr
351#endif
352
353.globl cpu_mohawk_suspend_size
354.equ cpu_mohawk_suspend_size, 4 * 6
355#ifdef CONFIG_ARM_CPU_SUSPEND
356ENTRY(cpu_mohawk_do_suspend)
357 stmfd sp!, {r4 - r9, lr}
358 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
359 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
360 mrc p15, 0, r6, c13, c0, 0 @ PID
361 mrc p15, 0, r7, c3, c0, 0 @ domain ID
362 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
363 mrc p15, 0, r9, c1, c0, 0 @ control reg
364 bic r4, r4,
365 stmia r0, {r4 - r9} @ store cp regs
366 ldmia sp!, {r4 - r9, pc}
367ENDPROC(cpu_mohawk_do_suspend)
368
369ENTRY(cpu_mohawk_do_resume)
370 ldmia r0, {r4 - r9} @ load cp regs
371 mov ip,
372 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
373 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
374 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
375 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
376 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
377 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
378 mcr p15, 0, r6, c13, c0, 0 @ PID
379 mcr p15, 0, r7, c3, c0, 0 @ domain ID
380 orr r1, r1,
381 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
382 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
383 mov r0, r9 @ control register
384 b cpu_resume_mmu
385ENDPROC(cpu_mohawk_do_resume)
386#endif
387
388 .type __mohawk_setup,
389__mohawk_setup:
390 mov r0,
391 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
392 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
393 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
394 orr r4, r4,
395 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
396
397 mov r0,
398 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
399
400 adr r5, mohawk_crval
401 ldmia r5, {r5, r6}
402 mrc p15, 0, r0, c1, c0 @ get control register
403 bic r0, r0, r5
404 orr r0, r0, r6
405 ret lr
406
407 .size __mohawk_setup, . - __mohawk_setup
408
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412
413
414
415 .type mohawk_crval,
416mohawk_crval:
417 crval clear=0x00007f3f, mmuset=0x00003905, ucset=0x00001134
418
419 __INITDATA
420
421 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
422 define_processor_functions mohawk, dabort=v5t_early_abort, pabort=legacy_pabort
423
424 .section ".rodata"
425
426 string cpu_arch_name, "armv5te"
427 string cpu_elf_name, "v5"
428 string cpu_mohawk_name, "Marvell 88SV331x"
429
430 .align
431
432 .section ".proc.info.init",
433
434 .type __88sv331x_proc_info,
435__88sv331x_proc_info:
436 .long 0x56158000 @ Marvell 88SV331x (MOHAWK)
437 .long 0xfffff000
438 .long PMD_TYPE_SECT | \
439 PMD_SECT_BUFFERABLE | \
440 PMD_SECT_CACHEABLE | \
441 PMD_BIT4 | \
442 PMD_SECT_AP_WRITE | \
443 PMD_SECT_AP_READ
444 .long PMD_TYPE_SECT | \
445 PMD_BIT4 | \
446 PMD_SECT_AP_WRITE | \
447 PMD_SECT_AP_READ
448 initfn __mohawk_setup, __88sv331x_proc_info
449 .long cpu_arch_name
450 .long cpu_elf_name
451 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
452 .long cpu_mohawk_name
453 .long mohawk_processor_functions
454 .long v4wbi_tlb_fns
455 .long v4wb_user_fns
456 .long mohawk_cache_fns
457 .size __88sv331x_proc_info, . - __88sv331x_proc_info
458