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19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/shmem_fs.h>
26#include <linux/list.h>
27#include <linux/syscalls.h>
28#include <linux/irq.h>
29#include <linux/vmalloc.h>
30#include <linux/slab.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/of_pci.h>
35#include <linux/export.h>
36
37#include <asm/processor.h>
38#include <linux/io.h>
39#include <asm/pci-bridge.h>
40#include <asm/byteorder.h>
41
42static DEFINE_SPINLOCK(hose_spinlock);
43LIST_HEAD(hose_list);
44
45
46static int global_phb_number;
47
48
49resource_size_t isa_mem_base;
50
51unsigned long isa_io_base;
52EXPORT_SYMBOL(isa_io_base);
53
54static int pci_bus_count;
55
56struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
57{
58 struct pci_controller *phb;
59
60 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
61 if (!phb)
62 return NULL;
63 spin_lock(&hose_spinlock);
64 phb->global_number = global_phb_number++;
65 list_add_tail(&phb->list_node, &hose_list);
66 spin_unlock(&hose_spinlock);
67 phb->dn = dev;
68 phb->is_dynamic = mem_init_done;
69 return phb;
70}
71
72void pcibios_free_controller(struct pci_controller *phb)
73{
74 spin_lock(&hose_spinlock);
75 list_del(&phb->list_node);
76 spin_unlock(&hose_spinlock);
77
78 if (phb->is_dynamic)
79 kfree(phb);
80}
81
82static resource_size_t pcibios_io_size(const struct pci_controller *hose)
83{
84 return resource_size(&hose->io_resource);
85}
86
87int pcibios_vaddr_is_ioport(void __iomem *address)
88{
89 int ret = 0;
90 struct pci_controller *hose;
91 resource_size_t size;
92
93 spin_lock(&hose_spinlock);
94 list_for_each_entry(hose, &hose_list, list_node) {
95 size = pcibios_io_size(hose);
96 if (address >= hose->io_base_virt &&
97 address < (hose->io_base_virt + size)) {
98 ret = 1;
99 break;
100 }
101 }
102 spin_unlock(&hose_spinlock);
103 return ret;
104}
105
106unsigned long pci_address_to_pio(phys_addr_t address)
107{
108 struct pci_controller *hose;
109 resource_size_t size;
110 unsigned long ret = ~0;
111
112 spin_lock(&hose_spinlock);
113 list_for_each_entry(hose, &hose_list, list_node) {
114 size = pcibios_io_size(hose);
115 if (address >= hose->io_base_phys &&
116 address < (hose->io_base_phys + size)) {
117 unsigned long base =
118 (unsigned long)hose->io_base_virt - _IO_BASE;
119 ret = base + (address - hose->io_base_phys);
120 break;
121 }
122 }
123 spin_unlock(&hose_spinlock);
124
125 return ret;
126}
127EXPORT_SYMBOL_GPL(pci_address_to_pio);
128
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135
136struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
137{
138 while (node) {
139 struct pci_controller *hose, *tmp;
140 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
141 if (hose->dn == node)
142 return hose;
143 node = node->parent;
144 }
145 return NULL;
146}
147
148void pcibios_set_master(struct pci_dev *dev)
149{
150
151}
152
153
154
155
156
157int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
158{
159 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
160 resource_size_t ioaddr = pci_resource_start(pdev, bar);
161
162 if (!hose)
163 return -EINVAL;
164
165
166 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
167
168 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
169 return 0;
170}
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176
177pgprot_t pci_phys_mem_access_prot(struct file *file,
178 unsigned long pfn,
179 unsigned long size,
180 pgprot_t prot)
181{
182 struct pci_dev *pdev = NULL;
183 struct resource *found = NULL;
184 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
185 int i;
186
187 if (page_is_ram(pfn))
188 return prot;
189
190 prot = pgprot_noncached(prot);
191 for_each_pci_dev(pdev) {
192 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
193 struct resource *rp = &pdev->resource[i];
194 int flags = rp->flags;
195
196
197 if ((flags & IORESOURCE_MEM) == 0)
198 continue;
199
200 if (offset < (rp->start & PAGE_MASK) ||
201 offset > rp->end)
202 continue;
203 found = rp;
204 break;
205 }
206 if (found)
207 break;
208 }
209 if (found) {
210 if (found->flags & IORESOURCE_PREFETCH)
211 prot = pgprot_noncached_wc(prot);
212 pci_dev_put(pdev);
213 }
214
215 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
216 (unsigned long long)offset, pgprot_val(prot));
217
218 return prot;
219}
220
221
222int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
223{
224 unsigned long offset;
225 struct pci_controller *hose = pci_bus_to_host(bus);
226 struct resource *rp = &hose->io_resource;
227 void __iomem *addr;
228
229
230
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232
233
234 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
235 offset += port;
236
237 if (!(rp->flags & IORESOURCE_IO))
238 return -ENXIO;
239 if (offset < rp->start || (offset + size) > rp->end)
240 return -ENXIO;
241 addr = hose->io_base_virt + port;
242
243 switch (size) {
244 case 1:
245 *((u8 *)val) = in_8(addr);
246 return 1;
247 case 2:
248 if (port & 1)
249 return -EINVAL;
250 *((u16 *)val) = in_le16(addr);
251 return 2;
252 case 4:
253 if (port & 3)
254 return -EINVAL;
255 *((u32 *)val) = in_le32(addr);
256 return 4;
257 }
258 return -EINVAL;
259}
260
261
262int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
263{
264 unsigned long offset;
265 struct pci_controller *hose = pci_bus_to_host(bus);
266 struct resource *rp = &hose->io_resource;
267 void __iomem *addr;
268
269
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271
272
273
274 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
275 offset += port;
276
277 if (!(rp->flags & IORESOURCE_IO))
278 return -ENXIO;
279 if (offset < rp->start || (offset + size) > rp->end)
280 return -ENXIO;
281 addr = hose->io_base_virt + port;
282
283
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286
287
288 switch (size) {
289 case 1:
290 out_8(addr, val >> 24);
291 return 1;
292 case 2:
293 if (port & 1)
294 return -EINVAL;
295 out_le16(addr, val >> 16);
296 return 2;
297 case 4:
298 if (port & 3)
299 return -EINVAL;
300 out_le32(addr, val);
301 return 4;
302 }
303 return -EINVAL;
304}
305
306
307int pci_mmap_legacy_page_range(struct pci_bus *bus,
308 struct vm_area_struct *vma,
309 enum pci_mmap_state mmap_state)
310{
311 struct pci_controller *hose = pci_bus_to_host(bus);
312 resource_size_t offset =
313 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
314 resource_size_t size = vma->vm_end - vma->vm_start;
315 struct resource *rp;
316
317 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
318 pci_domain_nr(bus), bus->number,
319 mmap_state == pci_mmap_mem ? "MEM" : "IO",
320 (unsigned long long)offset,
321 (unsigned long long)(offset + size - 1));
322
323 if (mmap_state == pci_mmap_mem) {
324
325
326
327
328
329
330
331 if ((offset + size) > hose->isa_mem_size) {
332#ifdef CONFIG_MMU
333 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
334 current->comm, current->pid);
335 pr_debug("legacy memory for 0%04x:%02x\n",
336 pci_domain_nr(bus), bus->number);
337#endif
338 if (vma->vm_flags & VM_SHARED)
339 return shmem_zero_setup(vma);
340 return 0;
341 }
342 offset += hose->isa_mem_phys;
343 } else {
344 unsigned long io_offset = (unsigned long)hose->io_base_virt -
345 _IO_BASE;
346 unsigned long roffset = offset + io_offset;
347 rp = &hose->io_resource;
348 if (!(rp->flags & IORESOURCE_IO))
349 return -ENXIO;
350 if (roffset < rp->start || (roffset + size) > rp->end)
351 return -ENXIO;
352 offset += hose->io_base_phys;
353 }
354 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
355
356 vma->vm_pgoff = offset >> PAGE_SHIFT;
357 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
358 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
359 vma->vm_end - vma->vm_start,
360 vma->vm_page_prot);
361}
362
363void pci_resource_to_user(const struct pci_dev *dev, int bar,
364 const struct resource *rsrc,
365 resource_size_t *start, resource_size_t *end)
366{
367 struct pci_bus_region region;
368
369 if (rsrc->flags & IORESOURCE_IO) {
370 pcibios_resource_to_bus(dev->bus, ®ion,
371 (struct resource *) rsrc);
372 *start = region.start;
373 *end = region.end;
374 return;
375 }
376
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380
381
382
383
384 *start = rsrc->start;
385 *end = rsrc->end;
386}
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420
421void pci_process_bridge_OF_ranges(struct pci_controller *hose,
422 struct device_node *dev, int primary)
423{
424 int memno = 0, isa_hole = -1;
425 unsigned long long isa_mb = 0;
426 struct resource *res;
427 struct of_pci_range range;
428 struct of_pci_range_parser parser;
429
430 pr_info("PCI host bridge %pOF %s ranges:\n",
431 dev, primary ? "(primary)" : "");
432
433
434 if (of_pci_range_parser_init(&parser, dev))
435 return;
436
437 pr_debug("Parsing ranges property...\n");
438 for_each_of_pci_range(&parser, &range) {
439
440 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
441 range.pci_space, range.pci_addr);
442 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
443 range.cpu_addr, range.size);
444
445
446
447
448
449
450 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
451 continue;
452
453
454 res = NULL;
455 switch (range.flags & IORESOURCE_TYPE_BITS) {
456 case IORESOURCE_IO:
457 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
458 range.cpu_addr, range.cpu_addr + range.size - 1,
459 range.pci_addr);
460
461
462 if (hose->pci_io_size) {
463 pr_info(" \\--> Skipped (too many) !\n");
464 continue;
465 }
466
467 if (range.size > 0x01000000)
468 range.size = 0x01000000;
469
470
471 hose->io_base_virt = ioremap(range.cpu_addr,
472 range.size);
473
474
475 if (primary)
476 isa_io_base =
477 (unsigned long)hose->io_base_virt;
478
479
480
481 hose->pci_io_size = range.pci_addr + range.size;
482 hose->io_base_phys = range.cpu_addr - range.pci_addr;
483
484
485 res = &hose->io_resource;
486 range.cpu_addr = range.pci_addr;
487
488 break;
489 case IORESOURCE_MEM:
490 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
491 range.cpu_addr, range.cpu_addr + range.size - 1,
492 range.pci_addr,
493 (range.pci_space & 0x40000000) ?
494 "Prefetch" : "");
495
496
497 if (memno >= 3) {
498 pr_info(" \\--> Skipped (too many) !\n");
499 continue;
500 }
501
502 if (range.pci_addr == 0) {
503 isa_mb = range.cpu_addr;
504 isa_hole = memno;
505 if (primary || isa_mem_base == 0)
506 isa_mem_base = range.cpu_addr;
507 hose->isa_mem_phys = range.cpu_addr;
508 hose->isa_mem_size = range.size;
509 }
510
511
512
513
514
515 if (memno == 0 ||
516 (isa_hole >= 0 && range.pci_addr != 0 &&
517 hose->pci_mem_offset == isa_mb))
518 hose->pci_mem_offset = range.cpu_addr -
519 range.pci_addr;
520 else if (range.pci_addr != 0 &&
521 hose->pci_mem_offset != range.cpu_addr -
522 range.pci_addr) {
523 pr_info(" \\--> Skipped (offset mismatch) !\n");
524 continue;
525 }
526
527
528 res = &hose->mem_resources[memno++];
529 break;
530 }
531 if (res != NULL) {
532 res->name = dev->full_name;
533 res->flags = range.flags;
534 res->start = range.cpu_addr;
535 res->end = range.cpu_addr + range.size - 1;
536 res->parent = res->child = res->sibling = NULL;
537 }
538 }
539
540
541
542
543
544 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
545 unsigned int next = isa_hole + 1;
546 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
547 if (next < memno)
548 memmove(&hose->mem_resources[isa_hole],
549 &hose->mem_resources[next],
550 sizeof(struct resource) * (memno - next));
551 hose->mem_resources[--memno].flags = 0;
552 }
553}
554
555
556int pci_proc_domain(struct pci_bus *bus)
557{
558 return pci_domain_nr(bus);
559}
560
561
562
563
564static void pcibios_fixup_resources(struct pci_dev *dev)
565{
566 struct pci_controller *hose = pci_bus_to_host(dev->bus);
567 int i;
568
569 if (!hose) {
570 pr_err("No host bridge for PCI dev %s !\n",
571 pci_name(dev));
572 return;
573 }
574 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
575 struct resource *res = dev->resource + i;
576 if (!res->flags)
577 continue;
578 if (res->start == 0) {
579 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]",
580 pci_name(dev), i,
581 (unsigned long long)res->start,
582 (unsigned long long)res->end,
583 (unsigned int)res->flags);
584 pr_debug("is unassigned\n");
585 res->end -= res->start;
586 res->start = 0;
587 res->flags |= IORESOURCE_UNSET;
588 continue;
589 }
590
591 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
592 pci_name(dev), i,
593 (unsigned long long)res->start,
594 (unsigned long long)res->end,
595 (unsigned int)res->flags);
596 }
597}
598DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
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613int pcibios_add_device(struct pci_dev *dev)
614{
615 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
616
617 return 0;
618}
619EXPORT_SYMBOL(pcibios_add_device);
620
621
622
623
624
625static int __init reparent_resources(struct resource *parent,
626 struct resource *res)
627{
628 struct resource *p, **pp;
629 struct resource **firstpp = NULL;
630
631 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
632 if (p->end < res->start)
633 continue;
634 if (res->end < p->start)
635 break;
636 if (p->start < res->start || p->end > res->end)
637 return -1;
638 if (firstpp == NULL)
639 firstpp = pp;
640 }
641 if (firstpp == NULL)
642 return -1;
643 res->parent = parent;
644 res->child = *firstpp;
645 res->sibling = *pp;
646 *firstpp = res;
647 *pp = NULL;
648 for (p = res->child; p != NULL; p = p->sibling) {
649 p->parent = res;
650 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
651 p->name,
652 (unsigned long long)p->start,
653 (unsigned long long)p->end, res->name);
654 }
655 return 0;
656}
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691static void pcibios_allocate_bus_resources(struct pci_bus *bus)
692{
693 struct pci_bus *b;
694 int i;
695 struct resource *res, *pr;
696
697 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
698 pci_domain_nr(bus), bus->number);
699
700 pci_bus_for_each_resource(bus, res, i) {
701 if (!res || !res->flags
702 || res->start > res->end || res->parent)
703 continue;
704 if (bus->parent == NULL)
705 pr = (res->flags & IORESOURCE_IO) ?
706 &ioport_resource : &iomem_resource;
707 else {
708
709
710
711
712
713
714 pr = pci_find_parent_resource(bus->self, res);
715 if (pr == res) {
716
717
718
719
720 continue;
721 }
722 }
723
724 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
725 bus->self ? pci_name(bus->self) : "PHB",
726 bus->number, i,
727 (unsigned long long)res->start,
728 (unsigned long long)res->end);
729 pr_debug("[0x%x], parent %p (%s)\n",
730 (unsigned int)res->flags,
731 pr, (pr && pr->name) ? pr->name : "nil");
732
733 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
734 struct pci_dev *dev = bus->self;
735
736 if (request_resource(pr, res) == 0)
737 continue;
738
739
740
741
742
743 if (reparent_resources(pr, res) == 0)
744 continue;
745
746 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
747 pci_claim_bridge_resource(dev,
748 i + PCI_BRIDGE_RESOURCES) == 0)
749 continue;
750
751 }
752 pr_warn("PCI: Cannot allocate resource region ");
753 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
754 res->start = res->end = 0;
755 res->flags = 0;
756 }
757
758 list_for_each_entry(b, &bus->children, node)
759 pcibios_allocate_bus_resources(b);
760}
761
762static inline void alloc_resource(struct pci_dev *dev, int idx)
763{
764 struct resource *pr, *r = &dev->resource[idx];
765
766 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
767 pci_name(dev), idx,
768 (unsigned long long)r->start,
769 (unsigned long long)r->end,
770 (unsigned int)r->flags);
771
772 pr = pci_find_parent_resource(dev, r);
773 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
774 request_resource(pr, r) < 0) {
775 pr_warn("PCI: Cannot allocate resource region %d ", idx);
776 pr_cont("of device %s, will remap\n", pci_name(dev));
777 if (pr)
778 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
779 pr,
780 (unsigned long long)pr->start,
781 (unsigned long long)pr->end,
782 (unsigned int)pr->flags);
783
784 r->flags |= IORESOURCE_UNSET;
785 r->end -= r->start;
786 r->start = 0;
787 }
788}
789
790static void __init pcibios_allocate_resources(int pass)
791{
792 struct pci_dev *dev = NULL;
793 int idx, disabled;
794 u16 command;
795 struct resource *r;
796
797 for_each_pci_dev(dev) {
798 pci_read_config_word(dev, PCI_COMMAND, &command);
799 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
800 r = &dev->resource[idx];
801 if (r->parent)
802 continue;
803 if (!r->flags || (r->flags & IORESOURCE_UNSET))
804 continue;
805
806
807
808 if (idx == PCI_ROM_RESOURCE)
809 disabled = 1;
810 if (r->flags & IORESOURCE_IO)
811 disabled = !(command & PCI_COMMAND_IO);
812 else
813 disabled = !(command & PCI_COMMAND_MEMORY);
814 if (pass == disabled)
815 alloc_resource(dev, idx);
816 }
817 if (pass)
818 continue;
819 r = &dev->resource[PCI_ROM_RESOURCE];
820 if (r->flags) {
821
822
823
824 u32 reg;
825 pci_read_config_dword(dev, dev->rom_base_reg, ®);
826 if (reg & PCI_ROM_ADDRESS_ENABLE) {
827 pr_debug("PCI: Switching off ROM of %s\n",
828 pci_name(dev));
829 r->flags &= ~IORESOURCE_ROM_ENABLE;
830 pci_write_config_dword(dev, dev->rom_base_reg,
831 reg & ~PCI_ROM_ADDRESS_ENABLE);
832 }
833 }
834 }
835}
836
837static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
838{
839 struct pci_controller *hose = pci_bus_to_host(bus);
840 resource_size_t offset;
841 struct resource *res, *pres;
842 int i;
843
844 pr_debug("Reserving legacy ranges for domain %04x\n",
845 pci_domain_nr(bus));
846
847
848 if (!(hose->io_resource.flags & IORESOURCE_IO))
849 goto no_io;
850 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
851 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
852 BUG_ON(res == NULL);
853 res->name = "Legacy IO";
854 res->flags = IORESOURCE_IO;
855 res->start = offset;
856 res->end = (offset + 0xfff) & 0xfffffffful;
857 pr_debug("Candidate legacy IO: %pR\n", res);
858 if (request_resource(&hose->io_resource, res)) {
859 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
860 pci_domain_nr(bus), bus->number, res);
861 kfree(res);
862 }
863
864 no_io:
865
866 offset = hose->pci_mem_offset;
867 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
868 for (i = 0; i < 3; i++) {
869 pres = &hose->mem_resources[i];
870 if (!(pres->flags & IORESOURCE_MEM))
871 continue;
872 pr_debug("hose mem res: %pR\n", pres);
873 if ((pres->start - offset) <= 0xa0000 &&
874 (pres->end - offset) >= 0xbffff)
875 break;
876 }
877 if (i >= 3)
878 return;
879 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
880 BUG_ON(res == NULL);
881 res->name = "Legacy VGA memory";
882 res->flags = IORESOURCE_MEM;
883 res->start = 0xa0000 + offset;
884 res->end = 0xbffff + offset;
885 pr_debug("Candidate VGA memory: %pR\n", res);
886 if (request_resource(pres, res)) {
887 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
888 pci_domain_nr(bus), bus->number, res);
889 kfree(res);
890 }
891}
892
893void __init pcibios_resource_survey(void)
894{
895 struct pci_bus *b;
896
897
898
899
900 list_for_each_entry(b, &pci_root_buses, node)
901 pcibios_allocate_bus_resources(b);
902
903 pcibios_allocate_resources(0);
904 pcibios_allocate_resources(1);
905
906
907
908
909
910 list_for_each_entry(b, &pci_root_buses, node)
911 pcibios_reserve_legacy_regions(b);
912
913
914 pr_debug("PCI: Assigning unassigned resources...\n");
915 pci_assign_unassigned_resources();
916}
917
918
919
920
921
922
923void pcibios_claim_one_bus(struct pci_bus *bus)
924{
925 struct pci_dev *dev;
926 struct pci_bus *child_bus;
927
928 list_for_each_entry(dev, &bus->devices, bus_list) {
929 int i;
930
931 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
932 struct resource *r = &dev->resource[i];
933
934 if (r->parent || !r->start || !r->flags)
935 continue;
936
937 pr_debug("PCI: Claiming %s: ", pci_name(dev));
938 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
939 i, (unsigned long long)r->start,
940 (unsigned long long)r->end,
941 (unsigned int)r->flags);
942
943 if (pci_claim_resource(dev, i) == 0)
944 continue;
945
946 pci_claim_bridge_resource(dev, i);
947 }
948 }
949
950 list_for_each_entry(child_bus, &bus->children, node)
951 pcibios_claim_one_bus(child_bus);
952}
953EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
954
955
956
957
958
959
960
961
962void pcibios_finish_adding_to_bus(struct pci_bus *bus)
963{
964 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
965 pci_domain_nr(bus), bus->number);
966
967
968 pcibios_allocate_bus_resources(bus);
969 pcibios_claim_one_bus(bus);
970
971
972 pci_bus_add_devices(bus);
973
974
975
976}
977EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
978
979static void pcibios_setup_phb_resources(struct pci_controller *hose,
980 struct list_head *resources)
981{
982 unsigned long io_offset;
983 struct resource *res;
984 int i;
985
986
987 res = &hose->io_resource;
988
989
990 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
991 res->start = (res->start + io_offset) & 0xffffffffu;
992 res->end = (res->end + io_offset) & 0xffffffffu;
993
994 if (!res->flags) {
995 pr_warn("PCI: I/O resource not set for host ");
996 pr_cont("bridge %pOF (domain %d)\n",
997 hose->dn, hose->global_number);
998
999 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1000 res->end = res->start + IO_SPACE_LIMIT;
1001 res->flags = IORESOURCE_IO;
1002 }
1003 pci_add_resource_offset(resources, res,
1004 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1005
1006 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1007 (unsigned long long)res->start,
1008 (unsigned long long)res->end,
1009 (unsigned long)res->flags);
1010
1011
1012 for (i = 0; i < 3; ++i) {
1013 res = &hose->mem_resources[i];
1014 if (!res->flags) {
1015 if (i > 0)
1016 continue;
1017 pr_err("PCI: Memory resource 0 not set for ");
1018 pr_cont("host bridge %pOF (domain %d)\n",
1019 hose->dn, hose->global_number);
1020
1021
1022 res->start = hose->pci_mem_offset;
1023 res->end = (resource_size_t)-1LL;
1024 res->flags = IORESOURCE_MEM;
1025
1026 }
1027 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1028
1029 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1030 i, (unsigned long long)res->start,
1031 (unsigned long long)res->end,
1032 (unsigned long)res->flags);
1033 }
1034
1035 pr_debug("PCI: PHB MEM offset = %016llx\n",
1036 (unsigned long long)hose->pci_mem_offset);
1037 pr_debug("PCI: PHB IO offset = %08lx\n",
1038 (unsigned long)hose->io_base_virt - _IO_BASE);
1039}
1040
1041static void pcibios_scan_phb(struct pci_controller *hose)
1042{
1043 LIST_HEAD(resources);
1044 struct pci_bus *bus;
1045 struct device_node *node = hose->dn;
1046
1047 pr_debug("PCI: Scanning PHB %pOF\n", node);
1048
1049 pcibios_setup_phb_resources(hose, &resources);
1050
1051 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1052 hose->ops, hose, &resources);
1053 if (bus == NULL) {
1054 pr_err("Failed to create bus for PCI domain %04x\n",
1055 hose->global_number);
1056 pci_free_resource_list(&resources);
1057 return;
1058 }
1059 bus->busn_res.start = hose->first_busno;
1060 hose->bus = bus;
1061
1062 hose->last_busno = bus->busn_res.end;
1063}
1064
1065static int __init pcibios_init(void)
1066{
1067 struct pci_controller *hose, *tmp;
1068 int next_busno = 0;
1069
1070 pr_info("PCI: Probing PCI hardware\n");
1071
1072
1073 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1074 hose->last_busno = 0xff;
1075 pcibios_scan_phb(hose);
1076 if (next_busno <= hose->last_busno)
1077 next_busno = hose->last_busno + 1;
1078 }
1079 pci_bus_count = next_busno;
1080
1081
1082 pcibios_resource_survey();
1083 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1084 if (hose->bus)
1085 pci_bus_add_devices(hose->bus);
1086 }
1087
1088 return 0;
1089}
1090
1091subsys_initcall(pcibios_init);
1092
1093static struct pci_controller *pci_bus_to_hose(int bus)
1094{
1095 struct pci_controller *hose, *tmp;
1096
1097 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1098 if (bus >= hose->first_busno && bus <= hose->last_busno)
1099 return hose;
1100 return NULL;
1101}
1102
1103
1104
1105
1106
1107
1108
1109long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1110{
1111 struct pci_controller *hose;
1112 long result = -EOPNOTSUPP;
1113
1114 hose = pci_bus_to_hose(bus);
1115 if (!hose)
1116 return -ENODEV;
1117
1118 switch (which) {
1119 case IOBASE_BRIDGE_NUMBER:
1120 return (long)hose->first_busno;
1121 case IOBASE_MEMORY:
1122 return (long)hose->pci_mem_offset;
1123 case IOBASE_IO:
1124 return (long)hose->io_base_phys;
1125 case IOBASE_ISA_IO:
1126 return (long)isa_io_base;
1127 case IOBASE_ISA_MEM:
1128 return (long)isa_mem_base;
1129 }
1130
1131 return result;
1132}
1133
1134
1135
1136
1137
1138#define NULL_PCI_OP(rw, size, type) \
1139static int \
1140null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1141{ \
1142 return PCIBIOS_DEVICE_NOT_FOUND; \
1143}
1144
1145static int
1146null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1147 int len, u32 *val)
1148{
1149 return PCIBIOS_DEVICE_NOT_FOUND;
1150}
1151
1152static int
1153null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1154 int len, u32 val)
1155{
1156 return PCIBIOS_DEVICE_NOT_FOUND;
1157}
1158
1159static struct pci_ops null_pci_ops = {
1160 .read = null_read_config,
1161 .write = null_write_config,
1162};
1163
1164
1165
1166
1167
1168static struct pci_bus *
1169fake_pci_bus(struct pci_controller *hose, int busnr)
1170{
1171 static struct pci_bus bus;
1172
1173 if (!hose)
1174 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1175
1176 bus.number = busnr;
1177 bus.sysdata = hose;
1178 bus.ops = hose ? hose->ops : &null_pci_ops;
1179 return &bus;
1180}
1181
1182#define EARLY_PCI_OP(rw, size, type) \
1183int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1184 int devfn, int offset, type value) \
1185{ \
1186 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1187 devfn, offset, value); \
1188}
1189
1190EARLY_PCI_OP(read, byte, u8 *)
1191EARLY_PCI_OP(read, word, u16 *)
1192EARLY_PCI_OP(read, dword, u32 *)
1193EARLY_PCI_OP(write, byte, u8)
1194EARLY_PCI_OP(write, word, u16)
1195EARLY_PCI_OP(write, dword, u32)
1196
1197int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1198 int cap)
1199{
1200 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1201}
1202
1203