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10#include <linux/compiler.h>
11#include <linux/vmalloc.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/console.h>
15#include <linux/delay.h>
16#include <linux/export.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/serial.h>
20#include <linux/smp.h>
21#include <linux/types.h>
22#include <linux/string.h>
23#include <linux/tty.h>
24#include <linux/time.h>
25#include <linux/platform_device.h>
26#include <linux/serial_core.h>
27#include <linux/serial_8250.h>
28#include <linux/of_fdt.h>
29#include <linux/libfdt.h>
30#include <linux/kexec.h>
31
32#include <asm/processor.h>
33#include <asm/reboot.h>
34#include <asm/smp-ops.h>
35#include <asm/irq_cpu.h>
36#include <asm/mipsregs.h>
37#include <asm/bootinfo.h>
38#include <asm/sections.h>
39#include <asm/time.h>
40
41#include <asm/octeon/octeon.h>
42#include <asm/octeon/pci-octeon.h>
43#include <asm/octeon/cvmx-rst-defs.h>
44
45
46
47
48
49
50
51const bool octeon_should_swizzle_table[256] = {
52 [0x00] = true,
53 [0x1b] = true,
54 [0x1c] = true,
55 [0x1d] = true,
56 [0x1e] = true,
57 [0x68] = true,
58 [0x69] = true,
59 [0x6c] = true,
60 [0x6f] = true,
61};
62EXPORT_SYMBOL(octeon_should_swizzle_table);
63
64#ifdef CONFIG_PCI
65extern void pci_console_init(const char *arg);
66#endif
67
68static unsigned long long max_memory = ULLONG_MAX;
69static unsigned long long reserve_low_mem;
70
71DEFINE_SEMAPHORE(octeon_bootbus_sem);
72EXPORT_SYMBOL(octeon_bootbus_sem);
73
74struct octeon_boot_descriptor *octeon_boot_desc_ptr;
75
76struct cvmx_bootinfo *octeon_bootinfo;
77EXPORT_SYMBOL(octeon_bootinfo);
78
79#ifdef CONFIG_KEXEC
80#ifdef CONFIG_SMP
81
82
83
84
85static void octeon_kexec_smp_down(void *ignored)
86{
87 int cpu = smp_processor_id();
88
89 local_irq_disable();
90 set_cpu_online(cpu, false);
91 while (!atomic_read(&kexec_ready_to_reboot))
92 cpu_relax();
93
94 asm volatile (
95 " sync \n"
96 " synci ($0) \n");
97
98 relocated_kexec_smp_wait(NULL);
99}
100#endif
101
102#define OCTEON_DDR0_BASE (0x0ULL)
103#define OCTEON_DDR0_SIZE (0x010000000ULL)
104#define OCTEON_DDR1_BASE (0x410000000ULL)
105#define OCTEON_DDR1_SIZE (0x010000000ULL)
106#define OCTEON_DDR2_BASE (0x020000000ULL)
107#define OCTEON_DDR2_SIZE (0x3e0000000ULL)
108#define OCTEON_MAX_PHY_MEM_SIZE (16*1024*1024*1024ULL)
109
110static struct kimage *kimage_ptr;
111
112static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
113{
114 int64_t addr;
115 struct cvmx_bootmem_desc *bootmem_desc;
116
117 bootmem_desc = cvmx_bootmem_get_desc();
118
119 if (mem_size > OCTEON_MAX_PHY_MEM_SIZE) {
120 mem_size = OCTEON_MAX_PHY_MEM_SIZE;
121 pr_err("Error: requested memory too large,"
122 "truncating to maximum size\n");
123 }
124
125 bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
126 bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
127
128 addr = (OCTEON_DDR0_BASE + reserve_low_mem + low_reserved_bytes);
129 bootmem_desc->head_addr = 0;
130
131 if (mem_size <= OCTEON_DDR0_SIZE) {
132 __cvmx_bootmem_phy_free(addr,
133 mem_size - reserve_low_mem -
134 low_reserved_bytes, 0);
135 return;
136 }
137
138 __cvmx_bootmem_phy_free(addr,
139 OCTEON_DDR0_SIZE - reserve_low_mem -
140 low_reserved_bytes, 0);
141
142 mem_size -= OCTEON_DDR0_SIZE;
143
144 if (mem_size > OCTEON_DDR1_SIZE) {
145 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, OCTEON_DDR1_SIZE, 0);
146 __cvmx_bootmem_phy_free(OCTEON_DDR2_BASE,
147 mem_size - OCTEON_DDR1_SIZE, 0);
148 } else
149 __cvmx_bootmem_phy_free(OCTEON_DDR1_BASE, mem_size, 0);
150}
151
152static int octeon_kexec_prepare(struct kimage *image)
153{
154 int i;
155 char *bootloader = "kexec";
156
157 octeon_boot_desc_ptr->argc = 0;
158 for (i = 0; i < image->nr_segments; i++) {
159 if (!strncmp(bootloader, (char *)image->segment[i].buf,
160 strlen(bootloader))) {
161
162
163
164
165 int argc = 0, offt;
166 char *str = (char *)image->segment[i].buf;
167 char *ptr = strchr(str, ' ');
168 while (ptr && (OCTEON_ARGV_MAX_ARGS > argc)) {
169 *ptr = '\0';
170 if (ptr[1] != ' ') {
171 offt = (int)(ptr - str + 1);
172 octeon_boot_desc_ptr->argv[argc] =
173 image->segment[i].mem + offt;
174 argc++;
175 }
176 ptr = strchr(ptr + 1, ' ');
177 }
178 octeon_boot_desc_ptr->argc = argc;
179 break;
180 }
181 }
182
183
184
185
186
187 kimage_ptr = image;
188 return 0;
189}
190
191static void octeon_generic_shutdown(void)
192{
193 int i;
194#ifdef CONFIG_SMP
195 int cpu;
196#endif
197 struct cvmx_bootmem_desc *bootmem_desc;
198 void *named_block_array_ptr;
199
200 bootmem_desc = cvmx_bootmem_get_desc();
201 named_block_array_ptr =
202 cvmx_phys_to_ptr(bootmem_desc->named_block_array_addr);
203
204#ifdef CONFIG_SMP
205
206 for_each_online_cpu(cpu)
207 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
208#else
209 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
210#endif
211 if (kimage_ptr != kexec_crash_image) {
212 memset(named_block_array_ptr,
213 0x0,
214 CVMX_BOOTMEM_NUM_NAMED_BLOCKS *
215 sizeof(struct cvmx_bootmem_named_block_desc));
216
217
218
219
220 kexec_bootmem_init(octeon_bootinfo->dram_size*1024ULL*1024ULL,
221 0x100000);
222
223
224
225 for (i = 0; i < kimage_ptr->nr_segments; i++)
226 cvmx_bootmem_alloc_address(
227 kimage_ptr->segment[i].memsz + 2*PAGE_SIZE,
228 kimage_ptr->segment[i].mem - PAGE_SIZE,
229 PAGE_SIZE);
230 } else {
231
232
233
234
235 struct cvmx_bootmem_named_block_desc *ptr =
236 (struct cvmx_bootmem_named_block_desc *)
237 named_block_array_ptr;
238
239 for (i = 0; i < bootmem_desc->named_block_num_blocks; i++)
240 if (ptr[i].size)
241 cvmx_bootmem_free_named(ptr[i].name);
242 }
243 kexec_args[2] = 1UL;
244 kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
245#ifdef CONFIG_SMP
246 secondary_kexec_args[2] = 0UL;
247 secondary_kexec_args[3] = (unsigned long)octeon_boot_desc_ptr;
248#endif
249}
250
251static void octeon_shutdown(void)
252{
253 octeon_generic_shutdown();
254#ifdef CONFIG_SMP
255 smp_call_function(octeon_kexec_smp_down, NULL, 0);
256 smp_wmb();
257 while (num_online_cpus() > 1) {
258 cpu_relax();
259 mdelay(1);
260 }
261#endif
262}
263
264static void octeon_crash_shutdown(struct pt_regs *regs)
265{
266 octeon_generic_shutdown();
267 default_machine_crash_shutdown(regs);
268}
269
270#ifdef CONFIG_SMP
271void octeon_crash_smp_send_stop(void)
272{
273 int cpu;
274
275
276 for_each_online_cpu(cpu)
277 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
278}
279#endif
280
281#endif
282
283#ifdef CONFIG_CAVIUM_RESERVE32
284uint64_t octeon_reserve32_memory;
285EXPORT_SYMBOL(octeon_reserve32_memory);
286#endif
287
288#ifdef CONFIG_KEXEC
289
290
291static uint64_t crashk_size, crashk_base;
292#endif
293
294static int octeon_uart;
295
296extern asmlinkage void handle_int(void);
297
298
299
300
301
302
303int octeon_is_simulation(void)
304{
305 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
306}
307EXPORT_SYMBOL(octeon_is_simulation);
308
309
310
311
312
313
314
315int octeon_is_pci_host(void)
316{
317#ifdef CONFIG_PCI
318 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
319#else
320 return 0;
321#endif
322}
323
324
325
326
327
328
329uint64_t octeon_get_clock_rate(void)
330{
331 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
332
333 return sysinfo->cpu_clock_hz;
334}
335EXPORT_SYMBOL(octeon_get_clock_rate);
336
337static u64 octeon_io_clock_rate;
338
339u64 octeon_get_io_clock_rate(void)
340{
341 return octeon_io_clock_rate;
342}
343EXPORT_SYMBOL(octeon_get_io_clock_rate);
344
345
346
347
348
349
350
351
352
353void octeon_write_lcd(const char *s)
354{
355 if (octeon_bootinfo->led_display_base_addr) {
356 void __iomem *lcd_address =
357 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
358 8);
359 int i;
360 for (i = 0; i < 8; i++, s++) {
361 if (*s)
362 iowrite8(*s, lcd_address + i);
363 else
364 iowrite8(' ', lcd_address + i);
365 }
366 iounmap(lcd_address);
367 }
368}
369
370
371
372
373
374
375int octeon_get_boot_uart(void)
376{
377 return (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
378 1 : 0;
379}
380
381
382
383
384
385
386int octeon_get_boot_coremask(void)
387{
388 return octeon_boot_desc_ptr->core_mask;
389}
390
391
392
393
394void octeon_check_cpu_bist(void)
395{
396 const int coreid = cvmx_get_core_num();
397 unsigned long long mask;
398 unsigned long long bist_val;
399
400
401 mask = 0x1f00000000ull;
402 bist_val = read_octeon_c0_icacheerr();
403 if (bist_val & mask)
404 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
405 coreid, bist_val);
406
407 bist_val = read_octeon_c0_dcacheerr();
408 if (bist_val & 1)
409 pr_err("Core%d L1 Dcache parity error: "
410 "CacheErr(dcache) = 0x%llx\n",
411 coreid, bist_val);
412
413 mask = 0xfc00000000000000ull;
414 bist_val = read_c0_cvmmemctl();
415 if (bist_val & mask)
416 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
417 coreid, bist_val);
418
419 write_octeon_c0_dcacheerr(0);
420}
421
422
423
424
425
426
427static void octeon_restart(char *command)
428{
429
430#ifdef CONFIG_SMP
431 int cpu;
432 for_each_online_cpu(cpu)
433 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
434#else
435 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
436#endif
437
438 mb();
439 while (1)
440 if (OCTEON_IS_OCTEON3())
441 cvmx_write_csr(CVMX_RST_SOFT_RST, 1);
442 else
443 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
444}
445
446
447
448
449
450
451
452static void octeon_kill_core(void *arg)
453{
454 if (octeon_is_simulation())
455
456 asm volatile ("break" ::: "memory");
457
458 local_irq_disable();
459
460 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
461
462 while (true)
463 asm volatile ("wait" ::: "memory");
464}
465
466
467
468
469
470static void octeon_halt(void)
471{
472 smp_call_function(octeon_kill_core, NULL, 0);
473
474 switch (octeon_bootinfo->board_type) {
475 case CVMX_BOARD_TYPE_NAO38:
476
477 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
478 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
479 break;
480 default:
481 octeon_write_lcd("PowerOff");
482 break;
483 }
484
485 octeon_kill_core(NULL);
486}
487
488static char __read_mostly octeon_system_type[80];
489
490static void __init init_octeon_system_type(void)
491{
492 char const *board_type;
493
494 board_type = cvmx_board_type_to_string(octeon_bootinfo->board_type);
495 if (board_type == NULL) {
496 struct device_node *root;
497 int ret;
498
499 root = of_find_node_by_path("/");
500 ret = of_property_read_string(root, "model", &board_type);
501 of_node_put(root);
502 if (ret)
503 board_type = "Unsupported Board";
504 }
505
506 snprintf(octeon_system_type, sizeof(octeon_system_type), "%s (%s)",
507 board_type, octeon_model_get_string(read_c0_prid()));
508}
509
510
511
512
513
514
515const char *octeon_board_type_string(void)
516{
517 return octeon_system_type;
518}
519
520const char *get_system_type(void)
521 __attribute__ ((alias("octeon_board_type_string")));
522
523void octeon_user_io_init(void)
524{
525 union octeon_cvmemctl cvmmemctl;
526
527
528 cvmmemctl.u64 = read_c0_cvmmemctl();
529
530
531
532 cvmmemctl.s.dismarkwblongto = 1;
533
534
535 cvmmemctl.s.dismrgclrwbto = 0;
536
537
538
539 cvmmemctl.s.iobdmascrmsb = 0;
540
541
542
543
544 cvmmemctl.s.syncwsmarked = 0;
545
546 cvmmemctl.s.dissyncws = 0;
547
548 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
549 cvmmemctl.s.diswbfst = 1;
550 else
551 cvmmemctl.s.diswbfst = 0;
552
553
554 cvmmemctl.s.xkmemenas = 0;
555
556
557
558 cvmmemctl.s.xkmemenau = 0;
559
560
561
562 cvmmemctl.s.xkioenas = 0;
563
564
565
566 cvmmemctl.s.xkioenau = 0;
567
568
569
570 cvmmemctl.s.allsyncw = 0;
571
572
573
574 cvmmemctl.s.nomerge = 0;
575
576
577
578
579 cvmmemctl.s.didtto = 0;
580
581 cvmmemctl.s.csrckalwys = 0;
582
583 cvmmemctl.s.mclkalwys = 0;
584
585
586
587
588
589
590 cvmmemctl.s.wbfltime = 0;
591
592 cvmmemctl.s.istrnol2 = 0;
593
594
595
596
597
598
599
600 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
601 cvmmemctl.s.wbthresh = 4;
602 else
603 cvmmemctl.s.wbthresh = 10;
604
605
606
607#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
608 cvmmemctl.s.cvmsegenak = 1;
609#else
610 cvmmemctl.s.cvmsegenak = 0;
611#endif
612
613
614 cvmmemctl.s.cvmsegenas = 0;
615
616
617 cvmmemctl.s.cvmsegenau = 0;
618
619 write_c0_cvmmemctl(cvmmemctl.u64);
620
621
622 if (smp_processor_id() == 0)
623 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
624 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
625 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
626
627 if (octeon_has_feature(OCTEON_FEATURE_FAU)) {
628 union cvmx_iob_fau_timeout fau_timeout;
629
630
631 fau_timeout.u64 = 0;
632 fau_timeout.s.tout_val = 0xfff;
633
634 fau_timeout.s.tout_enb = 0;
635 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
636 }
637
638 if ((!OCTEON_IS_MODEL(OCTEON_CN68XX) &&
639 !OCTEON_IS_MODEL(OCTEON_CN7XXX)) ||
640 OCTEON_IS_MODEL(OCTEON_CN70XX)) {
641 union cvmx_pow_nw_tim nm_tim;
642
643 nm_tim.u64 = 0;
644
645 nm_tim.s.nw_tim = 3;
646 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
647 }
648
649 write_octeon_c0_icacheerr(0);
650 write_c0_derraddr1(0);
651}
652
653
654
655
656void __init prom_init(void)
657{
658 struct cvmx_sysinfo *sysinfo;
659 const char *arg;
660 char *p;
661 int i;
662 u64 t;
663 int argc;
664#ifdef CONFIG_CAVIUM_RESERVE32
665 int64_t addr = -1;
666#endif
667
668
669
670
671 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
672 octeon_bootinfo =
673 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
674 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
675
676 sysinfo = cvmx_sysinfo_get();
677 memset(sysinfo, 0, sizeof(*sysinfo));
678 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
679 sysinfo->phy_mem_desc_addr = (u64)phys_to_virt(octeon_bootinfo->phy_mem_desc_addr);
680
681 if ((octeon_bootinfo->major_version > 1) ||
682 (octeon_bootinfo->major_version == 1 &&
683 octeon_bootinfo->minor_version >= 4))
684 cvmx_coremask_copy(&sysinfo->core_mask,
685 &octeon_bootinfo->ext_core_mask);
686 else
687 cvmx_coremask_set64(&sysinfo->core_mask,
688 octeon_bootinfo->core_mask);
689
690
691 if (!OCTEON_IS_MODEL(OCTEON_CN78XX))
692 for (i = 512; i < 1024; i++)
693 cvmx_coremask_clear_core(&sysinfo->core_mask, i);
694
695 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
696 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
697 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
698 sysinfo->board_type = octeon_bootinfo->board_type;
699 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
700 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
701 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
702 sizeof(sysinfo->mac_addr_base));
703 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
704 memcpy(sysinfo->board_serial_number,
705 octeon_bootinfo->board_serial_number,
706 sizeof(sysinfo->board_serial_number));
707 sysinfo->compact_flash_common_base_addr =
708 octeon_bootinfo->compact_flash_common_base_addr;
709 sysinfo->compact_flash_attribute_base_addr =
710 octeon_bootinfo->compact_flash_attribute_base_addr;
711 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
712 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
713 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
714
715 if (OCTEON_IS_OCTEON2()) {
716
717 union cvmx_mio_rst_boot rst_boot;
718 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
719 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
720 } else if (OCTEON_IS_OCTEON3()) {
721
722 union cvmx_rst_boot rst_boot;
723 rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
724 octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
725 } else {
726 octeon_io_clock_rate = sysinfo->cpu_clock_hz;
727 }
728
729 t = read_c0_cvmctl();
730 if ((t & (1ull << 27)) == 0) {
731
732
733
734
735 void *save;
736 void *save_end;
737 void *restore;
738 void *restore_end;
739 int save_len;
740 int restore_len;
741 int save_max = (char *)octeon_mult_save_end -
742 (char *)octeon_mult_save;
743 int restore_max = (char *)octeon_mult_restore_end -
744 (char *)octeon_mult_restore;
745 if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) {
746 save = octeon_mult_save3;
747 save_end = octeon_mult_save3_end;
748 restore = octeon_mult_restore3;
749 restore_end = octeon_mult_restore3_end;
750 } else {
751 save = octeon_mult_save2;
752 save_end = octeon_mult_save2_end;
753 restore = octeon_mult_restore2;
754 restore_end = octeon_mult_restore2_end;
755 }
756 save_len = (char *)save_end - (char *)save;
757 restore_len = (char *)restore_end - (char *)restore;
758 if (!WARN_ON(save_len > save_max ||
759 restore_len > restore_max)) {
760 memcpy(octeon_mult_save, save, save_len);
761 memcpy(octeon_mult_restore, restore, restore_len);
762 }
763 }
764
765
766
767
768
769 if (!octeon_is_simulation() &&
770 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
771 cvmx_write_csr(CVMX_LED_EN, 0);
772 cvmx_write_csr(CVMX_LED_PRT, 0);
773 cvmx_write_csr(CVMX_LED_DBG, 0);
774 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
775 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
776 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
777 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
778 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
779 cvmx_write_csr(CVMX_LED_EN, 1);
780 }
781#ifdef CONFIG_CAVIUM_RESERVE32
782
783
784
785
786
787
788
789
790
791
792 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
793 0, 0, 2 << 20,
794 "CAVIUM_RESERVE32", 0);
795 if (addr < 0)
796 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
797 else
798 octeon_reserve32_memory = addr;
799#endif
800
801#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
802 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
803 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
804 } else {
805 uint32_t __maybe_unused ebase = read_c0_ebase() & 0x3ffff000;
806#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
807
808 cvmx_l2c_lock_mem_region(ebase, 0x100);
809#endif
810#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
811
812 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
813#endif
814#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
815
816 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
817#endif
818#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
819 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
820 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
821#endif
822#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
823 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
824#endif
825 }
826#endif
827
828 octeon_check_cpu_bist();
829
830 octeon_uart = octeon_get_boot_uart();
831
832#ifdef CONFIG_SMP
833 octeon_write_lcd("LinuxSMP");
834#else
835 octeon_write_lcd("Linux");
836#endif
837
838 octeon_setup_delays();
839
840
841
842
843
844
845
846 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
847 OCTEON_IS_MODEL(OCTEON_CN31XX))
848 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
849 else
850 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
851
852
853 if (octeon_is_simulation())
854 max_memory = 64ull << 20;
855
856 arg = strstr(arcs_cmdline, "mem=");
857 if (arg) {
858 max_memory = memparse(arg + 4, &p);
859 if (max_memory == 0)
860 max_memory = 32ull << 30;
861 if (*p == '@')
862 reserve_low_mem = memparse(p + 1, &p);
863 }
864
865 arcs_cmdline[0] = 0;
866 argc = octeon_boot_desc_ptr->argc;
867 for (i = 0; i < argc; i++) {
868 const char *arg =
869 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
870 if ((strncmp(arg, "MEM=", 4) == 0) ||
871 (strncmp(arg, "mem=", 4) == 0)) {
872 max_memory = memparse(arg + 4, &p);
873 if (max_memory == 0)
874 max_memory = 32ull << 30;
875 if (*p == '@')
876 reserve_low_mem = memparse(p + 1, &p);
877#ifdef CONFIG_KEXEC
878 } else if (strncmp(arg, "crashkernel=", 12) == 0) {
879 crashk_size = memparse(arg+12, &p);
880 if (*p == '@')
881 crashk_base = memparse(p+1, &p);
882 strcat(arcs_cmdline, " ");
883 strcat(arcs_cmdline, arg);
884
885
886
887
888
889#endif
890 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
891 sizeof(arcs_cmdline) - 1) {
892 strcat(arcs_cmdline, " ");
893 strcat(arcs_cmdline, arg);
894 }
895 }
896
897 if (strstr(arcs_cmdline, "console=") == NULL) {
898 if (octeon_uart == 1)
899 strcat(arcs_cmdline, " console=ttyS1,115200");
900 else
901 strcat(arcs_cmdline, " console=ttyS0,115200");
902 }
903
904 mips_hpt_frequency = octeon_get_clock_rate();
905
906 octeon_init_cvmcount();
907
908 _machine_restart = octeon_restart;
909 _machine_halt = octeon_halt;
910
911#ifdef CONFIG_KEXEC
912 _machine_kexec_shutdown = octeon_shutdown;
913 _machine_crash_shutdown = octeon_crash_shutdown;
914 _machine_kexec_prepare = octeon_kexec_prepare;
915#ifdef CONFIG_SMP
916 _crash_smp_send_stop = octeon_crash_smp_send_stop;
917#endif
918#endif
919
920 octeon_user_io_init();
921 octeon_setup_smp();
922}
923
924
925#ifndef CONFIG_CRASH_DUMP
926static __init void memory_exclude_page(u64 addr, u64 *mem, u64 *size)
927{
928 if (addr > *mem && addr < *mem + *size) {
929 u64 inc = addr - *mem;
930 add_memory_region(*mem, inc, BOOT_MEM_RAM);
931 *mem += inc;
932 *size -= inc;
933 }
934
935 if (addr == *mem && *size > PAGE_SIZE) {
936 *mem += PAGE_SIZE;
937 *size -= PAGE_SIZE;
938 }
939}
940#endif
941
942void __init fw_init_cmdline(void)
943{
944 int i;
945
946 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
947 for (i = 0; i < octeon_boot_desc_ptr->argc; i++) {
948 const char *arg =
949 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
950 if (strlen(arcs_cmdline) + strlen(arg) + 1 <
951 sizeof(arcs_cmdline) - 1) {
952 strcat(arcs_cmdline, " ");
953 strcat(arcs_cmdline, arg);
954 }
955 }
956}
957
958void __init *plat_get_fdt(void)
959{
960 octeon_bootinfo =
961 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
962 return phys_to_virt(octeon_bootinfo->fdt_addr);
963}
964
965void __init plat_mem_setup(void)
966{
967 uint64_t mem_alloc_size;
968 uint64_t total;
969 uint64_t crashk_end;
970#ifndef CONFIG_CRASH_DUMP
971 int64_t memory;
972 uint64_t kernel_start;
973 uint64_t kernel_size;
974#endif
975
976 total = 0;
977 crashk_end = 0;
978
979
980
981
982
983
984
985
986 mem_alloc_size = 4 << 20;
987 if (mem_alloc_size > max_memory)
988 mem_alloc_size = max_memory;
989
990
991#ifdef CONFIG_CRASH_DUMP
992 add_memory_region(reserve_low_mem, max_memory, BOOT_MEM_RAM);
993 total += max_memory;
994#else
995#ifdef CONFIG_KEXEC
996 if (crashk_size > 0) {
997 add_memory_region(crashk_base, crashk_size, BOOT_MEM_RAM);
998 crashk_end = crashk_base + crashk_size;
999 }
1000#endif
1001
1002
1003
1004
1005
1006 cvmx_bootmem_lock();
1007 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
1008 && (total < max_memory)) {
1009 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
1010 __pa_symbol(&_end), -1,
1011 0x100000,
1012 CVMX_BOOTMEM_FLAG_NO_LOCKING);
1013 if (memory >= 0) {
1014 u64 size = mem_alloc_size;
1015#ifdef CONFIG_KEXEC
1016 uint64_t end;
1017#endif
1018
1019
1020
1021
1022
1023
1024
1025 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE,
1026 &memory, &size);
1027 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE +
1028 CVMX_PCIE_BAR1_PHYS_SIZE,
1029 &memory, &size);
1030#ifdef CONFIG_KEXEC
1031 end = memory + mem_alloc_size;
1032
1033
1034
1035
1036
1037
1038 if (memory < crashk_base && end > crashk_end) {
1039
1040 add_memory_region(memory,
1041 crashk_base - memory,
1042 BOOT_MEM_RAM);
1043 total += crashk_base - memory;
1044 add_memory_region(crashk_end,
1045 end - crashk_end,
1046 BOOT_MEM_RAM);
1047 total += end - crashk_end;
1048 continue;
1049 }
1050
1051 if (memory >= crashk_base && end <= crashk_end)
1052
1053
1054
1055
1056 continue;
1057
1058 if (memory > crashk_base && memory < crashk_end &&
1059 end > crashk_end) {
1060
1061
1062
1063
1064 mem_alloc_size -= crashk_end - memory;
1065 memory = crashk_end;
1066 } else if (memory < crashk_base && end > crashk_base &&
1067 end < crashk_end)
1068
1069
1070
1071
1072 mem_alloc_size -= end - crashk_base;
1073#endif
1074 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
1075 total += mem_alloc_size;
1076
1077 mem_alloc_size = 4 << 20;
1078 } else {
1079 break;
1080 }
1081 }
1082 cvmx_bootmem_unlock();
1083
1084 kernel_start = (unsigned long) _text;
1085 kernel_size = _end - _text;
1086
1087
1088 kernel_start &= ~0xffffffff80000000ULL;
1089 add_memory_region(kernel_start, kernel_size, BOOT_MEM_RAM);
1090#endif
1091
1092#ifdef CONFIG_CAVIUM_RESERVE32
1093
1094
1095
1096
1097
1098 if (octeon_reserve32_memory)
1099 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
1100#endif
1101
1102 if (total == 0)
1103 panic("Unable to allocate memory from "
1104 "cvmx_bootmem_phy_alloc");
1105}
1106
1107
1108
1109
1110
1111int prom_putchar(char c)
1112{
1113 uint64_t lsrval;
1114
1115
1116 do {
1117 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
1118 } while ((lsrval & 0x20) == 0);
1119
1120
1121 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c & 0xffull);
1122 return 1;
1123}
1124EXPORT_SYMBOL(prom_putchar);
1125
1126void __init prom_free_prom_memory(void)
1127{
1128 if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
1129
1130 u32 insn;
1131 u32 *foo;
1132
1133 foo = &insn;
1134
1135 asm volatile("# before" : : : "memory");
1136 prefetch(foo);
1137 asm volatile(
1138 ".set push\n\t"
1139 ".set noreorder\n\t"
1140 "bal 1f\n\t"
1141 "nop\n"
1142 "1:\tlw %0,-12($31)\n\t"
1143 ".set pop\n\t"
1144 : "=r" (insn) : : "$31", "memory");
1145
1146 if ((insn >> 26) != 0x33)
1147 panic("No PREF instruction at Core-14449 probe point.");
1148
1149 if (((insn >> 16) & 0x1f) != 28)
1150 panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
1151 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
1152 insn);
1153 }
1154}
1155
1156void __init octeon_fill_mac_addresses(void);
1157int octeon_prune_device_tree(void);
1158
1159extern const char __appended_dtb;
1160extern const char __dtb_octeon_3xxx_begin;
1161extern const char __dtb_octeon_68xx_begin;
1162void __init device_tree_init(void)
1163{
1164 const void *fdt;
1165 bool do_prune;
1166 bool fill_mac;
1167
1168#ifdef CONFIG_MIPS_ELF_APPENDED_DTB
1169 if (!fdt_check_header(&__appended_dtb)) {
1170 fdt = &__appended_dtb;
1171 do_prune = false;
1172 fill_mac = true;
1173 pr_info("Using appended Device Tree.\n");
1174 } else
1175#endif
1176 if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
1177 fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
1178 if (fdt_check_header(fdt))
1179 panic("Corrupt Device Tree passed to kernel.");
1180 do_prune = false;
1181 fill_mac = false;
1182 pr_info("Using passed Device Tree.\n");
1183 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
1184 fdt = &__dtb_octeon_68xx_begin;
1185 do_prune = true;
1186 fill_mac = true;
1187 } else {
1188 fdt = &__dtb_octeon_3xxx_begin;
1189 do_prune = true;
1190 fill_mac = true;
1191 }
1192
1193 initial_boot_params = (void *)fdt;
1194
1195 if (do_prune) {
1196 octeon_prune_device_tree();
1197 pr_info("Using internal Device Tree.\n");
1198 }
1199 if (fill_mac)
1200 octeon_fill_mac_addresses();
1201 unflatten_and_copy_device_tree();
1202 init_octeon_system_type();
1203}
1204
1205static int __initdata disable_octeon_edac_p;
1206
1207static int __init disable_octeon_edac(char *str)
1208{
1209 disable_octeon_edac_p = 1;
1210 return 0;
1211}
1212early_param("disable_octeon_edac", disable_octeon_edac);
1213
1214static char *edac_device_names[] = {
1215 "octeon_l2c_edac",
1216 "octeon_pc_edac",
1217};
1218
1219static int __init edac_devinit(void)
1220{
1221 struct platform_device *dev;
1222 int i, err = 0;
1223 int num_lmc;
1224 char *name;
1225
1226 if (disable_octeon_edac_p)
1227 return 0;
1228
1229 for (i = 0; i < ARRAY_SIZE(edac_device_names); i++) {
1230 name = edac_device_names[i];
1231 dev = platform_device_register_simple(name, -1, NULL, 0);
1232 if (IS_ERR(dev)) {
1233 pr_err("Registration of %s failed!\n", name);
1234 err = PTR_ERR(dev);
1235 }
1236 }
1237
1238 num_lmc = OCTEON_IS_MODEL(OCTEON_CN68XX) ? 4 :
1239 (OCTEON_IS_MODEL(OCTEON_CN56XX) ? 2 : 1);
1240 for (i = 0; i < num_lmc; i++) {
1241 dev = platform_device_register_simple("octeon_lmc_edac",
1242 i, NULL, 0);
1243 if (IS_ERR(dev)) {
1244 pr_err("Registration of octeon_lmc_edac %d failed!\n", i);
1245 err = PTR_ERR(dev);
1246 }
1247 }
1248
1249 return err;
1250}
1251device_initcall(edac_devinit);
1252
1253static void __initdata *octeon_dummy_iospace;
1254
1255static int __init octeon_no_pci_init(void)
1256{
1257
1258
1259
1260
1261 octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
1262 set_io_port_base((unsigned long)octeon_dummy_iospace);
1263 ioport_resource.start = MAX_RESOURCE;
1264 ioport_resource.end = 0;
1265 return 0;
1266}
1267core_initcall(octeon_no_pci_init);
1268
1269static int __init octeon_no_pci_release(void)
1270{
1271
1272
1273
1274 if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
1275 vfree(octeon_dummy_iospace);
1276 return 0;
1277}
1278late_initcall(octeon_no_pci_release);
1279