LXR linux/arch/mips/include/asm/mach-loongson64/loongson.h

   1/*
   2 * Copyright (C) 2009 Lemote, Inc.
   3 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
   4 *
   5 * This program is free software; you can redistribute  it and/or modify it
   6 * under  the terms of  the GNU General  Public License as published by the
   7 * Free Software Foundation;  either version 2 of the  License, or (at your
   8 * option) any later version.
   9 */
  10
  11#ifndef __ASM_MACH_LOONGSON64_LOONGSON_H
  12#define __ASM_MACH_LOONGSON64_LOONGSON_H
  13
  14#include <linux/io.h>
  15#include <linux/init.h>
  16#include <linux/irq.h>
  17#include <boot_param.h>
  18
  19/* loongson internal northbridge initialization */
  20extern void bonito_irq_init(void);
  21
  22/* machine-specific reboot/halt operation */
  23extern void mach_prepare_reboot(void);
  24extern void mach_prepare_shutdown(void);
  25
  26/* environment arguments from bootloader */
  27extern u32 cpu_clock_freq;
  28extern u32 memsize, highmemsize;
  29extern const struct plat_smp_ops loongson3_smp_ops;
  30
  31/* loongson-specific command line, env and memory initialization */
  32extern void __init prom_init_memory(void);
  33extern void __init prom_init_cmdline(void);
  34extern void __init prom_init_machtype(void);
  35extern void __init prom_init_env(void);
  36#ifdef CONFIG_LOONGSON_UART_BASE
  37extern unsigned long _loongson_uart_base[], loongson_uart_base[];
  38extern void prom_init_loongson_uart_base(void);
  39#endif
  40
  41static inline void prom_init_uart_base(void)
  42{
  43#ifdef CONFIG_LOONGSON_UART_BASE
  44        prom_init_loongson_uart_base();
  45#endif
  46}
  47
  48/* irq operation functions */
  49extern void bonito_irqdispatch(void);
  50extern void __init bonito_irq_init(void);
  51extern void __init mach_init_irq(void);
  52extern void mach_irq_dispatch(unsigned int pending);
  53extern int mach_i8259_irq(void);
  54
  55/* We need this in some places... */
  56#define delay() ({              \
  57        int x;                          \
  58        for (x = 0; x < 100000; x++)    \
  59                __asm__ __volatile__(""); \
  60})
  61
  62#define LOONGSON_REG(x) \
  63        (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
  64
  65#define LOONGSON3_REG8(base, x) \
  66        (*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
  67
  68#define LOONGSON3_REG32(base, x) \
  69        (*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))
  70
  71#define LOONGSON_IRQ_BASE       32
  72#define LOONGSON2_PERFCNT_IRQ   (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
  73
  74#include <linux/interrupt.h>
  75static inline void do_perfcnt_IRQ(void)
  76{
  77#if IS_ENABLED(CONFIG_OPROFILE)
  78        do_IRQ(LOONGSON2_PERFCNT_IRQ);
  79#endif
  80}
  81
  82#define LOONGSON_FLASH_BASE     0x1c000000
  83#define LOONGSON_FLASH_SIZE     0x02000000      /* 32M */
  84#define LOONGSON_FLASH_TOP      (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
  85
  86#define LOONGSON_LIO0_BASE      0x1e000000
  87#define LOONGSON_LIO0_SIZE      0x01C00000      /* 28M */
  88#define LOONGSON_LIO0_TOP       (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
  89
  90#define LOONGSON_BOOT_BASE      0x1fc00000
  91#define LOONGSON_BOOT_SIZE      0x00100000      /* 1M */
  92#define LOONGSON_BOOT_TOP       (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
  93#define LOONGSON_REG_BASE       0x1fe00000
  94#define LOONGSON_REG_SIZE       0x00100000      /* 256Bytes + 256Bytes + ??? */
  95#define LOONGSON_REG_TOP        (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
  96/* Loongson-3 specific registers */
  97#define LOONGSON3_REG_BASE      0x3ff00000
  98#define LOONGSON3_REG_SIZE      0x00100000      /* 256Bytes + 256Bytes + ??? */
  99#define LOONGSON3_REG_TOP       (LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
 100
 101#define LOONGSON_LIO1_BASE      0x1ff00000
 102#define LOONGSON_LIO1_SIZE      0x00100000      /* 1M */
 103#define LOONGSON_LIO1_TOP       (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
 104
 105#define LOONGSON_PCILO0_BASE    0x10000000
 106#define LOONGSON_PCILO1_BASE    0x14000000
 107#define LOONGSON_PCILO2_BASE    0x18000000
 108#define LOONGSON_PCILO_BASE     LOONGSON_PCILO0_BASE
 109#define LOONGSON_PCILO_SIZE     0x0c000000      /* 64M * 3 */
 110#define LOONGSON_PCILO_TOP      (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
 111
 112#define LOONGSON_PCICFG_BASE    0x1fe80000
 113#define LOONGSON_PCICFG_SIZE    0x00000800      /* 2K */
 114#define LOONGSON_PCICFG_TOP     (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
 115
 116#if defined(CONFIG_HT_PCI)
 117#define LOONGSON_PCIIO_BASE     loongson_sysconf.pci_io_base
 118#else
 119#define LOONGSON_PCIIO_BASE     0x1fd00000
 120#endif
 121
 122#define LOONGSON_PCIIO_SIZE     0x00100000      /* 1M */
 123#define LOONGSON_PCIIO_TOP      (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
 124
 125/* Loongson Register Bases */
 126
 127#define LOONGSON_PCICONFIGBASE  0x00
 128#define LOONGSON_REGBASE        0x100
 129
 130/* PCI Configuration Registers */
 131
 132#define LOONGSON_PCI_REG(x)     LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
 133#define LOONGSON_PCIDID         LOONGSON_PCI_REG(0x00)
 134#define LOONGSON_PCICMD         LOONGSON_PCI_REG(0x04)
 135#define LOONGSON_PCICLASS       LOONGSON_PCI_REG(0x08)
 136#define LOONGSON_PCILTIMER      LOONGSON_PCI_REG(0x0c)
 137#define LOONGSON_PCIBASE0       LOONGSON_PCI_REG(0x10)
 138#define LOONGSON_PCIBASE1       LOONGSON_PCI_REG(0x14)
 139#define LOONGSON_PCIBASE2       LOONGSON_PCI_REG(0x18)
 140#define LOONGSON_PCIBASE3       LOONGSON_PCI_REG(0x1c)
 141#define LOONGSON_PCIBASE4       LOONGSON_PCI_REG(0x20)
 142#define LOONGSON_PCIEXPRBASE    LOONGSON_PCI_REG(0x30)
 143#define LOONGSON_PCIINT         LOONGSON_PCI_REG(0x3c)
 144
 145#define LOONGSON_PCI_ISR4C      LOONGSON_PCI_REG(0x4c)
 146
 147#define LOONGSON_PCICMD_PERR_CLR        0x80000000
 148#define LOONGSON_PCICMD_SERR_CLR        0x40000000
 149#define LOONGSON_PCICMD_MABORT_CLR      0x20000000
 150#define LOONGSON_PCICMD_MTABORT_CLR     0x10000000
 151#define LOONGSON_PCICMD_TABORT_CLR      0x08000000
 152#define LOONGSON_PCICMD_MPERR_CLR       0x01000000
 153#define LOONGSON_PCICMD_PERRRESPEN      0x00000040
 154#define LOONGSON_PCICMD_ASTEPEN         0x00000080
 155#define LOONGSON_PCICMD_SERREN          0x00000100
 156#define LOONGSON_PCILTIMER_BUSLATENCY   0x0000ff00
 157#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT     8
 158
 159/* Loongson h/w Configuration */
 160
 161#define LOONGSON_GENCFG_OFFSET          0x4
 162#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
 163
 164#define LOONGSON_GENCFG_DEBUGMODE       0x00000001
 165#define LOONGSON_GENCFG_SNOOPEN         0x00000002
 166#define LOONGSON_GENCFG_CPUSELFRESET    0x00000004
 167
 168#define LOONGSON_GENCFG_FORCE_IRQA      0x00000008
 169#define LOONGSON_GENCFG_IRQA_ISOUT      0x00000010
 170#define LOONGSON_GENCFG_IRQA_FROM_INT1  0x00000020
 171#define LOONGSON_GENCFG_BYTESWAP        0x00000040
 172
 173#define LOONGSON_GENCFG_UNCACHED        0x00000080
 174#define LOONGSON_GENCFG_PREFETCHEN      0x00000100
 175#define LOONGSON_GENCFG_WBEHINDEN       0x00000200
 176#define LOONGSON_GENCFG_CACHEALG        0x00000c00
 177#define LOONGSON_GENCFG_CACHEALG_SHIFT  10
 178#define LOONGSON_GENCFG_PCIQUEUE        0x00001000
 179#define LOONGSON_GENCFG_CACHESTOP       0x00002000
 180#define LOONGSON_GENCFG_MSTRBYTESWAP    0x00004000
 181#define LOONGSON_GENCFG_BUSERREN        0x00008000
 182#define LOONGSON_GENCFG_NORETRYTIMEOUT  0x00010000
 183#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT        0x00020000
 184
 185/* PCI address map control */
 186
 187#define LOONGSON_PCIMAP                 LOONGSON_REG(LOONGSON_REGBASE + 0x10)
 188#define LOONGSON_PCIMEMBASECFG          LOONGSON_REG(LOONGSON_REGBASE + 0x14)
 189#define LOONGSON_PCIMAP_CFG             LOONGSON_REG(LOONGSON_REGBASE + 0x18)
 190
 191/* GPIO Regs - r/w */
 192
 193#define LOONGSON_GPIODATA               LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
 194#define LOONGSON_GPIOIE                 LOONGSON_REG(LOONGSON_REGBASE + 0x20)
 195
 196/* ICU Configuration Regs - r/w */
 197
 198#define LOONGSON_INTEDGE                LOONGSON_REG(LOONGSON_REGBASE + 0x24)
 199#define LOONGSON_INTSTEER               LOONGSON_REG(LOONGSON_REGBASE + 0x28)
 200#define LOONGSON_INTPOL                 LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
 201
 202/* ICU Enable Regs - IntEn & IntISR are r/o. */
 203
 204#define LOONGSON_INTENSET               LOONGSON_REG(LOONGSON_REGBASE + 0x30)
 205#define LOONGSON_INTENCLR               LOONGSON_REG(LOONGSON_REGBASE + 0x34)
 206#define LOONGSON_INTEN                  LOONGSON_REG(LOONGSON_REGBASE + 0x38)
 207#define LOONGSON_INTISR                 LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
 208
 209/* ICU */
 210#define LOONGSON_ICU_MBOXES             0x0000000f
 211#define LOONGSON_ICU_MBOXES_SHIFT       0
 212#define LOONGSON_ICU_DMARDY             0x00000010
 213#define LOONGSON_ICU_DMAEMPTY           0x00000020
 214#define LOONGSON_ICU_COPYRDY            0x00000040
 215#define LOONGSON_ICU_COPYEMPTY          0x00000080
 216#define LOONGSON_ICU_COPYERR            0x00000100
 217#define LOONGSON_ICU_PCIIRQ             0x00000200
 218#define LOONGSON_ICU_MASTERERR          0x00000400
 219#define LOONGSON_ICU_SYSTEMERR          0x00000800
 220#define LOONGSON_ICU_DRAMPERR           0x00001000
 221#define LOONGSON_ICU_RETRYERR           0x00002000
 222#define LOONGSON_ICU_GPIOS              0x01ff0000
 223#define LOONGSON_ICU_GPIOS_SHIFT                16
 224#define LOONGSON_ICU_GPINS              0x7e000000
 225#define LOONGSON_ICU_GPINS_SHIFT                25
 226#define LOONGSON_ICU_MBOX(N)            (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
 227#define LOONGSON_ICU_GPIO(N)            (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
 228#define LOONGSON_ICU_GPIN(N)            (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
 229
 230/* PCI prefetch window base & mask */
 231
 232#define LOONGSON_MEM_WIN_BASE_L         LOONGSON_REG(LOONGSON_REGBASE + 0x40)
 233#define LOONGSON_MEM_WIN_BASE_H         LOONGSON_REG(LOONGSON_REGBASE + 0x44)
 234#define LOONGSON_MEM_WIN_MASK_L         LOONGSON_REG(LOONGSON_REGBASE + 0x48)
 235#define LOONGSON_MEM_WIN_MASK_H         LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
 236
 237/* PCI_Hit*_Sel_* */
 238
 239#define LOONGSON_PCI_HIT0_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x50)
 240#define LOONGSON_PCI_HIT0_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x54)
 241#define LOONGSON_PCI_HIT1_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x58)
 242#define LOONGSON_PCI_HIT1_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
 243#define LOONGSON_PCI_HIT2_SEL_L         LOONGSON_REG(LOONGSON_REGBASE + 0x60)
 244#define LOONGSON_PCI_HIT2_SEL_H         LOONGSON_REG(LOONGSON_REGBASE + 0x64)
 245
 246/* PXArb Config & Status */
 247
 248#define LOONGSON_PXARB_CFG              LOONGSON_REG(LOONGSON_REGBASE + 0x68)
 249#define LOONGSON_PXARB_STATUS           LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
 250
 251#define MAX_PACKAGES 4
 252
 253/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
 254extern u64 loongson_chipcfg[MAX_PACKAGES];
 255#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
 256
 257/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */
 258extern u64 loongson_chiptemp[MAX_PACKAGES];
 259#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
 260
 261/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
 262extern u64 loongson_freqctrl[MAX_PACKAGES];
 263#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
 264
 265/* pcimap */
 266
 267#define LOONGSON_PCIMAP_PCIMAP_LO0      0x0000003f
 268#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT        0
 269#define LOONGSON_PCIMAP_PCIMAP_LO1      0x00000fc0
 270#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT        6
 271#define LOONGSON_PCIMAP_PCIMAP_LO2      0x0003f000
 272#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT        12
 273#define LOONGSON_PCIMAP_PCIMAP_2        0x00040000
 274#define LOONGSON_PCIMAP_WIN(WIN, ADDR)  \
 275        ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
 276
 277#ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
 278#include <linux/cpufreq.h>
 279extern struct cpufreq_frequency_table loongson2_clockmod_table[];
 280#endif
 281
 282/*
 283 * address windows configuration module
 284 *
 285 * loongson2e do not have this module
 286 */
 287#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
 288
 289/* address window config module base address */
 290#define LOONGSON_ADDRWINCFG_BASE                0x3ff00000ul
 291#define LOONGSON_ADDRWINCFG_SIZE                0x180
 292
 293extern unsigned long _loongson_addrwincfg_base;
 294#define LOONGSON_ADDRWINCFG(offset) \
 295        (*(volatile u64 *)(_loongson_addrwincfg_base + (offset)))
 296
 297#define CPU_WIN0_BASE   LOONGSON_ADDRWINCFG(0x00)
 298#define CPU_WIN1_BASE   LOONGSON_ADDRWINCFG(0x08)
 299#define CPU_WIN2_BASE   LOONGSON_ADDRWINCFG(0x10)
 300#define CPU_WIN3_BASE   LOONGSON_ADDRWINCFG(0x18)
 301
 302#define CPU_WIN0_MASK   LOONGSON_ADDRWINCFG(0x20)
 303#define CPU_WIN1_MASK   LOONGSON_ADDRWINCFG(0x28)
 304#define CPU_WIN2_MASK   LOONGSON_ADDRWINCFG(0x30)
 305#define CPU_WIN3_MASK   LOONGSON_ADDRWINCFG(0x38)
 306
 307#define CPU_WIN0_MMAP   LOONGSON_ADDRWINCFG(0x40)
 308#define CPU_WIN1_MMAP   LOONGSON_ADDRWINCFG(0x48)
 309#define CPU_WIN2_MMAP   LOONGSON_ADDRWINCFG(0x50)
 310#define CPU_WIN3_MMAP   LOONGSON_ADDRWINCFG(0x58)
 311
 312#define PCIDMA_WIN0_BASE        LOONGSON_ADDRWINCFG(0x60)
 313#define PCIDMA_WIN1_BASE        LOONGSON_ADDRWINCFG(0x68)
 314#define PCIDMA_WIN2_BASE        LOONGSON_ADDRWINCFG(0x70)
 315#define PCIDMA_WIN3_BASE        LOONGSON_ADDRWINCFG(0x78)
 316
 317#define PCIDMA_WIN0_MASK        LOONGSON_ADDRWINCFG(0x80)
 318#define PCIDMA_WIN1_MASK        LOONGSON_ADDRWINCFG(0x88)
 319#define PCIDMA_WIN2_MASK        LOONGSON_ADDRWINCFG(0x90)
 320#define PCIDMA_WIN3_MASK        LOONGSON_ADDRWINCFG(0x98)
 321
 322#define PCIDMA_WIN0_MMAP        LOONGSON_ADDRWINCFG(0xa0)
 323#define PCIDMA_WIN1_MMAP        LOONGSON_ADDRWINCFG(0xa8)
 324#define PCIDMA_WIN2_MMAP        LOONGSON_ADDRWINCFG(0xb0)
 325#define PCIDMA_WIN3_MMAP        LOONGSON_ADDRWINCFG(0xb8)
 326
 327#define ADDRWIN_WIN0    0
 328#define ADDRWIN_WIN1    1
 329#define ADDRWIN_WIN2    2
 330#define ADDRWIN_WIN3    3
 331
 332#define ADDRWIN_MAP_DST_DDR     0
 333#define ADDRWIN_MAP_DST_PCI     1
 334#define ADDRWIN_MAP_DST_LIO     1
 335
 336/*
 337 * s: CPU, PCIDMA
 338 * d: DDR, PCI, LIO
 339 * win: 0, 1, 2, 3
 340 * src: map source
 341 * dst: map destination
 342 * size: ~mask + 1
 343 */
 344#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\
 345        s##_WIN##w##_BASE = (src); \
 346        s##_WIN##w##_MMAP = (dst) | ADDRWIN_MAP_DST_##d; \
 347        s##_WIN##w##_MASK = ~(size-1); \
 348} while (0)
 349
 350#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \
 351        LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size)
 352#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \
 353        LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
 354#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \
 355        LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
 356
 357#endif  /* ! CONFIG_CPU_SUPPORTS_ADDRWINCFG */
 358
 359#endif /* __ASM_MACH_LOONGSON64_LOONGSON_H */
 360