LXR linux/arch/powerpc/boot/ppc

   1#ifndef _PPC64_PPC_ASM_H
   2#define _PPC64_PPC_ASM_H
   3/*
   4 *
   5 * Definitions used by various bits of low-level assembly code on PowerPC.
   6 *
   7 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
   8 *
   9 *  This program is free software; you can redistribute it and/or
  10 *  modify it under the terms of the GNU General Public License
  11 *  as published by the Free Software Foundation; either version
  12 *  2 of the License, or (at your option) any later version.
  13 */
  14
  15/* Condition Register Bit Fields */
  16
  17#define cr0     0
  18#define cr1     1
  19#define cr2     2
  20#define cr3     3
  21#define cr4     4
  22#define cr5     5
  23#define cr6     6
  24#define cr7     7
  25
  26
  27/* General Purpose Registers (GPRs) */
  28
  29#define r0      0
  30#define r1      1
  31#define r2      2
  32#define r3      3
  33#define r4      4
  34#define r5      5
  35#define r6      6
  36#define r7      7
  37#define r8      8
  38#define r9      9
  39#define r10     10
  40#define r11     11
  41#define r12     12
  42#define r13     13
  43#define r14     14
  44#define r15     15
  45#define r16     16
  46#define r17     17
  47#define r18     18
  48#define r19     19
  49#define r20     20
  50#define r21     21
  51#define r22     22
  52#define r23     23
  53#define r24     24
  54#define r25     25
  55#define r26     26
  56#define r27     27
  57#define r28     28
  58#define r29     29
  59#define r30     30
  60#define r31     31
  61
  62#define SPRN_TBRL       268
  63#define SPRN_TBRU       269
  64#define SPRN_HSRR0      0x13A   /* Hypervisor Save/Restore 0 */
  65#define SPRN_HSRR1      0x13B   /* Hypervisor Save/Restore 1 */
  66
  67#define MSR_LE          0x0000000000000001
  68
  69#define FIXUP_ENDIAN                                               \
  70        tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
  71        b     $+44;       /* Skip trampoline if endian is good  */ \
  72        .long 0xa600607d; /* mfmsr r11                          */ \
  73        .long 0x01006b69; /* xori r11,r11,1                     */ \
  74        .long 0x00004039; /* li r10,0                           */ \
  75        .long 0x6401417d; /* mtmsrd r10,1                       */ \
  76        .long 0x05009f42; /* bcl 20,31,$+4                      */ \
  77        .long 0xa602487d; /* mflr r10                           */ \
  78        .long 0x14004a39; /* addi r10,r10,20                    */ \
  79        .long 0xa6035a7d; /* mtsrr0 r10                         */ \
  80        .long 0xa6037b7d; /* mtsrr1 r11                         */ \
  81        .long 0x2400004c  /* rfid                               */
  82
  83#ifdef CONFIG_PPC_8xx
  84#define MFTBL(dest)                     mftb dest
  85#define MFTBU(dest)                     mftbu dest
  86#else
  87#define MFTBL(dest)                     mfspr dest, SPRN_TBRL
  88#define MFTBU(dest)                     mfspr dest, SPRN_TBRU
  89#endif
  90
  91#endif /* _PPC64_PPC_ASM_H */
  92