LXR linux/arch/powerpc/include/asm/eeh.h

   1/*
   2 * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
   3 * Copyright 2001-2012 IBM Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18 */
  19
  20#ifndef _POWERPC_EEH_H
  21#define _POWERPC_EEH_H
  22#ifdef __KERNEL__
  23
  24#include <linux/init.h>
  25#include <linux/list.h>
  26#include <linux/string.h>
  27#include <linux/time.h>
  28#include <linux/atomic.h>
  29
  30#include <uapi/asm/eeh.h>
  31
  32struct pci_dev;
  33struct pci_bus;
  34struct pci_dn;
  35
  36#ifdef CONFIG_EEH
  37
  38/* EEH subsystem flags */
  39#define EEH_ENABLED             0x01    /* EEH enabled          */
  40#define EEH_FORCE_DISABLED      0x02    /* EEH disabled         */
  41#define EEH_PROBE_MODE_DEV      0x04    /* From PCI device      */
  42#define EEH_PROBE_MODE_DEVTREE  0x08    /* From device tree     */
  43#define EEH_VALID_PE_ZERO       0x10    /* PE#0 is valid        */
  44#define EEH_ENABLE_IO_FOR_LOG   0x20    /* Enable IO for log    */
  45#define EEH_EARLY_DUMP_LOG      0x40    /* Dump log immediately */
  46
  47/*
  48 * Delay for PE reset, all in ms
  49 *
  50 * PCI specification has reset hold time of 100 milliseconds.
  51 * We have 250 milliseconds here. The PCI bus settlement time
  52 * is specified as 1.5 seconds and we have 1.8 seconds.
  53 */
  54#define EEH_PE_RST_HOLD_TIME            250
  55#define EEH_PE_RST_SETTLE_TIME          1800
  56
  57/*
  58 * The struct is used to trace PE related EEH functionality.
  59 * In theory, there will have one instance of the struct to
  60 * be created against particular PE. In nature, PEs correlate
  61 * to each other. the struct has to reflect that hierarchy in
  62 * order to easily pick up those affected PEs when one particular
  63 * PE has EEH errors.
  64 *
  65 * Also, one particular PE might be composed of PCI device, PCI
  66 * bus and its subordinate components. The struct also need ship
  67 * the information. Further more, one particular PE is only meaingful
  68 * in the corresponding PHB. Therefore, the root PEs should be created
  69 * against existing PHBs in on-to-one fashion.
  70 */
  71#define EEH_PE_INVALID  (1 << 0)        /* Invalid   */
  72#define EEH_PE_PHB      (1 << 1)        /* PHB PE    */
  73#define EEH_PE_DEVICE   (1 << 2)        /* Device PE */
  74#define EEH_PE_BUS      (1 << 3)        /* Bus PE    */
  75#define EEH_PE_VF       (1 << 4)        /* VF PE     */
  76
  77#define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
  78#define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
  79#define EEH_PE_CFG_BLOCKED      (1 << 2)        /* Block config access  */
  80#define EEH_PE_RESET            (1 << 3)        /* PE reset in progress */
  81
  82#define EEH_PE_KEEP             (1 << 8)        /* Keep PE on hotplug   */
  83#define EEH_PE_CFG_RESTRICTED   (1 << 9)        /* Block config on error */
  84#define EEH_PE_REMOVED          (1 << 10)       /* Removed permanently  */
  85#define EEH_PE_PRI_BUS          (1 << 11)       /* Cached primary bus   */
  86
  87struct eeh_pe {
  88        int type;                       /* PE type: PHB/Bus/Device      */
  89        int state;                      /* PE EEH dependent mode        */
  90        int config_addr;                /* Traditional PCI address      */
  91        int addr;                       /* PE configuration address     */
  92        struct pci_controller *phb;     /* Associated PHB               */
  93        struct pci_bus *bus;            /* Top PCI bus for bus PE       */
  94        int check_count;                /* Times of ignored error       */
  95        int freeze_count;               /* Times of froze up            */
  96        time64_t tstamp;                /* Time on first-time freeze    */
  97        int false_positives;            /* Times of reported #ff's      */
  98        atomic_t pass_dev_cnt;          /* Count of passed through devs */
  99        struct eeh_pe *parent;          /* Parent PE                    */
 100        void *data;                     /* PE auxillary data            */
 101        struct list_head child_list;    /* Link PE to the child list    */
 102        struct list_head edevs;         /* Link list of EEH devices     */
 103        struct list_head child;         /* Child PEs                    */
 104};
 105
 106#define eeh_pe_for_each_dev(pe, edev, tmp) \
 107                list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
 108
 109static inline bool eeh_pe_passed(struct eeh_pe *pe)
 110{
 111        return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
 112}
 113
 114/*
 115 * The struct is used to trace EEH state for the associated
 116 * PCI device node or PCI device. In future, it might
 117 * represent PE as well so that the EEH device to form
 118 * another tree except the currently existing tree of PCI
 119 * buses and PCI devices
 120 */
 121#define EEH_DEV_BRIDGE          (1 << 0)        /* PCI bridge           */
 122#define EEH_DEV_ROOT_PORT       (1 << 1)        /* PCIe root port       */
 123#define EEH_DEV_DS_PORT         (1 << 2)        /* Downstream port      */
 124#define EEH_DEV_IRQ_DISABLED    (1 << 3)        /* Interrupt disabled   */
 125#define EEH_DEV_DISCONNECTED    (1 << 4)        /* Removing from PE     */
 126
 127#define EEH_DEV_NO_HANDLER      (1 << 8)        /* No error handler     */
 128#define EEH_DEV_SYSFS           (1 << 9)        /* Sysfs created        */
 129#define EEH_DEV_REMOVED         (1 << 10)       /* Removed permanently  */
 130
 131struct eeh_dev {
 132        int mode;                       /* EEH mode                     */
 133        int class_code;                 /* Class code of the device     */
 134        int pe_config_addr;             /* PE config address            */
 135        u32 config_space[16];           /* Saved PCI config space       */
 136        int pcix_cap;                   /* Saved PCIx capability        */
 137        int pcie_cap;                   /* Saved PCIe capability        */
 138        int aer_cap;                    /* Saved AER capability         */
 139        int af_cap;                     /* Saved AF capability          */
 140        struct eeh_pe *pe;              /* Associated PE                */
 141        struct list_head list;          /* Form link list in the PE     */
 142        struct list_head rmv_list;      /* Record the removed edevs     */
 143        struct pci_dn *pdn;             /* Associated PCI device node   */
 144        struct pci_dev *pdev;           /* Associated PCI device        */
 145        bool in_error;                  /* Error flag for edev          */
 146        struct pci_dev *physfn;         /* Associated SRIOV PF          */
 147        struct pci_bus *bus;            /* PCI bus for partial hotplug  */
 148};
 149
 150static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
 151{
 152        return edev ? edev->pdn : NULL;
 153}
 154
 155static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 156{
 157        return edev ? edev->pdev : NULL;
 158}
 159
 160static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
 161{
 162        return edev ? edev->pe : NULL;
 163}
 164
 165/* Return values from eeh_ops::next_error */
 166enum {
 167        EEH_NEXT_ERR_NONE = 0,
 168        EEH_NEXT_ERR_INF,
 169        EEH_NEXT_ERR_FROZEN_PE,
 170        EEH_NEXT_ERR_FENCED_PHB,
 171        EEH_NEXT_ERR_DEAD_PHB,
 172        EEH_NEXT_ERR_DEAD_IOC
 173};
 174
 175/*
 176 * The struct is used to trace the registered EEH operation
 177 * callback functions. Actually, those operation callback
 178 * functions are heavily platform dependent. That means the
 179 * platform should register its own EEH operation callback
 180 * functions before any EEH further operations.
 181 */
 182#define EEH_OPT_DISABLE         0       /* EEH disable  */
 183#define EEH_OPT_ENABLE          1       /* EEH enable   */
 184#define EEH_OPT_THAW_MMIO       2       /* MMIO enable  */
 185#define EEH_OPT_THAW_DMA        3       /* DMA enable   */
 186#define EEH_OPT_FREEZE_PE       4       /* Freeze PE    */
 187#define EEH_STATE_UNAVAILABLE   (1 << 0)        /* State unavailable    */
 188#define EEH_STATE_NOT_SUPPORT   (1 << 1)        /* EEH not supported    */
 189#define EEH_STATE_RESET_ACTIVE  (1 << 2)        /* Active reset         */
 190#define EEH_STATE_MMIO_ACTIVE   (1 << 3)        /* Active MMIO          */
 191#define EEH_STATE_DMA_ACTIVE    (1 << 4)        /* Active DMA           */
 192#define EEH_STATE_MMIO_ENABLED  (1 << 5)        /* MMIO enabled         */
 193#define EEH_STATE_DMA_ENABLED   (1 << 6)        /* DMA enabled          */
 194#define EEH_RESET_DEACTIVATE    0       /* Deactivate the PE reset      */
 195#define EEH_RESET_HOT           1       /* Hot reset                    */
 196#define EEH_RESET_FUNDAMENTAL   3       /* Fundamental reset            */
 197#define EEH_LOG_TEMP            1       /* EEH temporary error log      */
 198#define EEH_LOG_PERM            2       /* EEH permanent error log      */
 199
 200struct eeh_ops {
 201        char *name;
 202        int (*init)(void);
 203        void* (*probe)(struct pci_dn *pdn, void *data);
 204        int (*set_option)(struct eeh_pe *pe, int option);
 205        int (*get_pe_addr)(struct eeh_pe *pe);
 206        int (*get_state)(struct eeh_pe *pe, int *state);
 207        int (*reset)(struct eeh_pe *pe, int option);
 208        int (*wait_state)(struct eeh_pe *pe, int max_wait);
 209        int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
 210        int (*configure_bridge)(struct eeh_pe *pe);
 211        int (*err_inject)(struct eeh_pe *pe, int type, int func,
 212                          unsigned long addr, unsigned long mask);
 213        int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
 214        int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
 215        int (*next_error)(struct eeh_pe **pe);
 216        int (*restore_config)(struct pci_dn *pdn);
 217        int (*notify_resume)(struct pci_dn *pdn);
 218};
 219
 220extern int eeh_subsystem_flags;
 221extern int eeh_max_freezes;
 222extern struct eeh_ops *eeh_ops;
 223extern raw_spinlock_t confirm_error_lock;
 224
 225static inline void eeh_add_flag(int flag)
 226{
 227        eeh_subsystem_flags |= flag;
 228}
 229
 230static inline void eeh_clear_flag(int flag)
 231{
 232        eeh_subsystem_flags &= ~flag;
 233}
 234
 235static inline bool eeh_has_flag(int flag)
 236{
 237        return !!(eeh_subsystem_flags & flag);
 238}
 239
 240static inline bool eeh_enabled(void)
 241{
 242        if (eeh_has_flag(EEH_FORCE_DISABLED) ||
 243            !eeh_has_flag(EEH_ENABLED))
 244                return false;
 245
 246        return true;
 247}
 248
 249static inline void eeh_serialize_lock(unsigned long *flags)
 250{
 251        raw_spin_lock_irqsave(&confirm_error_lock, *flags);
 252}
 253
 254static inline void eeh_serialize_unlock(unsigned long flags)
 255{
 256        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 257}
 258
 259static inline bool eeh_state_active(int state)
 260{
 261        return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
 262        == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
 263}
 264
 265typedef void *(*eeh_traverse_func)(void *data, void *flag);
 266void eeh_set_pe_aux_size(int size);
 267int eeh_phb_pe_create(struct pci_controller *phb);
 268struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
 269struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
 270                          int pe_no, int config_addr);
 271int eeh_add_to_parent_pe(struct eeh_dev *edev);
 272int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
 273void eeh_pe_update_time_stamp(struct eeh_pe *pe);
 274void *eeh_pe_traverse(struct eeh_pe *root,
 275                eeh_traverse_func fn, void *flag);
 276void *eeh_pe_dev_traverse(struct eeh_pe *root,
 277                eeh_traverse_func fn, void *flag);
 278void eeh_pe_restore_bars(struct eeh_pe *pe);
 279const char *eeh_pe_loc_get(struct eeh_pe *pe);
 280struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
 281
 282struct eeh_dev *eeh_dev_init(struct pci_dn *pdn);
 283void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
 284void eeh_probe_devices(void);
 285int __init eeh_ops_register(struct eeh_ops *ops);
 286int __exit eeh_ops_unregister(const char *name);
 287int eeh_check_failure(const volatile void __iomem *token);
 288int eeh_dev_check_failure(struct eeh_dev *edev);
 289void eeh_addr_cache_build(void);
 290void eeh_add_device_early(struct pci_dn *);
 291void eeh_add_device_tree_early(struct pci_dn *);
 292void eeh_add_device_late(struct pci_dev *);
 293void eeh_add_device_tree_late(struct pci_bus *);
 294void eeh_add_sysfs_files(struct pci_bus *);
 295void eeh_remove_device(struct pci_dev *);
 296int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
 297int eeh_pe_reset_and_recover(struct eeh_pe *pe);
 298int eeh_dev_open(struct pci_dev *pdev);
 299void eeh_dev_release(struct pci_dev *pdev);
 300struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
 301int eeh_pe_set_option(struct eeh_pe *pe, int option);
 302int eeh_pe_get_state(struct eeh_pe *pe);
 303int eeh_pe_reset(struct eeh_pe *pe, int option);
 304int eeh_pe_configure(struct eeh_pe *pe);
 305int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
 306                      unsigned long addr, unsigned long mask);
 307int eeh_restore_vf_config(struct pci_dn *pdn);
 308
 309/**
 310 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
 311 *
 312 * If this macro yields TRUE, the caller relays to eeh_check_failure()
 313 * which does further tests out of line.
 314 */
 315#define EEH_POSSIBLE_ERROR(val, type)   ((val) == (type)~0 && eeh_enabled())
 316
 317/*
 318 * Reads from a device which has been isolated by EEH will return
 319 * all 1s.  This macro gives an all-1s value of the given size (in
 320 * bytes: 1, 2, or 4) for comparing with the result of a read.
 321 */
 322#define EEH_IO_ERROR_VALUE(size)        (~0U >> ((4 - (size)) * 8))
 323
 324#else /* !CONFIG_EEH */
 325
 326static inline bool eeh_enabled(void)
 327{
 328        return false;
 329}
 330
 331static inline void eeh_probe_devices(void) { }
 332
 333static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
 334{
 335        return NULL;
 336}
 337
 338static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
 339
 340static inline int eeh_check_failure(const volatile void __iomem *token)
 341{
 342        return 0;
 343}
 344
 345#define eeh_dev_check_failure(x) (0)
 346
 347static inline void eeh_addr_cache_build(void) { }
 348
 349static inline void eeh_add_device_early(struct pci_dn *pdn) { }
 350
 351static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
 352
 353static inline void eeh_add_device_late(struct pci_dev *dev) { }
 354
 355static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
 356
 357static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
 358
 359static inline void eeh_remove_device(struct pci_dev *dev) { }
 360
 361#define EEH_POSSIBLE_ERROR(val, type) (0)
 362#define EEH_IO_ERROR_VALUE(size) (-1UL)
 363#endif /* CONFIG_EEH */
 364
 365#ifdef CONFIG_PPC64
 366/*
 367 * MMIO read/write operations with EEH support.
 368 */
 369static inline u8 eeh_readb(const volatile void __iomem *addr)
 370{
 371        u8 val = in_8(addr);
 372        if (EEH_POSSIBLE_ERROR(val, u8))
 373                eeh_check_failure(addr);
 374        return val;
 375}
 376
 377static inline u16 eeh_readw(const volatile void __iomem *addr)
 378{
 379        u16 val = in_le16(addr);
 380        if (EEH_POSSIBLE_ERROR(val, u16))
 381                eeh_check_failure(addr);
 382        return val;
 383}
 384
 385static inline u32 eeh_readl(const volatile void __iomem *addr)
 386{
 387        u32 val = in_le32(addr);
 388        if (EEH_POSSIBLE_ERROR(val, u32))
 389                eeh_check_failure(addr);
 390        return val;
 391}
 392
 393static inline u64 eeh_readq(const volatile void __iomem *addr)
 394{
 395        u64 val = in_le64(addr);
 396        if (EEH_POSSIBLE_ERROR(val, u64))
 397                eeh_check_failure(addr);
 398        return val;
 399}
 400
 401static inline u16 eeh_readw_be(const volatile void __iomem *addr)
 402{
 403        u16 val = in_be16(addr);
 404        if (EEH_POSSIBLE_ERROR(val, u16))
 405                eeh_check_failure(addr);
 406        return val;
 407}
 408
 409static inline u32 eeh_readl_be(const volatile void __iomem *addr)
 410{
 411        u32 val = in_be32(addr);
 412        if (EEH_POSSIBLE_ERROR(val, u32))
 413                eeh_check_failure(addr);
 414        return val;
 415}
 416
 417static inline u64 eeh_readq_be(const volatile void __iomem *addr)
 418{
 419        u64 val = in_be64(addr);
 420        if (EEH_POSSIBLE_ERROR(val, u64))
 421                eeh_check_failure(addr);
 422        return val;
 423}
 424
 425static inline void eeh_memcpy_fromio(void *dest, const
 426                                     volatile void __iomem *src,
 427                                     unsigned long n)
 428{
 429        _memcpy_fromio(dest, src, n);
 430
 431        /* Look for ffff's here at dest[n].  Assume that at least 4 bytes
 432         * were copied. Check all four bytes.
 433         */
 434        if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
 435                eeh_check_failure(src);
 436}
 437
 438/* in-string eeh macros */
 439static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
 440                              int ns)
 441{
 442        _insb(addr, buf, ns);
 443        if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
 444                eeh_check_failure(addr);
 445}
 446
 447static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
 448                              int ns)
 449{
 450        _insw(addr, buf, ns);
 451        if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
 452                eeh_check_failure(addr);
 453}
 454
 455static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
 456                              int nl)
 457{
 458        _insl(addr, buf, nl);
 459        if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
 460                eeh_check_failure(addr);
 461}
 462
 463#endif /* CONFIG_PPC64 */
 464#endif /* __KERNEL__ */
 465#endif /* _POWERPC_EEH_H */
 466