LXR linux/arch/powerpc/kernel/head

   1/*
   2 *  PowerPC version
   3 *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4 *
   5 *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
   6 *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   7 *  Adapted for Power Macintosh by Paul Mackerras.
   8 *  Low-level exception handlers and MMU support
   9 *  rewritten by Paul Mackerras.
  10 *    Copyright (C) 1996 Paul Mackerras.
  11 *  MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
  12 *
  13 *  This file contains the low-level support and setup for the
  14 *  PowerPC platform, including trap and interrupt dispatch.
  15 *  (The PPC 8xx embedded CPUs use head_8xx.S instead.)
  16 *
  17 *  This program is free software; you can redistribute it and/or
  18 *  modify it under the terms of the GNU General Public License
  19 *  as published by the Free Software Foundation; either version
  20 *  2 of the License, or (at your option) any later version.
  21 *
  22 */
  23
  24#include <linux/init.h>
  25#include <asm/reg.h>
  26#include <asm/page.h>
  27#include <asm/mmu.h>
  28#include <asm/pgtable.h>
  29#include <asm/cputable.h>
  30#include <asm/cache.h>
  31#include <asm/thread_info.h>
  32#include <asm/ppc_asm.h>
  33#include <asm/asm-offsets.h>
  34#include <asm/ptrace.h>
  35#include <asm/bug.h>
  36#include <asm/kvm_book3s_asm.h>
  37#include <asm/export.h>
  38
  39/* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
  40#define LOAD_BAT(n, reg, RA, RB)        \
  41        /* see the comment for clear_bats() -- Cort */ \
  42        li      RA,0;                   \
  43        mtspr   SPRN_IBAT##n##U,RA;     \
  44        mtspr   SPRN_DBAT##n##U,RA;     \
  45        lwz     RA,(n*16)+0(reg);       \
  46        lwz     RB,(n*16)+4(reg);       \
  47        mtspr   SPRN_IBAT##n##U,RA;     \
  48        mtspr   SPRN_IBAT##n##L,RB;     \
  49        beq     1f;                     \
  50        lwz     RA,(n*16)+8(reg);       \
  51        lwz     RB,(n*16)+12(reg);      \
  52        mtspr   SPRN_DBAT##n##U,RA;     \
  53        mtspr   SPRN_DBAT##n##L,RB;     \
  541:
  55
  56        __HEAD
  57        .stabs  "arch/powerpc/kernel/",N_SO,0,0,0f
  58        .stabs  "head_32.S",N_SO,0,0,0f
  590:
  60_ENTRY(_stext);
  61
  62/*
  63 * _start is defined this way because the XCOFF loader in the OpenFirmware
  64 * on the powermac expects the entry point to be a procedure descriptor.
  65 */
  66_ENTRY(_start);
  67        /*
  68         * These are here for legacy reasons, the kernel used to
  69         * need to look like a coff function entry for the pmac
  70         * but we're always started by some kind of bootloader now.
  71         *  -- Cort
  72         */
  73        nop     /* used by __secondary_hold on prep (mtx) and chrp smp */
  74        nop     /* used by __secondary_hold on prep (mtx) and chrp smp */
  75        nop
  76
  77/* PMAC
  78 * Enter here with the kernel text, data and bss loaded starting at
  79 * 0, running with virtual == physical mapping.
  80 * r5 points to the prom entry point (the client interface handler
  81 * address).  Address translation is turned on, with the prom
  82 * managing the hash table.  Interrupts are disabled.  The stack
  83 * pointer (r1) points to just below the end of the half-meg region
  84 * from 0x380000 - 0x400000, which is mapped in already.
  85 *
  86 * If we are booted from MacOS via BootX, we enter with the kernel
  87 * image loaded somewhere, and the following values in registers:
  88 *  r3: 'BooX' (0x426f6f58)
  89 *  r4: virtual address of boot_infos_t
  90 *  r5: 0
  91 *
  92 * PREP
  93 * This is jumped to on prep systems right after the kernel is relocated
  94 * to its proper place in memory by the boot loader.  The expected layout
  95 * of the regs is:
  96 *   r3: ptr to residual data
  97 *   r4: initrd_start or if no initrd then 0
  98 *   r5: initrd_end - unused if r4 is 0
  99 *   r6: Start of command line string
 100 *   r7: End of command line string
 101 *
 102 * This just gets a minimal mmu environment setup so we can call
 103 * start_here() to do the real work.
 104 * -- Cort
 105 */
 106
 107        .globl  __start
 108__start:
 109/*
 110 * We have to do any OF calls before we map ourselves to KERNELBASE,
 111 * because OF may have I/O devices mapped into that area
 112 * (particularly on CHRP).
 113 */
 114        cmpwi   0,r5,0
 115        beq     1f
 116
 117#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
 118        /* find out where we are now */
 119        bcl     20,31,$+4
 1200:      mflr    r8                      /* r8 = runtime addr here */
 121        addis   r8,r8,(_stext - 0b)@ha
 122        addi    r8,r8,(_stext - 0b)@l   /* current runtime base addr */
 123        bl      prom_init
 124#endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
 125
 126        /* We never return. We also hit that trap if trying to boot
 127         * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
 128        trap
 129
 130/*
 131 * Check for BootX signature when supporting PowerMac and branch to
 132 * appropriate trampoline if it's present
 133 */
 134#ifdef CONFIG_PPC_PMAC
 1351:      lis     r31,0x426f
 136        ori     r31,r31,0x6f58
 137        cmpw    0,r3,r31
 138        bne     1f
 139        bl      bootx_init
 140        trap
 141#endif /* CONFIG_PPC_PMAC */
 142
 1431:      mr      r31,r3                  /* save device tree ptr */
 144        li      r24,0                   /* cpu # */
 145
 146/*
 147 * early_init() does the early machine identification and does
 148 * the necessary low-level setup and clears the BSS
 149 *  -- Cort <cort@fsmlabs.com>
 150 */
 151        bl      early_init
 152
 153/* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
 154 * the physical address we are running at, returned by early_init()
 155 */
 156        bl      mmu_off
 157__after_mmu_off:
 158        bl      clear_bats
 159        bl      flush_tlbs
 160
 161        bl      initial_bats
 162#if defined(CONFIG_BOOTX_TEXT)
 163        bl      setup_disp_bat
 164#endif
 165#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
 166        bl      setup_cpm_bat
 167#endif
 168#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
 169        bl      setup_usbgecko_bat
 170#endif
 171
 172/*
 173 * Call setup_cpu for CPU 0 and initialize 6xx Idle
 174 */
 175        bl      reloc_offset
 176        li      r24,0                   /* cpu# */
 177        bl      call_setup_cpu          /* Call setup_cpu for this CPU */
 178#ifdef CONFIG_6xx
 179        bl      reloc_offset
 180        bl      init_idle_6xx
 181#endif /* CONFIG_6xx */
 182
 183
 184/*
 185 * We need to run with _start at physical address 0.
 186 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
 187 * the exception vectors at 0 (and therefore this copy
 188 * overwrites OF's exception vectors with our own).
 189 * The MMU is off at this point.
 190 */
 191        bl      reloc_offset
 192        mr      r26,r3
 193        addis   r4,r3,KERNELBASE@h      /* current address of _start */
 194        lis     r5,PHYSICAL_START@h
 195        cmplw   0,r4,r5                 /* already running at PHYSICAL_START? */
 196        bne     relocate_kernel
 197/*
 198 * we now have the 1st 16M of ram mapped with the bats.
 199 * prep needs the mmu to be turned on here, but pmac already has it on.
 200 * this shouldn't bother the pmac since it just gets turned on again
 201 * as we jump to our code at KERNELBASE. -- Cort
 202 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
 203 * off, and in other cases, we now turn it off before changing BATs above.
 204 */
 205turn_on_mmu:
 206        mfmsr   r0
 207        ori     r0,r0,MSR_DR|MSR_IR
 208        mtspr   SPRN_SRR1,r0
 209        lis     r0,start_here@h
 210        ori     r0,r0,start_here@l
 211        mtspr   SPRN_SRR0,r0
 212        SYNC
 213        RFI                             /* enables MMU */
 214
 215/*
 216 * We need __secondary_hold as a place to hold the other cpus on
 217 * an SMP machine, even when we are running a UP kernel.
 218 */
 219        . = 0xc0                        /* for prep bootloader */
 220        li      r3,1                    /* MTX only has 1 cpu */
 221        .globl  __secondary_hold
 222__secondary_hold:
 223        /* tell the master we're here */
 224        stw     r3,__secondary_hold_acknowledge@l(0)
 225#ifdef CONFIG_SMP
 226100:    lwz     r4,0(0)
 227        /* wait until we're told to start */
 228        cmpw    0,r4,r3
 229        bne     100b
 230        /* our cpu # was at addr 0 - go */
 231        mr      r24,r3                  /* cpu # */
 232        b       __secondary_start
 233#else
 234        b       .
 235#endif /* CONFIG_SMP */
 236
 237        .globl  __secondary_hold_spinloop
 238__secondary_hold_spinloop:
 239        .long   0
 240        .globl  __secondary_hold_acknowledge
 241__secondary_hold_acknowledge:
 242        .long   -1
 243
 244/*
 245 * Exception entry code.  This code runs with address translation
 246 * turned off, i.e. using physical addresses.
 247 * We assume sprg3 has the physical address of the current
 248 * task's thread_struct.
 249 */
 250#define EXCEPTION_PROLOG        \
 251        mtspr   SPRN_SPRG_SCRATCH0,r10; \
 252        mtspr   SPRN_SPRG_SCRATCH1,r11; \
 253        mfcr    r10;            \
 254        EXCEPTION_PROLOG_1;     \
 255        EXCEPTION_PROLOG_2
 256
 257#define EXCEPTION_PROLOG_1      \
 258        mfspr   r11,SPRN_SRR1;          /* check whether user or kernel */ \
 259        andi.   r11,r11,MSR_PR; \
 260        tophys(r11,r1);                 /* use tophys(r1) if kernel */ \
 261        beq     1f;             \
 262        mfspr   r11,SPRN_SPRG_THREAD;   \
 263        lwz     r11,THREAD_INFO-THREAD(r11);    \
 264        addi    r11,r11,THREAD_SIZE;    \
 265        tophys(r11,r11);        \
 2661:      subi    r11,r11,INT_FRAME_SIZE  /* alloc exc. frame */
 267
 268
 269#define EXCEPTION_PROLOG_2      \
 270        stw     r10,_CCR(r11);          /* save registers */ \
 271        stw     r12,GPR12(r11); \
 272        stw     r9,GPR9(r11);   \
 273        mfspr   r10,SPRN_SPRG_SCRATCH0; \
 274        stw     r10,GPR10(r11); \
 275        mfspr   r12,SPRN_SPRG_SCRATCH1; \
 276        stw     r12,GPR11(r11); \
 277        mflr    r10;            \
 278        stw     r10,_LINK(r11); \
 279        mfspr   r12,SPRN_SRR0;  \
 280        mfspr   r9,SPRN_SRR1;   \
 281        stw     r1,GPR1(r11);   \
 282        stw     r1,0(r11);      \
 283        tovirt(r1,r11);                 /* set new kernel sp */ \
 284        li      r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
 285        MTMSRD(r10);                    /* (except for mach check in rtas) */ \
 286        stw     r0,GPR0(r11);   \
 287        lis     r10,STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */ \
 288        addi    r10,r10,STACK_FRAME_REGS_MARKER@l; \
 289        stw     r10,8(r11);     \
 290        SAVE_4GPRS(3, r11);     \
 291        SAVE_2GPRS(7, r11)
 292
 293/*
 294 * Note: code which follows this uses cr0.eq (set if from kernel),
 295 * r11, r12 (SRR0), and r9 (SRR1).
 296 *
 297 * Note2: once we have set r1 we are in a position to take exceptions
 298 * again, and we could thus set MSR:RI at that point.
 299 */
 300
 301/*
 302 * Exception vectors.
 303 */
 304#define EXCEPTION(n, label, hdlr, xfer)         \
 305        . = n;                                  \
 306        DO_KVM n;                               \
 307label:                                          \
 308        EXCEPTION_PROLOG;                       \
 309        addi    r3,r1,STACK_FRAME_OVERHEAD;     \
 310        xfer(n, hdlr)
 311
 312#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret)     \
 313        li      r10,trap;                                       \
 314        stw     r10,_TRAP(r11);                                 \
 315        li      r10,MSR_KERNEL;                                 \
 316        copyee(r10, r9);                                        \
 317        bl      tfer;                                           \
 318i##n:                                                           \
 319        .long   hdlr;                                           \
 320        .long   ret
 321
 322#define COPY_EE(d, s)           rlwimi d,s,0,16,16
 323#define NOCOPY(d, s)
 324
 325#define EXC_XFER_STD(n, hdlr)           \
 326        EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
 327                          ret_from_except_full)
 328
 329#define EXC_XFER_LITE(n, hdlr)          \
 330        EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
 331                          ret_from_except)
 332
 333#define EXC_XFER_EE(n, hdlr)            \
 334        EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
 335                          ret_from_except_full)
 336
 337#define EXC_XFER_EE_LITE(n, hdlr)       \
 338        EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
 339                          ret_from_except)
 340
 341/* System reset */
 342/* core99 pmac starts the seconary here by changing the vector, and
 343   putting it back to what it was (unknown_exception) when done.  */
 344        EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
 345
 346/* Machine check */
 347/*
 348 * On CHRP, this is complicated by the fact that we could get a
 349 * machine check inside RTAS, and we have no guarantee that certain
 350 * critical registers will have the values we expect.  The set of
 351 * registers that might have bad values includes all the GPRs
 352 * and all the BATs.  We indicate that we are in RTAS by putting
 353 * a non-zero value, the address of the exception frame to use,
 354 * in SPRG2.  The machine check handler checks SPRG2 and uses its
 355 * value if it is non-zero.  If we ever needed to free up SPRG2,
 356 * we could use a field in the thread_info or thread_struct instead.
 357 * (Other exception handlers assume that r1 is a valid kernel stack
 358 * pointer when we take an exception from supervisor mode.)
 359 *      -- paulus.
 360 */
 361        . = 0x200
 362        DO_KVM  0x200
 363        mtspr   SPRN_SPRG_SCRATCH0,r10
 364        mtspr   SPRN_SPRG_SCRATCH1,r11
 365        mfcr    r10
 366#ifdef CONFIG_PPC_CHRP
 367        mfspr   r11,SPRN_SPRG_RTAS
 368        cmpwi   0,r11,0
 369        bne     7f
 370#endif /* CONFIG_PPC_CHRP */
 371        EXCEPTION_PROLOG_1
 3727:      EXCEPTION_PROLOG_2
 373        addi    r3,r1,STACK_FRAME_OVERHEAD
 374#ifdef CONFIG_PPC_CHRP
 375        mfspr   r4,SPRN_SPRG_RTAS
 376        cmpwi   cr1,r4,0
 377        bne     cr1,1f
 378#endif
 379        EXC_XFER_STD(0x200, machine_check_exception)
 380#ifdef CONFIG_PPC_CHRP
 3811:      b       machine_check_in_rtas
 382#endif
 383
 384/* Data access exception. */
 385        . = 0x300
 386        DO_KVM  0x300
 387DataAccess:
 388        EXCEPTION_PROLOG
 389        mfspr   r10,SPRN_DSISR
 390        stw     r10,_DSISR(r11)
 391        andis.  r0,r10,(DSISR_BAD_FAULT_32S|DSISR_DABRMATCH)@h
 392        bne     1f                      /* if not, try to put a PTE */
 393        mfspr   r4,SPRN_DAR             /* into the hash table */
 394        rlwinm  r3,r10,32-15,21,21      /* DSISR_STORE -> _PAGE_RW */
 395        bl      hash_page
 3961:      lwz     r5,_DSISR(r11)          /* get DSISR value */
 397        mfspr   r4,SPRN_DAR
 398        EXC_XFER_LITE(0x300, handle_page_fault)
 399
 400
 401/* Instruction access exception. */
 402        . = 0x400
 403        DO_KVM  0x400
 404InstructionAccess:
 405        EXCEPTION_PROLOG
 406        andis.  r0,r9,SRR1_ISI_NOPT@h   /* no pte found? */
 407        beq     1f                      /* if so, try to put a PTE */
 408        li      r3,0                    /* into the hash table */
 409        mr      r4,r12                  /* SRR0 is fault address */
 410        bl      hash_page
 4111:      mr      r4,r12
 412        andis.  r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
 413        EXC_XFER_LITE(0x400, handle_page_fault)
 414
 415/* External interrupt */
 416        EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
 417
 418/* Alignment exception */
 419        . = 0x600
 420        DO_KVM  0x600
 421Alignment:
 422        EXCEPTION_PROLOG
 423        mfspr   r4,SPRN_DAR
 424        stw     r4,_DAR(r11)
 425        mfspr   r5,SPRN_DSISR
 426        stw     r5,_DSISR(r11)
 427        addi    r3,r1,STACK_FRAME_OVERHEAD
 428        EXC_XFER_EE(0x600, alignment_exception)
 429
 430/* Program check exception */
 431        EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
 432
 433/* Floating-point unavailable */
 434        . = 0x800
 435        DO_KVM  0x800
 436FPUnavailable:
 437BEGIN_FTR_SECTION
 438/*
 439 * Certain Freescale cores don't have a FPU and treat fp instructions
 440 * as a FP Unavailable exception.  Redirect to illegal/emulation handling.
 441 */
 442        b       ProgramCheck
 443END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
 444        EXCEPTION_PROLOG
 445        beq     1f
 446        bl      load_up_fpu             /* if from user, just load it up */
 447        b       fast_exception_return
 4481:      addi    r3,r1,STACK_FRAME_OVERHEAD
 449        EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
 450
 451/* Decrementer */
 452        EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
 453
 454        EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
 455        EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
 456
 457/* System call */
 458        . = 0xc00
 459        DO_KVM  0xc00
 460SystemCall:
 461        EXCEPTION_PROLOG
 462        EXC_XFER_EE_LITE(0xc00, DoSyscall)
 463
 464/* Single step - not used on 601 */
 465        EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
 466        EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
 467
 468/*
 469 * The Altivec unavailable trap is at 0x0f20.  Foo.
 470 * We effectively remap it to 0x3000.
 471 * We include an altivec unavailable exception vector even if
 472 * not configured for Altivec, so that you can't panic a
 473 * non-altivec kernel running on a machine with altivec just
 474 * by executing an altivec instruction.
 475 */
 476        . = 0xf00
 477        DO_KVM  0xf00
 478        b       PerformanceMonitor
 479
 480        . = 0xf20
 481        DO_KVM  0xf20
 482        b       AltiVecUnavailable
 483
 484/*
 485 * Handle TLB miss for instruction on 603/603e.
 486 * Note: we get an alternate set of r0 - r3 to use automatically.
 487 */
 488        . = 0x1000
 489InstructionTLBMiss:
 490/*
 491 * r0:  scratch
 492 * r1:  linux style pte ( later becomes ppc hardware pte )
 493 * r2:  ptr to linux-style pte
 494 * r3:  scratch
 495 */
 496        /* Get PTE (linux-style) and check access */
 497        mfspr   r3,SPRN_IMISS
 498        lis     r1,PAGE_OFFSET@h                /* check if kernel address */
 499        cmplw   0,r1,r3
 500        mfspr   r2,SPRN_SPRG_THREAD
 501        li      r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
 502        lwz     r2,PGDIR(r2)
 503        bge-    112f
 504        mfspr   r2,SPRN_SRR1            /* and MSR_PR bit from SRR1 */
 505        rlwimi  r1,r2,32-12,29,29       /* shift MSR_PR to _PAGE_USER posn */
 506        lis     r2,swapper_pg_dir@ha    /* if kernel address, use */
 507        addi    r2,r2,swapper_pg_dir@l  /* kernel page table */
 508112:    tophys(r2,r2)
 509        rlwimi  r2,r3,12,20,29          /* insert top 10 bits of address */
 510        lwz     r2,0(r2)                /* get pmd entry */
 511        rlwinm. r2,r2,0,0,19            /* extract address of pte page */
 512        beq-    InstructionAddressInvalid       /* return if no mapping */
 513        rlwimi  r2,r3,22,20,29          /* insert next 10 bits of address */
 514        lwz     r0,0(r2)                /* get linux-style pte */
 515        andc.   r1,r1,r0                /* check access & ~permission */
 516        bne-    InstructionAddressInvalid /* return if access not permitted */
 517        ori     r0,r0,_PAGE_ACCESSED    /* set _PAGE_ACCESSED in pte */
 518        /*
 519         * NOTE! We are assuming this is not an SMP system, otherwise
 520         * we would need to update the pte atomically with lwarx/stwcx.
 521         */
 522        stw     r0,0(r2)                /* update PTE (accessed bit) */
 523        /* Convert linux-style PTE to low word of PPC-style PTE */
 524        rlwinm  r1,r0,32-10,31,31       /* _PAGE_RW -> PP lsb */
 525        rlwinm  r2,r0,32-7,31,31        /* _PAGE_DIRTY -> PP lsb */
 526        and     r1,r1,r2                /* writable if _RW and _DIRTY */
 527        rlwimi  r0,r0,32-1,30,30        /* _PAGE_USER -> PP msb */
 528        rlwimi  r0,r0,32-1,31,31        /* _PAGE_USER -> PP lsb */
 529        ori     r1,r1,0xe04             /* clear out reserved bits */
 530        andc    r1,r0,r1                /* PP = user? (rw&dirty? 2: 3): 0 */
 531BEGIN_FTR_SECTION
 532        rlwinm  r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
 533END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
 534        mtspr   SPRN_RPA,r1
 535        tlbli   r3
 536        mfspr   r3,SPRN_SRR1            /* Need to restore CR0 */
 537        mtcrf   0x80,r3
 538        rfi
 539InstructionAddressInvalid:
 540        mfspr   r3,SPRN_SRR1
 541        rlwinm  r1,r3,9,6,6     /* Get load/store bit */
 542
 543        addis   r1,r1,0x2000
 544        mtspr   SPRN_DSISR,r1   /* (shouldn't be needed) */
 545        andi.   r2,r3,0xFFFF    /* Clear upper bits of SRR1 */
 546        or      r2,r2,r1
 547        mtspr   SPRN_SRR1,r2
 548        mfspr   r1,SPRN_IMISS   /* Get failing address */
 549        rlwinm. r2,r2,0,31,31   /* Check for little endian access */
 550        rlwimi  r2,r2,1,30,30   /* change 1 -> 3 */
 551        xor     r1,r1,r2
 552        mtspr   SPRN_DAR,r1     /* Set fault address */
 553        mfmsr   r0              /* Restore "normal" registers */
 554        xoris   r0,r0,MSR_TGPR>>16
 555        mtcrf   0x80,r3         /* Restore CR0 */
 556        mtmsr   r0
 557        b       InstructionAccess
 558
 559/*
 560 * Handle TLB miss for DATA Load operation on 603/603e
 561 */
 562        . = 0x1100
 563DataLoadTLBMiss:
 564/*
 565 * r0:  scratch
 566 * r1:  linux style pte ( later becomes ppc hardware pte )
 567 * r2:  ptr to linux-style pte
 568 * r3:  scratch
 569 */
 570        /* Get PTE (linux-style) and check access */
 571        mfspr   r3,SPRN_DMISS
 572        lis     r1,PAGE_OFFSET@h                /* check if kernel address */
 573        cmplw   0,r1,r3
 574        mfspr   r2,SPRN_SPRG_THREAD
 575        li      r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
 576        lwz     r2,PGDIR(r2)
 577        bge-    112f
 578        mfspr   r2,SPRN_SRR1            /* and MSR_PR bit from SRR1 */
 579        rlwimi  r1,r2,32-12,29,29       /* shift MSR_PR to _PAGE_USER posn */
 580        lis     r2,swapper_pg_dir@ha    /* if kernel address, use */
 581        addi    r2,r2,swapper_pg_dir@l  /* kernel page table */
 582112:    tophys(r2,r2)
 583        rlwimi  r2,r3,12,20,29          /* insert top 10 bits of address */
 584        lwz     r2,0(r2)                /* get pmd entry */
 585        rlwinm. r2,r2,0,0,19            /* extract address of pte page */
 586        beq-    DataAddressInvalid      /* return if no mapping */
 587        rlwimi  r2,r3,22,20,29          /* insert next 10 bits of address */
 588        lwz     r0,0(r2)                /* get linux-style pte */
 589        andc.   r1,r1,r0                /* check access & ~permission */
 590        bne-    DataAddressInvalid      /* return if access not permitted */
 591        ori     r0,r0,_PAGE_ACCESSED    /* set _PAGE_ACCESSED in pte */
 592        /*
 593         * NOTE! We are assuming this is not an SMP system, otherwise
 594         * we would need to update the pte atomically with lwarx/stwcx.
 595         */
 596        stw     r0,0(r2)                /* update PTE (accessed bit) */
 597        /* Convert linux-style PTE to low word of PPC-style PTE */
 598        rlwinm  r1,r0,32-10,31,31       /* _PAGE_RW -> PP lsb */
 599        rlwinm  r2,r0,32-7,31,31        /* _PAGE_DIRTY -> PP lsb */
 600        and     r1,r1,r2                /* writable if _RW and _DIRTY */
 601        rlwimi  r0,r0,32-1,30,30        /* _PAGE_USER -> PP msb */
 602        rlwimi  r0,r0,32-1,31,31        /* _PAGE_USER -> PP lsb */
 603        ori     r1,r1,0xe04             /* clear out reserved bits */
 604        andc    r1,r0,r1                /* PP = user? (rw&dirty? 2: 3): 0 */
 605BEGIN_FTR_SECTION
 606        rlwinm  r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
 607END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
 608        mtspr   SPRN_RPA,r1
 609        mfspr   r2,SPRN_SRR1            /* Need to restore CR0 */
 610        mtcrf   0x80,r2
 611BEGIN_MMU_FTR_SECTION
 612        li      r0,1
 613        mfspr   r1,SPRN_SPRG_603_LRU
 614        rlwinm  r2,r3,20,27,31          /* Get Address bits 15:19 */
 615        slw     r0,r0,r2
 616        xor     r1,r0,r1
 617        srw     r0,r1,r2
 618        mtspr   SPRN_SPRG_603_LRU,r1
 619        mfspr   r2,SPRN_SRR1
 620        rlwimi  r2,r0,31-14,14,14
 621        mtspr   SPRN_SRR1,r2
 622END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
 623        tlbld   r3
 624        rfi
 625DataAddressInvalid:
 626        mfspr   r3,SPRN_SRR1
 627        rlwinm  r1,r3,9,6,6     /* Get load/store bit */
 628        addis   r1,r1,0x2000
 629        mtspr   SPRN_DSISR,r1
 630        andi.   r2,r3,0xFFFF    /* Clear upper bits of SRR1 */
 631        mtspr   SPRN_SRR1,r2
 632        mfspr   r1,SPRN_DMISS   /* Get failing address */
 633        rlwinm. r2,r2,0,31,31   /* Check for little endian access */
 634        beq     20f             /* Jump if big endian */
 635        xori    r1,r1,3
 63620:     mtspr   SPRN_DAR,r1     /* Set fault address */
 637        mfmsr   r0              /* Restore "normal" registers */
 638        xoris   r0,r0,MSR_TGPR>>16
 639        mtcrf   0x80,r3         /* Restore CR0 */
 640        mtmsr   r0
 641        b       DataAccess
 642
 643/*
 644 * Handle TLB miss for DATA Store on 603/603e
 645 */
 646        . = 0x1200
 647DataStoreTLBMiss:
 648/*
 649 * r0:  scratch
 650 * r1:  linux style pte ( later becomes ppc hardware pte )
 651 * r2:  ptr to linux-style pte
 652 * r3:  scratch
 653 */
 654        /* Get PTE (linux-style) and check access */
 655        mfspr   r3,SPRN_DMISS
 656        lis     r1,PAGE_OFFSET@h                /* check if kernel address */
 657        cmplw   0,r1,r3
 658        mfspr   r2,SPRN_SPRG_THREAD
 659        li      r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
 660        lwz     r2,PGDIR(r2)
 661        bge-    112f
 662        mfspr   r2,SPRN_SRR1            /* and MSR_PR bit from SRR1 */
 663        rlwimi  r1,r2,32-12,29,29       /* shift MSR_PR to _PAGE_USER posn */
 664        lis     r2,swapper_pg_dir@ha    /* if kernel address, use */
 665        addi    r2,r2,swapper_pg_dir@l  /* kernel page table */
 666112:    tophys(r2,r2)
 667        rlwimi  r2,r3,12,20,29          /* insert top 10 bits of address */
 668        lwz     r2,0(r2)                /* get pmd entry */
 669        rlwinm. r2,r2,0,0,19            /* extract address of pte page */
 670        beq-    DataAddressInvalid      /* return if no mapping */
 671        rlwimi  r2,r3,22,20,29          /* insert next 10 bits of address */
 672        lwz     r0,0(r2)                /* get linux-style pte */
 673        andc.   r1,r1,r0                /* check access & ~permission */
 674        bne-    DataAddressInvalid      /* return if access not permitted */
 675        ori     r0,r0,_PAGE_ACCESSED|_PAGE_DIRTY
 676        /*
 677         * NOTE! We are assuming this is not an SMP system, otherwise
 678         * we would need to update the pte atomically with lwarx/stwcx.
 679         */
 680        stw     r0,0(r2)                /* update PTE (accessed/dirty bits) */
 681        /* Convert linux-style PTE to low word of PPC-style PTE */
 682        rlwimi  r0,r0,32-1,30,30        /* _PAGE_USER -> PP msb */
 683        li      r1,0xe05                /* clear out reserved bits & PP lsb */
 684        andc    r1,r0,r1                /* PP = user? 2: 0 */
 685BEGIN_FTR_SECTION
 686        rlwinm  r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
 687END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
 688        mtspr   SPRN_RPA,r1
 689        mfspr   r2,SPRN_SRR1            /* Need to restore CR0 */
 690        mtcrf   0x80,r2
 691BEGIN_MMU_FTR_SECTION
 692        li      r0,1
 693        mfspr   r1,SPRN_SPRG_603_LRU
 694        rlwinm  r2,r3,20,27,31          /* Get Address bits 15:19 */
 695        slw     r0,r0,r2
 696        xor     r1,r0,r1
 697        srw     r0,r1,r2
 698        mtspr   SPRN_SPRG_603_LRU,r1
 699        mfspr   r2,SPRN_SRR1
 700        rlwimi  r2,r0,31-14,14,14
 701        mtspr   SPRN_SRR1,r2
 702END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
 703        tlbld   r3
 704        rfi
 705
 706#ifndef CONFIG_ALTIVEC
 707#define altivec_assist_exception        unknown_exception
 708#endif
 709
 710        EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
 711        EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
 712        EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
 713        EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
 714        EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
 715        EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
 716        EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
 717        EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
 718        EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
 719        EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
 720        EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
 721        EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
 722        EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
 723        EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
 724        EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
 725        EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
 726        EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
 727        EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
 728        EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
 729        EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
 730        EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
 731        EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
 732        EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
 733        EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
 734        EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
 735        EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
 736        EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
 737        EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
 738        EXCEPTION(0x2f00, Trap_2f, unknown_exception, EXC_XFER_EE)
 739
 740        . = 0x3000
 741
 742AltiVecUnavailable:
 743        EXCEPTION_PROLOG
 744#ifdef CONFIG_ALTIVEC
 745        beq     1f
 746        bl      load_up_altivec         /* if from user, just load it up */
 747        b       fast_exception_return
 748#endif /* CONFIG_ALTIVEC */
 7491:      addi    r3,r1,STACK_FRAME_OVERHEAD
 750        EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
 751
 752PerformanceMonitor:
 753        EXCEPTION_PROLOG
 754        addi    r3,r1,STACK_FRAME_OVERHEAD
 755        EXC_XFER_STD(0xf00, performance_monitor_exception)
 756
 757
 758/*
 759 * This code is jumped to from the startup code to copy
 760 * the kernel image to physical address PHYSICAL_START.
 761 */
 762relocate_kernel:
 763        addis   r9,r26,klimit@ha        /* fetch klimit */
 764        lwz     r25,klimit@l(r9)
 765        addis   r25,r25,-KERNELBASE@h
 766        lis     r3,PHYSICAL_START@h     /* Destination base address */
 767        li      r6,0                    /* Destination offset */
 768        li      r5,0x4000               /* # bytes of memory to copy */
 769        bl      copy_and_flush          /* copy the first 0x4000 bytes */
 770        addi    r0,r3,4f@l              /* jump to the address of 4f */
 771        mtctr   r0                      /* in copy and do the rest. */
 772        bctr                            /* jump to the copy */
 7734:      mr      r5,r25
 774        bl      copy_and_flush          /* copy the rest */
 775        b       turn_on_mmu
 776
 777/*
 778 * Copy routine used to copy the kernel to start at physical address 0
 779 * and flush and invalidate the caches as needed.
 780 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
 781 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
 782 */
 783_ENTRY(copy_and_flush)
 784        addi    r5,r5,-4
 785        addi    r6,r6,-4
 7864:      li      r0,L1_CACHE_BYTES/4
 787        mtctr   r0
 7883:      addi    r6,r6,4                 /* copy a cache line */
 789        lwzx    r0,r6,r4
 790        stwx    r0,r6,r3
 791        bdnz    3b
 792        dcbst   r6,r3                   /* write it to memory */
 793        sync
 794        icbi    r6,r3                   /* flush the icache line */
 795        cmplw   0,r6,r5
 796        blt     4b
 797        sync                            /* additional sync needed on g4 */
 798        isync
 799        addi    r5,r5,4
 800        addi    r6,r6,4
 801        blr
 802
 803#ifdef CONFIG_SMP
 804        .globl __secondary_start_mpc86xx
 805__secondary_start_mpc86xx:
 806        mfspr   r3, SPRN_PIR
 807        stw     r3, __secondary_hold_acknowledge@l(0)
 808        mr      r24, r3                 /* cpu # */
 809        b       __secondary_start
 810
 811        .globl  __secondary_start_pmac_0
 812__secondary_start_pmac_0:
 813        /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
 814        li      r24,0
 815        b       1f
 816        li      r24,1
 817        b       1f
 818        li      r24,2
 819        b       1f
 820        li      r24,3
 8211:
 822        /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
 823           set to map the 0xf0000000 - 0xffffffff region */
 824        mfmsr   r0
 825        rlwinm  r0,r0,0,28,26           /* clear DR (0x10) */
 826        SYNC
 827        mtmsr   r0
 828        isync
 829
 830        .globl  __secondary_start
 831__secondary_start:
 832        /* Copy some CPU settings from CPU 0 */
 833        bl      __restore_cpu_setup
 834
 835        lis     r3,-KERNELBASE@h
 836        mr      r4,r24
 837        bl      call_setup_cpu          /* Call setup_cpu for this CPU */
 838#ifdef CONFIG_6xx
 839        lis     r3,-KERNELBASE@h
 840        bl      init_idle_6xx
 841#endif /* CONFIG_6xx */
 842
 843        /* get current_thread_info and current */
 844        lis     r1,secondary_ti@ha
 845        tophys(r1,r1)
 846        lwz     r1,secondary_ti@l(r1)
 847        tophys(r2,r1)
 848        lwz     r2,TI_TASK(r2)
 849
 850        /* stack */
 851        addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
 852        li      r0,0
 853        tophys(r3,r1)
 854        stw     r0,0(r3)
 855
 856        /* load up the MMU */
 857        bl      load_up_mmu
 858
 859        /* ptr to phys current thread */
 860        tophys(r4,r2)
 861        addi    r4,r4,THREAD    /* phys address of our thread_struct */
 862        mtspr   SPRN_SPRG_THREAD,r4
 863        li      r3,0
 864        mtspr   SPRN_SPRG_RTAS,r3       /* 0 => not in RTAS */
 865
 866        /* enable MMU and jump to start_secondary */
 867        li      r4,MSR_KERNEL
 868        lis     r3,start_secondary@h
 869        ori     r3,r3,start_secondary@l
 870        mtspr   SPRN_SRR0,r3
 871        mtspr   SPRN_SRR1,r4
 872        SYNC
 873        RFI
 874#endif /* CONFIG_SMP */
 875
 876#ifdef CONFIG_KVM_BOOK3S_HANDLER
 877#include "../kvm/book3s_rmhandlers.S"
 878#endif
 879
 880/*
 881 * Those generic dummy functions are kept for CPUs not
 882 * included in CONFIG_6xx
 883 */
 884#if !defined(CONFIG_6xx)
 885_ENTRY(__save_cpu_setup)
 886        blr
 887_ENTRY(__restore_cpu_setup)
 888        blr
 889#endif /* !defined(CONFIG_6xx) */
 890
 891
 892/*
 893 * Load stuff into the MMU.  Intended to be called with
 894 * IR=0 and DR=0.
 895 */
 896load_up_mmu:
 897        sync                    /* Force all PTE updates to finish */
 898        isync
 899        tlbia                   /* Clear all TLB entries */
 900        sync                    /* wait for tlbia/tlbie to finish */
 901        TLBSYNC                 /* ... on all CPUs */
 902        /* Load the SDR1 register (hash table base & size) */
 903        lis     r6,_SDR1@ha
 904        tophys(r6,r6)
 905        lwz     r6,_SDR1@l(r6)
 906        mtspr   SPRN_SDR1,r6
 907        li      r0,16           /* load up segment register values */
 908        mtctr   r0              /* for context 0 */
 909        lis     r3,0x2000       /* Ku = 1, VSID = 0 */
 910        li      r4,0
 9113:      mtsrin  r3,r4
 912        addi    r3,r3,0x111     /* increment VSID */
 913        addis   r4,r4,0x1000    /* address of next segment */
 914        bdnz    3b
 915
 916/* Load the BAT registers with the values set up by MMU_init.
 917   MMU_init takes care of whether we're on a 601 or not. */
 918        mfpvr   r3
 919        srwi    r3,r3,16
 920        cmpwi   r3,1
 921        lis     r3,BATS@ha
 922        addi    r3,r3,BATS@l
 923        tophys(r3,r3)
 924        LOAD_BAT(0,r3,r4,r5)
 925        LOAD_BAT(1,r3,r4,r5)
 926        LOAD_BAT(2,r3,r4,r5)
 927        LOAD_BAT(3,r3,r4,r5)
 928BEGIN_MMU_FTR_SECTION
 929        LOAD_BAT(4,r3,r4,r5)
 930        LOAD_BAT(5,r3,r4,r5)
 931        LOAD_BAT(6,r3,r4,r5)
 932        LOAD_BAT(7,r3,r4,r5)
 933END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
 934        blr
 935
 936/*
 937 * This is where the main kernel code starts.
 938 */
 939start_here:
 940        /* ptr to current */
 941        lis     r2,init_task@h
 942        ori     r2,r2,init_task@l
 943        /* Set up for using our exception vectors */
 944        /* ptr to phys current thread */
 945        tophys(r4,r2)
 946        addi    r4,r4,THREAD    /* init task's THREAD */
 947        mtspr   SPRN_SPRG_THREAD,r4
 948        li      r3,0
 949        mtspr   SPRN_SPRG_RTAS,r3       /* 0 => not in RTAS */
 950
 951        /* stack */
 952        lis     r1,init_thread_union@ha
 953        addi    r1,r1,init_thread_union@l
 954        li      r0,0
 955        stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 956/*
 957 * Do early platform-specific initialization,
 958 * and set up the MMU.
 959 */
 960        li      r3,0
 961        mr      r4,r31
 962        bl      machine_init
 963        bl      __save_cpu_setup
 964        bl      MMU_init
 965
 966/*
 967 * Go back to running unmapped so we can load up new values
 968 * for SDR1 (hash table pointer) and the segment registers
 969 * and change to using our exception vectors.
 970 */
 971        lis     r4,2f@h
 972        ori     r4,r4,2f@l
 973        tophys(r4,r4)
 974        li      r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
 975        mtspr   SPRN_SRR0,r4
 976        mtspr   SPRN_SRR1,r3
 977        SYNC
 978        RFI
 979/* Load up the kernel context */
 9802:      bl      load_up_mmu
 981
 982#ifdef CONFIG_BDI_SWITCH
 983        /* Add helper information for the Abatron bdiGDB debugger.
 984         * We do this here because we know the mmu is disabled, and
 985         * will be enabled for real in just a few instructions.
 986         */
 987        lis     r5, abatron_pteptrs@h
 988        ori     r5, r5, abatron_pteptrs@l
 989        stw     r5, 0xf0(r0)    /* This much match your Abatron config */
 990        lis     r6, swapper_pg_dir@h
 991        ori     r6, r6, swapper_pg_dir@l
 992        tophys(r5, r5)
 993        stw     r6, 0(r5)
 994#endif /* CONFIG_BDI_SWITCH */
 995
 996/* Now turn on the MMU for real! */
 997        li      r4,MSR_KERNEL
 998        lis     r3,start_kernel@h
 999        ori     r3,r3,start_kernel@l
1000        mtspr   SPRN_SRR0,r3

1001        mtspr   SPRN_SRR1,r4
1002        SYNC
1003        RFI
1004
1005/*
1006 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1007 *
1008 * Set up the segment registers for a new context.
1009 */
1010_ENTRY(switch_mmu_context)
1011        lwz     r3,MMCONTEXTID(r4)
1012        cmpwi   cr0,r3,0
1013        blt-    4f
1014        mulli   r3,r3,897       /* multiply context by skew factor */
1015        rlwinm  r3,r3,4,8,27    /* VSID = (context & 0xfffff) << 4 */
1016        addis   r3,r3,0x6000    /* Set Ks, Ku bits */
1017        li      r0,NUM_USER_SEGMENTS
1018        mtctr   r0
1019
1020#ifdef CONFIG_BDI_SWITCH
1021        /* Context switch the PTE pointer for the Abatron BDI2000.
1022         * The PGDIR is passed as second argument.
1023         */
1024        lwz     r4,MM_PGD(r4)
1025        lis     r5, KERNELBASE@h
1026        lwz     r5, 0xf0(r5)
1027        stw     r4, 0x4(r5)
1028#endif
1029        li      r4,0
1030        isync
10313:
1032        mtsrin  r3,r4
1033        addi    r3,r3,0x111     /* next VSID */
1034        rlwinm  r3,r3,0,8,3     /* clear out any overflow from VSID field */
1035        addis   r4,r4,0x1000    /* address of next segment */
1036        bdnz    3b
1037        sync
1038        isync
1039        blr
10404:      trap
1041        EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1042        blr
1043EXPORT_SYMBOL(switch_mmu_context)
1044
1045/*
1046 * An undocumented "feature" of 604e requires that the v bit
1047 * be cleared before changing BAT values.
1048 *
1049 * Also, newer IBM firmware does not clear bat3 and 4 so
1050 * this makes sure it's done.
1051 *  -- Cort
1052 */
1053clear_bats:
1054        li      r10,0
1055        mfspr   r9,SPRN_PVR
1056        rlwinm  r9,r9,16,16,31          /* r9 = 1 for 601, 4 for 604 */
1057        cmpwi   r9, 1
1058        beq     1f
1059
1060        mtspr   SPRN_DBAT0U,r10
1061        mtspr   SPRN_DBAT0L,r10
1062        mtspr   SPRN_DBAT1U,r10
1063        mtspr   SPRN_DBAT1L,r10
1064        mtspr   SPRN_DBAT2U,r10
1065        mtspr   SPRN_DBAT2L,r10
1066        mtspr   SPRN_DBAT3U,r10
1067        mtspr   SPRN_DBAT3L,r10
10681:
1069        mtspr   SPRN_IBAT0U,r10
1070        mtspr   SPRN_IBAT0L,r10
1071        mtspr   SPRN_IBAT1U,r10
1072        mtspr   SPRN_IBAT1L,r10
1073        mtspr   SPRN_IBAT2U,r10
1074        mtspr   SPRN_IBAT2L,r10
1075        mtspr   SPRN_IBAT3U,r10
1076        mtspr   SPRN_IBAT3L,r10
1077BEGIN_MMU_FTR_SECTION
1078        /* Here's a tweak: at this point, CPU setup have
1079         * not been called yet, so HIGH_BAT_EN may not be
1080         * set in HID0 for the 745x processors. However, it
1081         * seems that doesn't affect our ability to actually
1082         * write to these SPRs.
1083         */
1084        mtspr   SPRN_DBAT4U,r10
1085        mtspr   SPRN_DBAT4L,r10
1086        mtspr   SPRN_DBAT5U,r10
1087        mtspr   SPRN_DBAT5L,r10
1088        mtspr   SPRN_DBAT6U,r10
1089        mtspr   SPRN_DBAT6L,r10
1090        mtspr   SPRN_DBAT7U,r10
1091        mtspr   SPRN_DBAT7L,r10
1092        mtspr   SPRN_IBAT4U,r10
1093        mtspr   SPRN_IBAT4L,r10
1094        mtspr   SPRN_IBAT5U,r10
1095        mtspr   SPRN_IBAT5L,r10
1096        mtspr   SPRN_IBAT6U,r10
1097        mtspr   SPRN_IBAT6L,r10
1098        mtspr   SPRN_IBAT7U,r10
1099        mtspr   SPRN_IBAT7L,r10
1100END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1101        blr
1102
1103flush_tlbs:
1104        lis     r10, 0x40
11051:      addic.  r10, r10, -0x1000
1106        tlbie   r10
1107        bgt     1b
1108        sync
1109        blr
1110
1111mmu_off:
1112        addi    r4, r3, __after_mmu_off - _start
1113        mfmsr   r3
1114        andi.   r0,r3,MSR_DR|MSR_IR             /* MMU enabled? */
1115        beqlr
1116        andc    r3,r3,r0
1117        mtspr   SPRN_SRR0,r4
1118        mtspr   SPRN_SRR1,r3
1119        sync
1120        RFI
1121
1122/*
1123 * On 601, we use 3 BATs to map up to 24M of RAM at _PAGE_OFFSET
1124 * (we keep one for debugging) and on others, we use one 256M BAT.
1125 */
1126initial_bats:
1127        lis     r11,PAGE_OFFSET@h
1128        mfspr   r9,SPRN_PVR
1129        rlwinm  r9,r9,16,16,31          /* r9 = 1 for 601, 4 for 604 */
1130        cmpwi   0,r9,1
1131        bne     4f
1132        ori     r11,r11,4               /* set up BAT registers for 601 */
1133        li      r8,0x7f                 /* valid, block length = 8MB */
1134        mtspr   SPRN_IBAT0U,r11         /* N.B. 601 has valid bit in */
1135        mtspr   SPRN_IBAT0L,r8          /* lower BAT register */
1136        addis   r11,r11,0x800000@h
1137        addis   r8,r8,0x800000@h
1138        mtspr   SPRN_IBAT1U,r11
1139        mtspr   SPRN_IBAT1L,r8
1140        addis   r11,r11,0x800000@h
1141        addis   r8,r8,0x800000@h
1142        mtspr   SPRN_IBAT2U,r11
1143        mtspr   SPRN_IBAT2L,r8
1144        isync
1145        blr
1146
11474:      tophys(r8,r11)
1148#ifdef CONFIG_SMP
1149        ori     r8,r8,0x12              /* R/W access, M=1 */
1150#else
1151        ori     r8,r8,2                 /* R/W access */
1152#endif /* CONFIG_SMP */
1153        ori     r11,r11,BL_256M<<2|0x2  /* set up BAT registers for 604 */
1154
1155        mtspr   SPRN_DBAT0L,r8          /* N.B. 6xx (not 601) have valid */
1156        mtspr   SPRN_DBAT0U,r11         /* bit in upper BAT register */
1157        mtspr   SPRN_IBAT0L,r8
1158        mtspr   SPRN_IBAT0U,r11
1159        isync
1160        blr
1161
1162
1163#ifdef CONFIG_BOOTX_TEXT
1164setup_disp_bat:
1165        /*
1166         * setup the display bat prepared for us in prom.c
1167         */
1168        mflr    r8
1169        bl      reloc_offset
1170        mtlr    r8
1171        addis   r8,r3,disp_BAT@ha
1172        addi    r8,r8,disp_BAT@l
1173        cmpwi   cr0,r8,0
1174        beqlr
1175        lwz     r11,0(r8)
1176        lwz     r8,4(r8)
1177        mfspr   r9,SPRN_PVR
1178        rlwinm  r9,r9,16,16,31          /* r9 = 1 for 601, 4 for 604 */
1179        cmpwi   0,r9,1
1180        beq     1f
1181        mtspr   SPRN_DBAT3L,r8
1182        mtspr   SPRN_DBAT3U,r11
1183        blr
11841:      mtspr   SPRN_IBAT3L,r8
1185        mtspr   SPRN_IBAT3U,r11
1186        blr
1187#endif /* CONFIG_BOOTX_TEXT */
1188
1189#ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1190setup_cpm_bat:
1191        lis     r8, 0xf000
1192        ori     r8, r8, 0x002a
1193        mtspr   SPRN_DBAT1L, r8
1194
1195        lis     r11, 0xf000
1196        ori     r11, r11, (BL_1M << 2) | 2
1197        mtspr   SPRN_DBAT1U, r11
1198
1199        blr
1200#endif
1201
1202#ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1203setup_usbgecko_bat:
1204        /* prepare a BAT for early io */
1205#if defined(CONFIG_GAMECUBE)
1206        lis     r8, 0x0c00
1207#elif defined(CONFIG_WII)
1208        lis     r8, 0x0d00
1209#else
1210#error Invalid platform for USB Gecko based early debugging.
1211#endif
1212        /*
1213         * The virtual address used must match the virtual address
1214         * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1215         */
1216        lis     r11, 0xfffe     /* top 128K */
1217        ori     r8, r8, 0x002a  /* uncached, guarded ,rw */
1218        ori     r11, r11, 0x2   /* 128K, Vs=1, Vp=0 */
1219        mtspr   SPRN_DBAT1L, r8
1220        mtspr   SPRN_DBAT1U, r11
1221        blr
1222#endif
1223
1224#ifdef CONFIG_8260
1225/* Jump into the system reset for the rom.
1226 * We first disable the MMU, and then jump to the ROM reset address.
1227 *
1228 * r3 is the board info structure, r4 is the location for starting.
1229 * I use this for building a small kernel that can load other kernels,
1230 * rather than trying to write or rely on a rom monitor that can tftp load.
1231 */
1232       .globl  m8260_gorom
1233m8260_gorom:
1234        mfmsr   r0
1235        rlwinm  r0,r0,0,17,15   /* clear MSR_EE in r0 */
1236        sync
1237        mtmsr   r0
1238        sync
1239        mfspr   r11, SPRN_HID0
1240        lis     r10, 0
1241        ori     r10,r10,HID0_ICE|HID0_DCE
1242        andc    r11, r11, r10
1243        mtspr   SPRN_HID0, r11
1244        isync
1245        li      r5, MSR_ME|MSR_RI
1246        lis     r6,2f@h
1247        addis   r6,r6,-KERNELBASE@h
1248        ori     r6,r6,2f@l
1249        mtspr   SPRN_SRR0,r6
1250        mtspr   SPRN_SRR1,r5
1251        isync
1252        sync
1253        rfi
12542:
1255        mtlr    r4
1256        blr
1257#endif
1258
1259
1260/*
1261 * We put a few things here that have to be page-aligned.
1262 * This stuff goes at the beginning of the data segment,
1263 * which is page-aligned.
1264 */
1265        .data
1266        .globl  sdata
1267sdata:
1268        .globl  empty_zero_page
1269empty_zero_page:
1270        .space  4096
1271EXPORT_SYMBOL(empty_zero_page)
1272
1273        .globl  swapper_pg_dir
1274swapper_pg_dir:
1275        .space  PGD_TABLE_SIZE
1276
1277/* Room for two PTE pointers, usually the kernel and current user pointers
1278 * to their respective root page table.
1279 */
1280abatron_pteptrs:
1281        .space  8
1282