LXR linux/arch/powerpc/kernel/head

   1/*
   2 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   3 *      Initial PowerPC version.
   4 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   5 *      Rewritten for PReP
   6 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   7 *      Low-level exception handers, MMU support, and rewrite.
   8 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
   9 *      PowerPC 8xx modifications.
  10 *    Copyright (c) 1998-1999 TiVo, Inc.
  11 *      PowerPC 403GCX modifications.
  12 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  13 *      PowerPC 403GCX/405GP modifications.
  14 *    Copyright 2000 MontaVista Software Inc.
  15 *      PPC405 modifications
  16 *      PowerPC 403GCX/405GP modifications.
  17 *      Author: MontaVista Software, Inc.
  18 *              frank_rowand@mvista.com or source@mvista.com
  19 *              debbie_chu@mvista.com
  20 *
  21 *
  22 *    Module name: head_4xx.S
  23 *
  24 *    Description:
  25 *      Kernel execution entry point code.
  26 *
  27 *    This program is free software; you can redistribute it and/or
  28 *    modify it under the terms of the GNU General Public License
  29 *    as published by the Free Software Foundation; either version
  30 *    2 of the License, or (at your option) any later version.
  31 *
  32 */
  33
  34#include <linux/init.h>
  35#include <asm/processor.h>
  36#include <asm/page.h>
  37#include <asm/mmu.h>
  38#include <asm/pgtable.h>
  39#include <asm/cputable.h>
  40#include <asm/thread_info.h>
  41#include <asm/ppc_asm.h>
  42#include <asm/asm-offsets.h>
  43#include <asm/ptrace.h>
  44#include <asm/export.h>
  45
  46/* As with the other PowerPC ports, it is expected that when code
  47 * execution begins here, the following registers contain valid, yet
  48 * optional, information:
  49 *
  50 *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  51 *   r4 - Starting address of the init RAM disk
  52 *   r5 - Ending address of the init RAM disk
  53 *   r6 - Start of kernel command line string (e.g. "mem=96m")
  54 *   r7 - End of kernel command line string
  55 *
  56 * This is all going to change RSN when we add bi_recs.......  -- Dan
  57 */
  58        __HEAD
  59_ENTRY(_stext);
  60_ENTRY(_start);
  61
  62        mr      r31,r3                  /* save device tree ptr */
  63
  64        /* We have to turn on the MMU right away so we get cache modes
  65         * set correctly.
  66         */
  67        bl      initial_mmu
  68
  69/* We now have the lower 16 Meg mapped into TLB entries, and the caches
  70 * ready to work.
  71 */
  72turn_on_mmu:
  73        lis     r0,MSR_KERNEL@h
  74        ori     r0,r0,MSR_KERNEL@l
  75        mtspr   SPRN_SRR1,r0
  76        lis     r0,start_here@h
  77        ori     r0,r0,start_here@l
  78        mtspr   SPRN_SRR0,r0
  79        SYNC
  80        rfi                             /* enables MMU */
  81        b       .                       /* prevent prefetch past rfi */
  82
  83/*
  84 * This area is used for temporarily saving registers during the
  85 * critical exception prolog.
  86 */
  87        . = 0xc0
  88crit_save:
  89_ENTRY(crit_r10)
  90        .space  4
  91_ENTRY(crit_r11)
  92        .space  4
  93_ENTRY(crit_srr0)
  94        .space  4
  95_ENTRY(crit_srr1)
  96        .space  4
  97_ENTRY(saved_ksp_limit)
  98        .space  4
  99
 100/*
 101 * Exception vector entry code. This code runs with address translation
 102 * turned off (i.e. using physical addresses). We assume SPRG_THREAD has
 103 * the physical address of the current task thread_struct.
 104 * Note that we have to have decremented r1 before we write to any fields
 105 * of the exception frame, since a critical interrupt could occur at any
 106 * time, and it will write to the area immediately below the current r1.
 107 */
 108#define NORMAL_EXCEPTION_PROLOG                                              \
 109        mtspr   SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\
 110        mtspr   SPRN_SPRG_SCRATCH1,r11;                                      \
 111        mtspr   SPRN_SPRG_SCRATCH2,r1;                                       \
 112        mfcr    r10;                    /* save CR in r10 for now          */\
 113        mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
 114        andi.   r11,r11,MSR_PR;                                              \
 115        beq     1f;                                                          \
 116        mfspr   r1,SPRN_SPRG_THREAD;    /* if from user, start at top of   */\
 117        lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
 118        addi    r1,r1,THREAD_SIZE;                                           \
 1191:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
 120        tophys(r11,r1);                                                      \
 121        stw     r10,_CCR(r11);          /* save various registers          */\
 122        stw     r12,GPR12(r11);                                              \
 123        stw     r9,GPR9(r11);                                                \
 124        mfspr   r10,SPRN_SPRG_SCRATCH0;                                      \
 125        stw     r10,GPR10(r11);                                              \
 126        mfspr   r12,SPRN_SPRG_SCRATCH1;                                      \
 127        stw     r12,GPR11(r11);                                              \
 128        mflr    r10;                                                         \
 129        stw     r10,_LINK(r11);                                              \
 130        mfspr   r10,SPRN_SPRG_SCRATCH2;                                      \
 131        mfspr   r12,SPRN_SRR0;                                               \
 132        stw     r10,GPR1(r11);                                               \
 133        mfspr   r9,SPRN_SRR1;                                                \
 134        stw     r10,0(r11);                                                  \
 135        rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 136        stw     r0,GPR0(r11);                                                \
 137        SAVE_4GPRS(3, r11);                                                  \
 138        SAVE_2GPRS(7, r11)
 139
 140/*
 141 * Exception prolog for critical exceptions.  This is a little different
 142 * from the normal exception prolog above since a critical exception
 143 * can potentially occur at any point during normal exception processing.
 144 * Thus we cannot use the same SPRG registers as the normal prolog above.
 145 * Instead we use a couple of words of memory at low physical addresses.
 146 * This is OK since we don't support SMP on these processors.
 147 */
 148#define CRITICAL_EXCEPTION_PROLOG                                            \
 149        stw     r10,crit_r10@l(0);      /* save two registers to work with */\
 150        stw     r11,crit_r11@l(0);                                           \
 151        mfcr    r10;                    /* save CR in r10 for now          */\
 152        mfspr   r11,SPRN_SRR3;          /* check whether user or kernel    */\
 153        andi.   r11,r11,MSR_PR;                                              \
 154        lis     r11,critirq_ctx@ha;                                          \
 155        tophys(r11,r11);                                                     \
 156        lwz     r11,critirq_ctx@l(r11);                                      \
 157        beq     1f;                                                          \
 158        /* COMING FROM USER MODE */                                          \
 159        mfspr   r11,SPRN_SPRG_THREAD;   /* if from user, start at top of   */\
 160        lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
 1611:      addi    r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm  */\
 162        tophys(r11,r11);                                                     \
 163        stw     r10,_CCR(r11);          /* save various registers          */\
 164        stw     r12,GPR12(r11);                                              \
 165        stw     r9,GPR9(r11);                                                \
 166        mflr    r10;                                                         \
 167        stw     r10,_LINK(r11);                                              \
 168        mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
 169        stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
 170        mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
 171        stw     r9,_ESR(r11);           /* exception was taken             */\
 172        mfspr   r12,SPRN_SRR2;                                               \
 173        stw     r1,GPR1(r11);                                                \
 174        mfspr   r9,SPRN_SRR3;                                                \
 175        stw     r1,0(r11);                                                   \
 176        tovirt(r1,r11);                                                      \
 177        rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 178        stw     r0,GPR0(r11);                                                \
 179        SAVE_4GPRS(3, r11);                                                  \
 180        SAVE_2GPRS(7, r11)
 181
 182        /*
 183         * State at this point:
 184         * r9 saved in stack frame, now saved SRR3 & ~MSR_WE
 185         * r10 saved in crit_r10 and in stack frame, trashed
 186         * r11 saved in crit_r11 and in stack frame,
 187         *      now phys stack/exception frame pointer
 188         * r12 saved in stack frame, now saved SRR2
 189         * CR saved in stack frame, CR0.EQ = !SRR3.PR
 190         * LR, DEAR, ESR in stack frame
 191         * r1 saved in stack frame, now virt stack/excframe pointer
 192         * r0, r3-r8 saved in stack frame
 193         */
 194
 195/*
 196 * Exception vectors.
 197 */
 198#define START_EXCEPTION(n, label)                                            \
 199        . = n;                                                               \
 200label:
 201
 202#define EXCEPTION(n, label, hdlr, xfer)                         \
 203        START_EXCEPTION(n, label);                              \
 204        NORMAL_EXCEPTION_PROLOG;                                \
 205        addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 206        xfer(n, hdlr)
 207
 208#define CRITICAL_EXCEPTION(n, label, hdlr)                      \
 209        START_EXCEPTION(n, label);                              \
 210        CRITICAL_EXCEPTION_PROLOG;                              \
 211        addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 212        EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 213                          NOCOPY, crit_transfer_to_handler,     \
 214                          ret_from_crit_exc)
 215
 216#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)   \
 217        li      r10,trap;                                       \
 218        stw     r10,_TRAP(r11);                                 \
 219        lis     r10,msr@h;                                      \
 220        ori     r10,r10,msr@l;                                  \
 221        copyee(r10, r9);                                        \
 222        bl      tfer;                                           \
 223        .long   hdlr;                                           \
 224        .long   ret
 225
 226#define COPY_EE(d, s)           rlwimi d,s,0,16,16
 227#define NOCOPY(d, s)
 228
 229#define EXC_XFER_STD(n, hdlr)           \
 230        EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
 231                          ret_from_except_full)
 232
 233#define EXC_XFER_LITE(n, hdlr)          \
 234        EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
 235                          ret_from_except)
 236
 237#define EXC_XFER_EE(n, hdlr)            \
 238        EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
 239                          ret_from_except_full)
 240
 241#define EXC_XFER_EE_LITE(n, hdlr)       \
 242        EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
 243                          ret_from_except)
 244
 245
 246/*
 247 * 0x0100 - Critical Interrupt Exception
 248 */
 249        CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
 250
 251/*
 252 * 0x0200 - Machine Check Exception
 253 */
 254        CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 255
 256/*
 257 * 0x0300 - Data Storage Exception
 258 * This happens for just a few reasons.  U0 set (but we don't do that),
 259 * or zone protection fault (user violation, write to protected page).
 260 * If this is just an update of modified status, we do that quickly
 261 * and exit.  Otherwise, we call heavywight functions to do the work.
 262 */
 263        START_EXCEPTION(0x0300, DataStorage)
 264        mtspr   SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
 265        mtspr   SPRN_SPRG_SCRATCH1, r11
 266#ifdef CONFIG_403GCX
 267        stw     r12, 0(r0)
 268        stw     r9, 4(r0)
 269        mfcr    r11
 270        mfspr   r12, SPRN_PID
 271        stw     r11, 8(r0)
 272        stw     r12, 12(r0)
 273#else
 274        mtspr   SPRN_SPRG_SCRATCH3, r12
 275        mtspr   SPRN_SPRG_SCRATCH4, r9
 276        mfcr    r11
 277        mfspr   r12, SPRN_PID
 278        mtspr   SPRN_SPRG_SCRATCH6, r11
 279        mtspr   SPRN_SPRG_SCRATCH5, r12
 280#endif
 281
 282        /* First, check if it was a zone fault (which means a user
 283        * tried to access a kernel or read-protected page - always
 284        * a SEGV).  All other faults here must be stores, so no
 285        * need to check ESR_DST as well. */
 286        mfspr   r10, SPRN_ESR
 287        andis.  r10, r10, ESR_DIZ@h
 288        bne     2f
 289
 290        mfspr   r10, SPRN_DEAR          /* Get faulting address */
 291
 292        /* If we are faulting a kernel address, we have to use the
 293         * kernel page tables.
 294         */
 295        lis     r11, PAGE_OFFSET@h
 296        cmplw   r10, r11
 297        blt+    3f
 298        lis     r11, swapper_pg_dir@h
 299        ori     r11, r11, swapper_pg_dir@l
 300        li      r9, 0
 301        mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 302        b       4f
 303
 304        /* Get the PGD for the current thread.
 305         */
 3063:
 307        mfspr   r11,SPRN_SPRG_THREAD
 308        lwz     r11,PGDIR(r11)
 3094:
 310        tophys(r11, r11)
 311        rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 312        lwz     r11, 0(r11)             /* Get L1 entry */
 313        rlwinm. r12, r11, 0, 0, 19      /* Extract L2 (pte) base address */
 314        beq     2f                      /* Bail if no table */
 315
 316        rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 317        lwz     r11, 0(r12)             /* Get Linux PTE */
 318
 319        andi.   r9, r11, _PAGE_RW       /* Is it writeable? */
 320        beq     2f                      /* Bail if not */
 321
 322        /* Update 'changed'.
 323        */
 324        ori     r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 325        stw     r11, 0(r12)             /* Update Linux page table */
 326
 327        /* Most of the Linux PTE is ready to load into the TLB LO.
 328         * We set ZSEL, where only the LS-bit determines user access.
 329         * We set execute, because we don't have the granularity to
 330         * properly set this at the page level (Linux problem).
 331         * If shared is set, we cause a zero PID->TID load.
 332         * Many of these bits are software only.  Bits we don't set
 333         * here we (properly should) assume have the appropriate value.
 334         */
 335        li      r12, 0x0ce2
 336        andc    r11, r11, r12           /* Make sure 20, 21 are zero */
 337
 338        /* find the TLB index that caused the fault.  It has to be here.
 339        */
 340        tlbsx   r9, 0, r10
 341
 342        tlbwe   r11, r9, TLB_DATA               /* Load TLB LO */
 343
 344        /* Done...restore registers and get out of here.
 345        */
 346#ifdef CONFIG_403GCX
 347        lwz     r12, 12(r0)
 348        lwz     r11, 8(r0)
 349        mtspr   SPRN_PID, r12
 350        mtcr    r11
 351        lwz     r9, 4(r0)
 352        lwz     r12, 0(r0)
 353#else
 354        mfspr   r12, SPRN_SPRG_SCRATCH5
 355        mfspr   r11, SPRN_SPRG_SCRATCH6
 356        mtspr   SPRN_PID, r12
 357        mtcr    r11
 358        mfspr   r9, SPRN_SPRG_SCRATCH4
 359        mfspr   r12, SPRN_SPRG_SCRATCH3
 360#endif
 361        mfspr   r11, SPRN_SPRG_SCRATCH1
 362        mfspr   r10, SPRN_SPRG_SCRATCH0
 363        PPC405_ERR77_SYNC
 364        rfi                     /* Should sync shadow TLBs */
 365        b       .               /* prevent prefetch past rfi */
 366
 3672:
 368        /* The bailout.  Restore registers to pre-exception conditions
 369         * and call the heavyweights to help us out.
 370         */
 371#ifdef CONFIG_403GCX
 372        lwz     r12, 12(r0)
 373        lwz     r11, 8(r0)
 374        mtspr   SPRN_PID, r12
 375        mtcr    r11
 376        lwz     r9, 4(r0)
 377        lwz     r12, 0(r0)
 378#else
 379        mfspr   r12, SPRN_SPRG_SCRATCH5
 380        mfspr   r11, SPRN_SPRG_SCRATCH6
 381        mtspr   SPRN_PID, r12
 382        mtcr    r11
 383        mfspr   r9, SPRN_SPRG_SCRATCH4
 384        mfspr   r12, SPRN_SPRG_SCRATCH3
 385#endif
 386        mfspr   r11, SPRN_SPRG_SCRATCH1
 387        mfspr   r10, SPRN_SPRG_SCRATCH0
 388        b       DataAccess
 389
 390/*
 391 * 0x0400 - Instruction Storage Exception
 392 * This is caused by a fetch from non-execute or guarded pages.
 393 */
 394        START_EXCEPTION(0x0400, InstructionAccess)
 395        NORMAL_EXCEPTION_PROLOG
 396        mr      r4,r12                  /* Pass SRR0 as arg2 */
 397        li      r5,0                    /* Pass zero as arg3 */
 398        EXC_XFER_LITE(0x400, handle_page_fault)
 399
 400/* 0x0500 - External Interrupt Exception */
 401        EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
 402
 403/* 0x0600 - Alignment Exception */
 404        START_EXCEPTION(0x0600, Alignment)
 405        NORMAL_EXCEPTION_PROLOG
 406        mfspr   r4,SPRN_DEAR            /* Grab the DEAR and save it */
 407        stw     r4,_DEAR(r11)
 408        addi    r3,r1,STACK_FRAME_OVERHEAD
 409        EXC_XFER_EE(0x600, alignment_exception)
 410
 411/* 0x0700 - Program Exception */
 412        START_EXCEPTION(0x0700, ProgramCheck)
 413        NORMAL_EXCEPTION_PROLOG
 414        mfspr   r4,SPRN_ESR             /* Grab the ESR and save it */
 415        stw     r4,_ESR(r11)
 416        addi    r3,r1,STACK_FRAME_OVERHEAD
 417        EXC_XFER_STD(0x700, program_check_exception)
 418
 419        EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE)
 420        EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE)
 421        EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE)
 422        EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE)
 423
 424/* 0x0C00 - System Call Exception */
 425        START_EXCEPTION(0x0C00, SystemCall)
 426        NORMAL_EXCEPTION_PROLOG
 427        EXC_XFER_EE_LITE(0xc00, DoSyscall)
 428
 429        EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE)
 430        EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE)
 431        EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE)
 432
 433/* 0x1000 - Programmable Interval Timer (PIT) Exception */
 434        . = 0x1000
 435        b Decrementer
 436
 437/* 0x1010 - Fixed Interval Timer (FIT) Exception
 438*/
 439        . = 0x1010
 440        b FITException
 441
 442/* 0x1020 - Watchdog Timer (WDT) Exception
 443*/
 444        . = 0x1020
 445        b WDTException
 446
 447/* 0x1100 - Data TLB Miss Exception
 448 * As the name implies, translation is not in the MMU, so search the
 449 * page tables and fix it.  The only purpose of this function is to
 450 * load TLB entries from the page table if they exist.
 451 */
 452        START_EXCEPTION(0x1100, DTLBMiss)
 453        mtspr   SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
 454        mtspr   SPRN_SPRG_SCRATCH1, r11
 455#ifdef CONFIG_403GCX
 456        stw     r12, 0(r0)
 457        stw     r9, 4(r0)
 458        mfcr    r11
 459        mfspr   r12, SPRN_PID
 460        stw     r11, 8(r0)
 461        stw     r12, 12(r0)
 462#else
 463        mtspr   SPRN_SPRG_SCRATCH3, r12
 464        mtspr   SPRN_SPRG_SCRATCH4, r9
 465        mfcr    r11
 466        mfspr   r12, SPRN_PID
 467        mtspr   SPRN_SPRG_SCRATCH6, r11
 468        mtspr   SPRN_SPRG_SCRATCH5, r12
 469#endif
 470        mfspr   r10, SPRN_DEAR          /* Get faulting address */
 471
 472        /* If we are faulting a kernel address, we have to use the
 473         * kernel page tables.
 474         */
 475        lis     r11, PAGE_OFFSET@h
 476        cmplw   r10, r11
 477        blt+    3f
 478        lis     r11, swapper_pg_dir@h
 479        ori     r11, r11, swapper_pg_dir@l
 480        li      r9, 0
 481        mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 482        b       4f
 483
 484        /* Get the PGD for the current thread.
 485         */
 4863:
 487        mfspr   r11,SPRN_SPRG_THREAD
 488        lwz     r11,PGDIR(r11)
 4894:
 490        tophys(r11, r11)
 491        rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 492        lwz     r12, 0(r11)             /* Get L1 entry */
 493        andi.   r9, r12, _PMD_PRESENT   /* Check if it points to a PTE page */
 494        beq     2f                      /* Bail if no table */
 495
 496        rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 497        lwz     r11, 0(r12)             /* Get Linux PTE */
 498        andi.   r9, r11, _PAGE_PRESENT
 499        beq     5f
 500
 501        ori     r11, r11, _PAGE_ACCESSED
 502        stw     r11, 0(r12)
 503
 504        /* Create TLB tag.  This is the faulting address plus a static
 505         * set of bits.  These are size, valid, E, U0.
 506        */
 507        li      r12, 0x00c0
 508        rlwimi  r10, r12, 0, 20, 31
 509
 510        b       finish_tlb_load
 511
 5122:      /* Check for possible large-page pmd entry */
 513        rlwinm. r9, r12, 2, 22, 24
 514        beq     5f
 515
 516        /* Create TLB tag.  This is the faulting address, plus a static
 517         * set of bits (valid, E, U0) plus the size from the PMD.
 518         */
 519        ori     r9, r9, 0x40
 520        rlwimi  r10, r9, 0, 20, 31
 521        mr      r11, r12
 522
 523        b       finish_tlb_load
 524
 5255:
 526        /* The bailout.  Restore registers to pre-exception conditions
 527         * and call the heavyweights to help us out.
 528         */
 529#ifdef CONFIG_403GCX
 530        lwz     r12, 12(r0)
 531        lwz     r11, 8(r0)
 532        mtspr   SPRN_PID, r12
 533        mtcr    r11
 534        lwz     r9, 4(r0)
 535        lwz     r12, 0(r0)
 536#else
 537        mfspr   r12, SPRN_SPRG_SCRATCH5
 538        mfspr   r11, SPRN_SPRG_SCRATCH6
 539        mtspr   SPRN_PID, r12
 540        mtcr    r11
 541        mfspr   r9, SPRN_SPRG_SCRATCH4
 542        mfspr   r12, SPRN_SPRG_SCRATCH3
 543#endif
 544        mfspr   r11, SPRN_SPRG_SCRATCH1
 545        mfspr   r10, SPRN_SPRG_SCRATCH0
 546        b       DataAccess
 547
 548/* 0x1200 - Instruction TLB Miss Exception
 549 * Nearly the same as above, except we get our information from different
 550 * registers and bailout to a different point.
 551 */
 552        START_EXCEPTION(0x1200, ITLBMiss)
 553        mtspr   SPRN_SPRG_SCRATCH0, r10  /* Save some working registers */
 554        mtspr   SPRN_SPRG_SCRATCH1, r11
 555#ifdef CONFIG_403GCX
 556        stw     r12, 0(r0)
 557        stw     r9, 4(r0)
 558        mfcr    r11
 559        mfspr   r12, SPRN_PID
 560        stw     r11, 8(r0)
 561        stw     r12, 12(r0)
 562#else
 563        mtspr   SPRN_SPRG_SCRATCH3, r12
 564        mtspr   SPRN_SPRG_SCRATCH4, r9
 565        mfcr    r11
 566        mfspr   r12, SPRN_PID
 567        mtspr   SPRN_SPRG_SCRATCH6, r11
 568        mtspr   SPRN_SPRG_SCRATCH5, r12
 569#endif
 570        mfspr   r10, SPRN_SRR0          /* Get faulting address */
 571
 572        /* If we are faulting a kernel address, we have to use the
 573         * kernel page tables.
 574         */
 575        lis     r11, PAGE_OFFSET@h
 576        cmplw   r10, r11
 577        blt+    3f
 578        lis     r11, swapper_pg_dir@h
 579        ori     r11, r11, swapper_pg_dir@l
 580        li      r9, 0
 581        mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 582        b       4f
 583
 584        /* Get the PGD for the current thread.
 585         */
 5863:
 587        mfspr   r11,SPRN_SPRG_THREAD
 588        lwz     r11,PGDIR(r11)
 5894:
 590        tophys(r11, r11)
 591        rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 592        lwz     r12, 0(r11)             /* Get L1 entry */
 593        andi.   r9, r12, _PMD_PRESENT   /* Check if it points to a PTE page */
 594        beq     2f                      /* Bail if no table */
 595
 596        rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 597        lwz     r11, 0(r12)             /* Get Linux PTE */
 598        andi.   r9, r11, _PAGE_PRESENT
 599        beq     5f
 600
 601        ori     r11, r11, _PAGE_ACCESSED
 602        stw     r11, 0(r12)
 603
 604        /* Create TLB tag.  This is the faulting address plus a static
 605         * set of bits.  These are size, valid, E, U0.
 606        */
 607        li      r12, 0x00c0
 608        rlwimi  r10, r12, 0, 20, 31
 609
 610        b       finish_tlb_load
 611
 6122:      /* Check for possible large-page pmd entry */
 613        rlwinm. r9, r12, 2, 22, 24
 614        beq     5f
 615
 616        /* Create TLB tag.  This is the faulting address, plus a static
 617         * set of bits (valid, E, U0) plus the size from the PMD.
 618         */
 619        ori     r9, r9, 0x40
 620        rlwimi  r10, r9, 0, 20, 31
 621        mr      r11, r12
 622
 623        b       finish_tlb_load
 624
 6255:
 626        /* The bailout.  Restore registers to pre-exception conditions
 627         * and call the heavyweights to help us out.
 628         */
 629#ifdef CONFIG_403GCX
 630        lwz     r12, 12(r0)
 631        lwz     r11, 8(r0)
 632        mtspr   SPRN_PID, r12
 633        mtcr    r11
 634        lwz     r9, 4(r0)
 635        lwz     r12, 0(r0)
 636#else
 637        mfspr   r12, SPRN_SPRG_SCRATCH5
 638        mfspr   r11, SPRN_SPRG_SCRATCH6
 639        mtspr   SPRN_PID, r12
 640        mtcr    r11
 641        mfspr   r9, SPRN_SPRG_SCRATCH4
 642        mfspr   r12, SPRN_SPRG_SCRATCH3
 643#endif
 644        mfspr   r11, SPRN_SPRG_SCRATCH1
 645        mfspr   r10, SPRN_SPRG_SCRATCH0
 646        b       InstructionAccess
 647
 648        EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE)
 649        EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE)
 650        EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
 651        EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
 652#ifdef CONFIG_IBM405_ERR51
 653        /* 405GP errata 51 */
 654        START_EXCEPTION(0x1700, Trap_17)
 655        b DTLBMiss
 656#else
 657        EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
 658#endif
 659        EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
 660        EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
 661        EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE)
 662        EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE)
 663        EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE)
 664        EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE)
 665        EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE)
 666        EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE)
 667
 668/* Check for a single step debug exception while in an exception
 669 * handler before state has been saved.  This is to catch the case
 670 * where an instruction that we are trying to single step causes
 671 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 672 * the exception handler generates a single step debug exception.
 673 *
 674 * If we get a debug trap on the first instruction of an exception handler,
 675 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 676 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 677 * The exception handler was handling a non-critical interrupt, so it will
 678 * save (and later restore) the MSR via SPRN_SRR1, which will still have
 679 * the MSR_DE bit set.
 680 */
 681        /* 0x2000 - Debug Exception */
 682        START_EXCEPTION(0x2000, DebugTrap)
 683        CRITICAL_EXCEPTION_PROLOG
 684
 685        /*
 686         * If this is a single step or branch-taken exception in an
 687         * exception entry sequence, it was probably meant to apply to
 688         * the code where the exception occurred (since exception entry
 689         * doesn't turn off DE automatically).  We simulate the effect
 690         * of turning off DE on entry to an exception handler by turning
 691         * off DE in the SRR3 value and clearing the debug status.
 692         */
 693        mfspr   r10,SPRN_DBSR           /* check single-step/branch taken */
 694        andis.  r10,r10,DBSR_IC@h
 695        beq+    2f
 696
 697        andi.   r10,r9,MSR_IR|MSR_PR    /* check supervisor + MMU off */
 698        beq     1f                      /* branch and fix it up */
 699
 700        mfspr   r10,SPRN_SRR2           /* Faulting instruction address */
 701        cmplwi  r10,0x2100
 702        bgt+    2f                      /* address above exception vectors */
 703
 704        /* here it looks like we got an inappropriate debug exception. */
 7051:      rlwinm  r9,r9,0,~MSR_DE         /* clear DE in the SRR3 value */
 706        lis     r10,DBSR_IC@h           /* clear the IC event */
 707        mtspr   SPRN_DBSR,r10
 708        /* restore state and get out */
 709        lwz     r10,_CCR(r11)
 710        lwz     r0,GPR0(r11)
 711        lwz     r1,GPR1(r11)
 712        mtcrf   0x80,r10
 713        mtspr   SPRN_SRR2,r12
 714        mtspr   SPRN_SRR3,r9
 715        lwz     r9,GPR9(r11)
 716        lwz     r12,GPR12(r11)
 717        lwz     r10,crit_r10@l(0)
 718        lwz     r11,crit_r11@l(0)
 719        PPC405_ERR77_SYNC
 720        rfci
 721        b       .
 722
 723        /* continue normal handling for a critical exception... */
 7242:      mfspr   r4,SPRN_DBSR
 725        addi    r3,r1,STACK_FRAME_OVERHEAD
 726        EXC_XFER_TEMPLATE(DebugException, 0x2002, \
 727                (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 728                NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
 729
 730        /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
 731Decrementer:
 732        NORMAL_EXCEPTION_PROLOG
 733        lis     r0,TSR_PIS@h
 734        mtspr   SPRN_TSR,r0             /* Clear the PIT exception */
 735        addi    r3,r1,STACK_FRAME_OVERHEAD
 736        EXC_XFER_LITE(0x1000, timer_interrupt)
 737
 738        /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
 739FITException:
 740        NORMAL_EXCEPTION_PROLOG
 741        addi    r3,r1,STACK_FRAME_OVERHEAD;
 742        EXC_XFER_EE(0x1010, unknown_exception)
 743
 744        /* Watchdog Timer (WDT) Exception. (from 0x1020) */
 745WDTException:
 746        CRITICAL_EXCEPTION_PROLOG;
 747        addi    r3,r1,STACK_FRAME_OVERHEAD;
 748        EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2,
 749                          (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)),
 750                          NOCOPY, crit_transfer_to_handler,
 751                          ret_from_crit_exc)
 752
 753/*
 754 * The other Data TLB exceptions bail out to this point
 755 * if they can't resolve the lightweight TLB fault.
 756 */
 757DataAccess:
 758        NORMAL_EXCEPTION_PROLOG
 759        mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 760        stw     r5,_ESR(r11)
 761        mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 762        EXC_XFER_LITE(0x300, handle_page_fault)
 763
 764/* Other PowerPC processors, namely those derived from the 6xx-series
 765 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
 766 * However, for the 4xx-series processors these are neither defined nor
 767 * reserved.
 768 */
 769
 770        /* Damn, I came up one instruction too many to fit into the
 771         * exception space :-).  Both the instruction and data TLB
 772         * miss get to this point to load the TLB.
 773         *      r10 - TLB_TAG value
 774         *      r11 - Linux PTE
 775         *      r12, r9 - available to use
 776         *      PID - loaded with proper value when we get here
 777         *      Upon exit, we reload everything and RFI.
 778         * Actually, it will fit now, but oh well.....a common place
 779         * to load the TLB.
 780         */
 781tlb_4xx_index:
 782        .long   0
 783finish_tlb_load:
 784        /* load the next available TLB index.
 785        */
 786        lwz     r9, tlb_4xx_index@l(0)
 787        addi    r9, r9, 1
 788        andi.   r9, r9, (PPC40X_TLB_SIZE-1)
 789        stw     r9, tlb_4xx_index@l(0)
 790
 7916:
 792        /*
 793         * Clear out the software-only bits in the PTE to generate the
 794         * TLB_DATA value.  These are the bottom 2 bits of the RPM, the
 795         * top 3 bits of the zone field, and M.
 796         */
 797        li      r12, 0x0ce2
 798        andc    r11, r11, r12
 799
 800        tlbwe   r11, r9, TLB_DATA               /* Load TLB LO */
 801        tlbwe   r10, r9, TLB_TAG                /* Load TLB HI */
 802
 803        /* Done...restore registers and get out of here.
 804        */
 805#ifdef CONFIG_403GCX
 806        lwz     r12, 12(r0)
 807        lwz     r11, 8(r0)
 808        mtspr   SPRN_PID, r12
 809        mtcr    r11
 810        lwz     r9, 4(r0)
 811        lwz     r12, 0(r0)
 812#else
 813        mfspr   r12, SPRN_SPRG_SCRATCH5
 814        mfspr   r11, SPRN_SPRG_SCRATCH6
 815        mtspr   SPRN_PID, r12
 816        mtcr    r11
 817        mfspr   r9, SPRN_SPRG_SCRATCH4
 818        mfspr   r12, SPRN_SPRG_SCRATCH3
 819#endif
 820        mfspr   r11, SPRN_SPRG_SCRATCH1
 821        mfspr   r10, SPRN_SPRG_SCRATCH0
 822        PPC405_ERR77_SYNC
 823        rfi                     /* Should sync shadow TLBs */
 824        b       .               /* prevent prefetch past rfi */
 825
 826/* This is where the main kernel code starts.
 827 */
 828start_here:
 829
 830        /* ptr to current */
 831        lis     r2,init_task@h
 832        ori     r2,r2,init_task@l
 833
 834        /* ptr to phys current thread */
 835        tophys(r4,r2)
 836        addi    r4,r4,THREAD    /* init task's THREAD */
 837        mtspr   SPRN_SPRG_THREAD,r4
 838
 839        /* stack */
 840        lis     r1,init_thread_union@ha
 841        addi    r1,r1,init_thread_union@l
 842        li      r0,0
 843        stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 844
 845        bl      early_init      /* We have to do this with MMU on */
 846
 847/*
 848 * Decide what sort of machine this is and initialize the MMU.
 849 */
 850        li      r3,0
 851        mr      r4,r31
 852        bl      machine_init
 853        bl      MMU_init
 854
 855/* Go back to running unmapped so we can load up new values
 856 * and change to using our exception vectors.
 857 * On the 4xx, all we have to do is invalidate the TLB to clear
 858 * the old 16M byte TLB mappings.
 859 */
 860        lis     r4,2f@h
 861        ori     r4,r4,2f@l
 862        tophys(r4,r4)
 863        lis     r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
 864        ori     r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
 865        mtspr   SPRN_SRR0,r4
 866        mtspr   SPRN_SRR1,r3
 867        rfi
 868        b       .               /* prevent prefetch past rfi */
 869
 870/* Load up the kernel context */
 8712:
 872        sync                    /* Flush to memory before changing TLB */
 873        tlbia
 874        isync                   /* Flush shadow TLBs */
 875
 876        /* set up the PTE pointers for the Abatron bdiGDB.
 877        */
 878        lis     r6, swapper_pg_dir@h
 879        ori     r6, r6, swapper_pg_dir@l
 880        lis     r5, abatron_pteptrs@h
 881        ori     r5, r5, abatron_pteptrs@l
 882        stw     r5, 0xf0(r0)    /* Must match your Abatron config file */
 883        tophys(r5,r5)
 884        stw     r6, 0(r5)
 885
 886/* Now turn on the MMU for real! */
 887        lis     r4,MSR_KERNEL@h
 888        ori     r4,r4,MSR_KERNEL@l
 889        lis     r3,start_kernel@h
 890        ori     r3,r3,start_kernel@l
 891        mtspr   SPRN_SRR0,r3
 892        mtspr   SPRN_SRR1,r4
 893        rfi                     /* enable MMU and jump to start_kernel */
 894        b       .               /* prevent prefetch past rfi */
 895
 896/* Set up the initial MMU state so we can do the first level of
 897 * kernel initialization.  This maps the first 16 MBytes of memory 1:1
 898 * virtual to physical and more importantly sets the cache mode.
 899 */
 900initial_mmu:
 901        tlbia                   /* Invalidate all TLB entries */
 902        isync
 903
 904        /* We should still be executing code at physical address 0x0000xxxx
 905         * at this point. However, start_here is at virtual address
 906         * 0xC000xxxx. So, set up a TLB mapping to cover this once
 907         * translation is enabled.
 908         */
 909
 910        lis     r3,KERNELBASE@h         /* Load the kernel virtual address */
 911        ori     r3,r3,KERNELBASE@l
 912        tophys(r4,r3)                   /* Load the kernel physical address */
 913
 914        iccci   r0,r3                   /* Invalidate the i-cache before use */
 915
 916        /* Load the kernel PID.
 917        */
 918        li      r0,0
 919        mtspr   SPRN_PID,r0
 920        sync
 921
 922        /* Configure and load one entry into TLB slots 63 */
 923        clrrwi  r4,r4,10                /* Mask off the real page number */
 924        ori     r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
 925
 926        clrrwi  r3,r3,10                /* Mask off the effective page number */
 927        ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
 928
 929        li      r0,63                    /* TLB slot 63 */
 930
 931        tlbwe   r4,r0,TLB_DATA          /* Load the data portion of the entry */
 932        tlbwe   r3,r0,TLB_TAG           /* Load the tag portion of the entry */
 933
 934        isync
 935
 936        /* Establish the exception vector base
 937        */
 938        lis     r4,KERNELBASE@h         /* EVPR only uses the high 16-bits */
 939        tophys(r0,r4)                   /* Use the physical address */
 940        mtspr   SPRN_EVPR,r0
 941
 942        blr
 943
 944_GLOBAL(abort)
 945        mfspr   r13,SPRN_DBCR0
 946        oris    r13,r13,DBCR0_RST_SYSTEM@h
 947        mtspr   SPRN_DBCR0,r13
 948
 949_GLOBAL(set_context)
 950
 951#ifdef CONFIG_BDI_SWITCH
 952        /* Context switch the PTE pointer for the Abatron BDI2000.
 953         * The PGDIR is the second parameter.
 954         */
 955        lis     r5, KERNELBASE@h
 956        lwz     r5, 0xf0(r5)
 957        stw     r4, 0x4(r5)
 958#endif
 959        sync
 960        mtspr   SPRN_PID,r3
 961        isync                           /* Need an isync to flush shadow */
 962                                        /* TLBs after changing PID */
 963        blr
 964
 965/* We put a few things here that have to be page-aligned. This stuff
 966 * goes at the beginning of the data segment, which is page-aligned.
 967 */
 968        .data
 969        .align  12
 970        .globl  sdata
 971sdata:
 972        .globl  empty_zero_page
 973empty_zero_page:
 974        .space  4096
 975EXPORT_SYMBOL(empty_zero_page)
 976        .globl  swapper_pg_dir
 977swapper_pg_dir:
 978        .space  PGD_TABLE_SIZE
 979
 980/* Room for two PTE pointers, usually the kernel and current user pointers
 981 * to their respective root page table.
 982 */
 983abatron_pteptrs:
 984        .space  8
 985