LXR linux/arch/powerpc/kernel/sysfs.c

   1#include <linux/device.h>
   2#include <linux/cpu.h>
   3#include <linux/smp.h>
   4#include <linux/percpu.h>
   5#include <linux/init.h>
   6#include <linux/sched.h>
   7#include <linux/export.h>
   8#include <linux/nodemask.h>
   9#include <linux/cpumask.h>
  10#include <linux/notifier.h>
  11
  12#include <asm/current.h>
  13#include <asm/processor.h>
  14#include <asm/cputable.h>
  15#include <asm/hvcall.h>
  16#include <asm/prom.h>
  17#include <asm/machdep.h>
  18#include <asm/smp.h>
  19#include <asm/pmc.h>
  20#include <asm/firmware.h>
  21
  22#include "cacheinfo.h"
  23#include "setup.h"
  24
  25#ifdef CONFIG_PPC64
  26#include <asm/paca.h>
  27#include <asm/lppaca.h>
  28#endif
  29
  30static DEFINE_PER_CPU(struct cpu, cpu_devices);
  31
  32/*
  33 * SMT snooze delay stuff, 64-bit only for now
  34 */
  35
  36#ifdef CONFIG_PPC64
  37
  38/* Time in microseconds we delay before sleeping in the idle loop */
  39static DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
  40
  41static ssize_t store_smt_snooze_delay(struct device *dev,
  42                                      struct device_attribute *attr,
  43                                      const char *buf,
  44                                      size_t count)
  45{
  46        struct cpu *cpu = container_of(dev, struct cpu, dev);
  47        ssize_t ret;
  48        long snooze;
  49
  50        ret = sscanf(buf, "%ld", &snooze);
  51        if (ret != 1)
  52                return -EINVAL;
  53
  54        per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
  55        return count;
  56}
  57
  58static ssize_t show_smt_snooze_delay(struct device *dev,
  59                                     struct device_attribute *attr,
  60                                     char *buf)
  61{
  62        struct cpu *cpu = container_of(dev, struct cpu, dev);
  63
  64        return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
  65}
  66
  67static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
  68                   store_smt_snooze_delay);
  69
  70static int __init setup_smt_snooze_delay(char *str)
  71{
  72        unsigned int cpu;
  73        long snooze;
  74
  75        if (!cpu_has_feature(CPU_FTR_SMT))
  76                return 1;
  77
  78        snooze = simple_strtol(str, NULL, 10);
  79        for_each_possible_cpu(cpu)
  80                per_cpu(smt_snooze_delay, cpu) = snooze;
  81
  82        return 1;
  83}
  84__setup("smt-snooze-delay=", setup_smt_snooze_delay);
  85
  86#endif /* CONFIG_PPC64 */
  87
  88#ifdef CONFIG_PPC_FSL_BOOK3E
  89#define MAX_BIT                         63
  90
  91static u64 pw20_wt;
  92static u64 altivec_idle_wt;
  93
  94static unsigned int get_idle_ticks_bit(u64 ns)
  95{
  96        u64 cycle;
  97
  98        if (ns >= 10000)
  99                cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
 100        else
 101                cycle = div_u64(ns * tb_ticks_per_usec, 1000);
 102
 103        if (!cycle)
 104                return 0;
 105
 106        return ilog2(cycle);
 107}
 108
 109static void do_show_pwrmgtcr0(void *val)
 110{
 111        u32 *value = val;
 112
 113        *value = mfspr(SPRN_PWRMGTCR0);
 114}
 115
 116static ssize_t show_pw20_state(struct device *dev,
 117                                struct device_attribute *attr, char *buf)
 118{
 119        u32 value;
 120        unsigned int cpu = dev->id;
 121
 122        smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 123
 124        value &= PWRMGTCR0_PW20_WAIT;
 125
 126        return sprintf(buf, "%u\n", value ? 1 : 0);
 127}
 128
 129static void do_store_pw20_state(void *val)
 130{
 131        u32 *value = val;
 132        u32 pw20_state;
 133
 134        pw20_state = mfspr(SPRN_PWRMGTCR0);
 135
 136        if (*value)
 137                pw20_state |= PWRMGTCR0_PW20_WAIT;
 138        else
 139                pw20_state &= ~PWRMGTCR0_PW20_WAIT;
 140
 141        mtspr(SPRN_PWRMGTCR0, pw20_state);
 142}
 143
 144static ssize_t store_pw20_state(struct device *dev,
 145                                struct device_attribute *attr,
 146                                const char *buf, size_t count)
 147{
 148        u32 value;
 149        unsigned int cpu = dev->id;
 150
 151        if (kstrtou32(buf, 0, &value))
 152                return -EINVAL;
 153
 154        if (value > 1)
 155                return -EINVAL;
 156
 157        smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
 158
 159        return count;
 160}
 161
 162static ssize_t show_pw20_wait_time(struct device *dev,
 163                                struct device_attribute *attr, char *buf)
 164{
 165        u32 value;
 166        u64 tb_cycle = 1;
 167        u64 time;
 168
 169        unsigned int cpu = dev->id;
 170
 171        if (!pw20_wt) {
 172                smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 173                value = (value & PWRMGTCR0_PW20_ENT) >>
 174                                        PWRMGTCR0_PW20_ENT_SHIFT;
 175
 176                tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 177                /* convert ms to ns */
 178                if (tb_ticks_per_usec > 1000) {
 179                        time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 180                } else {
 181                        u32 rem_us;
 182
 183                        time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 184                                                &rem_us);
 185                        time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 186                }
 187        } else {
 188                time = pw20_wt;
 189        }
 190
 191        return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 192}
 193
 194static void set_pw20_wait_entry_bit(void *val)
 195{
 196        u32 *value = val;
 197        u32 pw20_idle;
 198
 199        pw20_idle = mfspr(SPRN_PWRMGTCR0);
 200
 201        /* Set Automatic PW20 Core Idle Count */
 202        /* clear count */
 203        pw20_idle &= ~PWRMGTCR0_PW20_ENT;
 204
 205        /* set count */
 206        pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
 207
 208        mtspr(SPRN_PWRMGTCR0, pw20_idle);
 209}
 210
 211static ssize_t store_pw20_wait_time(struct device *dev,
 212                                struct device_attribute *attr,
 213                                const char *buf, size_t count)
 214{
 215        u32 entry_bit;
 216        u64 value;
 217
 218        unsigned int cpu = dev->id;
 219
 220        if (kstrtou64(buf, 0, &value))
 221                return -EINVAL;
 222
 223        if (!value)
 224                return -EINVAL;
 225
 226        entry_bit = get_idle_ticks_bit(value);
 227        if (entry_bit > MAX_BIT)
 228                return -EINVAL;
 229
 230        pw20_wt = value;
 231
 232        smp_call_function_single(cpu, set_pw20_wait_entry_bit,
 233                                &entry_bit, 1);
 234
 235        return count;
 236}
 237
 238static ssize_t show_altivec_idle(struct device *dev,
 239                                struct device_attribute *attr, char *buf)
 240{
 241        u32 value;
 242        unsigned int cpu = dev->id;
 243
 244        smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 245
 246        value &= PWRMGTCR0_AV_IDLE_PD_EN;
 247
 248        return sprintf(buf, "%u\n", value ? 1 : 0);
 249}
 250
 251static void do_store_altivec_idle(void *val)
 252{
 253        u32 *value = val;
 254        u32 altivec_idle;
 255
 256        altivec_idle = mfspr(SPRN_PWRMGTCR0);
 257
 258        if (*value)
 259                altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
 260        else
 261                altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
 262
 263        mtspr(SPRN_PWRMGTCR0, altivec_idle);
 264}
 265
 266static ssize_t store_altivec_idle(struct device *dev,
 267                                struct device_attribute *attr,
 268                                const char *buf, size_t count)
 269{
 270        u32 value;
 271        unsigned int cpu = dev->id;
 272
 273        if (kstrtou32(buf, 0, &value))
 274                return -EINVAL;
 275
 276        if (value > 1)
 277                return -EINVAL;
 278
 279        smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
 280
 281        return count;
 282}
 283
 284static ssize_t show_altivec_idle_wait_time(struct device *dev,
 285                                struct device_attribute *attr, char *buf)
 286{
 287        u32 value;
 288        u64 tb_cycle = 1;
 289        u64 time;
 290
 291        unsigned int cpu = dev->id;
 292
 293        if (!altivec_idle_wt) {
 294                smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 295                value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
 296                                        PWRMGTCR0_AV_IDLE_CNT_SHIFT;
 297
 298                tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 299                /* convert ms to ns */
 300                if (tb_ticks_per_usec > 1000) {
 301                        time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 302                } else {
 303                        u32 rem_us;
 304
 305                        time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 306                                                &rem_us);
 307                        time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 308                }
 309        } else {
 310                time = altivec_idle_wt;
 311        }
 312
 313        return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 314}
 315
 316static void set_altivec_idle_wait_entry_bit(void *val)
 317{
 318        u32 *value = val;
 319        u32 altivec_idle;
 320
 321        altivec_idle = mfspr(SPRN_PWRMGTCR0);
 322
 323        /* Set Automatic AltiVec Idle Count */
 324        /* clear count */
 325        altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
 326
 327        /* set count */
 328        altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
 329
 330        mtspr(SPRN_PWRMGTCR0, altivec_idle);
 331}
 332
 333static ssize_t store_altivec_idle_wait_time(struct device *dev,
 334                                struct device_attribute *attr,
 335                                const char *buf, size_t count)
 336{
 337        u32 entry_bit;
 338        u64 value;
 339
 340        unsigned int cpu = dev->id;
 341
 342        if (kstrtou64(buf, 0, &value))
 343                return -EINVAL;
 344
 345        if (!value)
 346                return -EINVAL;
 347
 348        entry_bit = get_idle_ticks_bit(value);
 349        if (entry_bit > MAX_BIT)
 350                return -EINVAL;
 351
 352        altivec_idle_wt = value;
 353
 354        smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
 355                                &entry_bit, 1);
 356
 357        return count;
 358}
 359
 360/*
 361 * Enable/Disable interface:
 362 * 0, disable. 1, enable.
 363 */
 364static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
 365static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
 366
 367/*
 368 * Set wait time interface:(Nanosecond)
 369 * Example: Base on TBfreq is 41MHZ.
 370 * 1~48(ns): TB[63]
 371 * 49~97(ns): TB[62]
 372 * 98~195(ns): TB[61]
 373 * 196~390(ns): TB[60]
 374 * 391~780(ns): TB[59]
 375 * 781~1560(ns): TB[58]
 376 * ...
 377 */
 378static DEVICE_ATTR(pw20_wait_time, 0600,
 379                        show_pw20_wait_time,
 380                        store_pw20_wait_time);
 381static DEVICE_ATTR(altivec_idle_wait_time, 0600,
 382                        show_altivec_idle_wait_time,
 383                        store_altivec_idle_wait_time);
 384#endif
 385
 386/*
 387 * Enabling PMCs will slow partition context switch times so we only do
 388 * it the first time we write to the PMCs.
 389 */
 390
 391static DEFINE_PER_CPU(char, pmcs_enabled);
 392
 393void ppc_enable_pmcs(void)
 394{
 395        ppc_set_pmu_inuse(1);
 396
 397        /* Only need to enable them once */
 398        if (__this_cpu_read(pmcs_enabled))
 399                return;
 400
 401        __this_cpu_write(pmcs_enabled, 1);
 402
 403        if (ppc_md.enable_pmcs)
 404                ppc_md.enable_pmcs();
 405}
 406EXPORT_SYMBOL(ppc_enable_pmcs);
 407
 408#define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
 409static void read_##NAME(void *val) \
 410{ \
 411        *(unsigned long *)val = mfspr(ADDRESS); \
 412} \
 413static void write_##NAME(void *val) \
 414{ \
 415        EXTRA; \
 416        mtspr(ADDRESS, *(unsigned long *)val);  \
 417}
 418
 419#define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 420static ssize_t show_##NAME(struct device *dev, \
 421                        struct device_attribute *attr, \
 422                        char *buf) \
 423{ \
 424        struct cpu *cpu = container_of(dev, struct cpu, dev); \
 425        unsigned long val; \
 426        smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);    \
 427        return sprintf(buf, "%lx\n", val); \
 428} \
 429static ssize_t __used \
 430        store_##NAME(struct device *dev, struct device_attribute *attr, \
 431                        const char *buf, size_t count) \
 432{ \
 433        struct cpu *cpu = container_of(dev, struct cpu, dev); \
 434        unsigned long val; \
 435        int ret = sscanf(buf, "%lx", &val); \
 436        if (ret != 1) \
 437                return -EINVAL; \
 438        smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
 439        return count; \
 440}
 441
 442#define SYSFS_PMCSETUP(NAME, ADDRESS) \
 443        __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
 444        __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 445#define SYSFS_SPRSETUP(NAME, ADDRESS) \
 446        __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
 447        __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 448
 449#define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 450        __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 451
 452/* Let's define all possible registers, we'll only hook up the ones
 453 * that are implemented on the current processor
 454 */
 455
 456#if defined(CONFIG_PPC64)
 457#define HAS_PPC_PMC_CLASSIC     1
 458#define HAS_PPC_PMC_IBM         1
 459#define HAS_PPC_PMC_PA6T        1
 460#elif defined(CONFIG_6xx)
 461#define HAS_PPC_PMC_CLASSIC     1
 462#define HAS_PPC_PMC_IBM         1
 463#define HAS_PPC_PMC_G4          1
 464#endif
 465
 466
 467#ifdef HAS_PPC_PMC_CLASSIC
 468SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
 469SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
 470SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
 471SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
 472SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
 473SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
 474SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
 475SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
 476
 477#ifdef HAS_PPC_PMC_G4
 478SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
 479#endif
 480
 481#ifdef CONFIG_PPC64
 482SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
 483SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
 484
 485SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
 486SYSFS_SPRSETUP(purr, SPRN_PURR);
 487SYSFS_SPRSETUP(spurr, SPRN_SPURR);
 488SYSFS_SPRSETUP(pir, SPRN_PIR);
 489SYSFS_SPRSETUP(tscr, SPRN_TSCR);
 490
 491/*
 492  Lets only enable read for phyp resources and
 493  enable write when needed with a separate function.
 494  Lets be conservative and default to pseries.
 495*/
 496static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 497static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
 498static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
 499static DEVICE_ATTR(pir, 0400, show_pir, NULL);
 500static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
 501
 502/*
 503 * This is the system wide DSCR register default value. Any
 504 * change to this default value through the sysfs interface
 505 * will update all per cpu DSCR default values across the
 506 * system stored in their respective PACA structures.
 507 */
 508static unsigned long dscr_default;
 509
 510/**
 511 * read_dscr() - Fetch the cpu specific DSCR default
 512 * @val:        Returned cpu specific DSCR default value
 513 *
 514 * This function returns the per cpu DSCR default value
 515 * for any cpu which is contained in it's PACA structure.
 516 */
 517static void read_dscr(void *val)
 518{
 519        *(unsigned long *)val = get_paca()->dscr_default;
 520}
 521
 522
 523/**
 524 * write_dscr() - Update the cpu specific DSCR default
 525 * @val:        New cpu specific DSCR default value to update
 526 *
 527 * This function updates the per cpu DSCR default value
 528 * for any cpu which is contained in it's PACA structure.
 529 */
 530static void write_dscr(void *val)
 531{
 532        get_paca()->dscr_default = *(unsigned long *)val;
 533        if (!current->thread.dscr_inherit) {
 534                current->thread.dscr = *(unsigned long *)val;
 535                mtspr(SPRN_DSCR, *(unsigned long *)val);
 536        }
 537}
 538
 539SYSFS_SPRSETUP_SHOW_STORE(dscr);
 540static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 541
 542static void add_write_permission_dev_attr(struct device_attribute *attr)
 543{
 544        attr->attr.mode |= 0200;
 545}
 546
 547/**
 548 * show_dscr_default() - Fetch the system wide DSCR default
 549 * @dev:        Device structure
 550 * @attr:       Device attribute structure
 551 * @buf:        Interface buffer
 552 *
 553 * This function returns the system wide DSCR default value.
 554 */
 555static ssize_t show_dscr_default(struct device *dev,
 556                struct device_attribute *attr, char *buf)
 557{
 558        return sprintf(buf, "%lx\n", dscr_default);
 559}
 560
 561/**
 562 * store_dscr_default() - Update the system wide DSCR default
 563 * @dev:        Device structure
 564 * @attr:       Device attribute structure
 565 * @buf:        Interface buffer
 566 * @count:      Size of the update
 567 *
 568 * This function updates the system wide DSCR default value.
 569 */
 570static ssize_t __used store_dscr_default(struct device *dev,
 571                struct device_attribute *attr, const char *buf,
 572                size_t count)
 573{
 574        unsigned long val;
 575        int ret = 0;
 576        
 577        ret = sscanf(buf, "%lx", &val);
 578        if (ret != 1)
 579                return -EINVAL;
 580        dscr_default = val;
 581
 582        on_each_cpu(write_dscr, &val, 1);
 583
 584        return count;
 585}
 586
 587static DEVICE_ATTR(dscr_default, 0600,
 588                show_dscr_default, store_dscr_default);
 589
 590static void sysfs_create_dscr_default(void)
 591{
 592        if (cpu_has_feature(CPU_FTR_DSCR)) {
 593                int err = 0;
 594                int cpu;
 595
 596                dscr_default = spr_default_dscr;
 597                for_each_possible_cpu(cpu)
 598                        paca_ptrs[cpu]->dscr_default = dscr_default;
 599
 600                err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
 601        }
 602}
 603
 604#endif /* CONFIG_PPC64 */
 605
 606#ifdef HAS_PPC_PMC_PA6T
 607SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
 608SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
 609SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
 610SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
 611SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
 612SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
 613#ifdef CONFIG_DEBUG_KERNEL
 614SYSFS_SPRSETUP(hid0, SPRN_HID0);
 615SYSFS_SPRSETUP(hid1, SPRN_HID1);
 616SYSFS_SPRSETUP(hid4, SPRN_HID4);
 617SYSFS_SPRSETUP(hid5, SPRN_HID5);
 618SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
 619SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
 620SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
 621SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
 622SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
 623SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
 624SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
 625SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
 626SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
 627SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
 628SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
 629SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
 630SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
 631SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
 632SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
 633SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
 634SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
 635SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
 636SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
 637SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
 638SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
 639SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
 640SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
 641SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
 642#endif /* CONFIG_DEBUG_KERNEL */
 643#endif /* HAS_PPC_PMC_PA6T */
 644
 645#ifdef HAS_PPC_PMC_IBM
 646static struct device_attribute ibm_common_attrs[] = {
 647        __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 648        __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 649};
 650#endif /* HAS_PPC_PMC_G4 */
 651
 652#ifdef HAS_PPC_PMC_G4
 653static struct device_attribute g4_common_attrs[] = {
 654        __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 655        __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 656        __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
 657};
 658#endif /* HAS_PPC_PMC_G4 */
 659
 660static struct device_attribute classic_pmc_attrs[] = {
 661        __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
 662        __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
 663        __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
 664        __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
 665        __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
 666        __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
 667#ifdef CONFIG_PPC64
 668        __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
 669        __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
 670#endif
 671};
 672
 673#ifdef HAS_PPC_PMC_PA6T
 674static struct device_attribute pa6t_attrs[] = {
 675        __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 676        __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 677        __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
 678        __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
 679        __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
 680        __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
 681        __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
 682        __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
 683#ifdef CONFIG_DEBUG_KERNEL
 684        __ATTR(hid0, 0600, show_hid0, store_hid0),
 685        __ATTR(hid1, 0600, show_hid1, store_hid1),
 686        __ATTR(hid4, 0600, show_hid4, store_hid4),
 687        __ATTR(hid5, 0600, show_hid5, store_hid5),
 688        __ATTR(ima0, 0600, show_ima0, store_ima0),
 689        __ATTR(ima1, 0600, show_ima1, store_ima1),
 690        __ATTR(ima2, 0600, show_ima2, store_ima2),
 691        __ATTR(ima3, 0600, show_ima3, store_ima3),
 692        __ATTR(ima4, 0600, show_ima4, store_ima4),
 693        __ATTR(ima5, 0600, show_ima5, store_ima5),
 694        __ATTR(ima6, 0600, show_ima6, store_ima6),
 695        __ATTR(ima7, 0600, show_ima7, store_ima7),
 696        __ATTR(ima8, 0600, show_ima8, store_ima8),
 697        __ATTR(ima9, 0600, show_ima9, store_ima9),
 698        __ATTR(imaat, 0600, show_imaat, store_imaat),
 699        __ATTR(btcr, 0600, show_btcr, store_btcr),
 700        __ATTR(pccr, 0600, show_pccr, store_pccr),
 701        __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
 702        __ATTR(der, 0600, show_der, store_der),
 703        __ATTR(mer, 0600, show_mer, store_mer),
 704        __ATTR(ber, 0600, show_ber, store_ber),
 705        __ATTR(ier, 0600, show_ier, store_ier),
 706        __ATTR(sier, 0600, show_sier, store_sier),
 707        __ATTR(siar, 0600, show_siar, store_siar),
 708        __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
 709        __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
 710        __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
 711        __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
 712#endif /* CONFIG_DEBUG_KERNEL */
 713};
 714#endif /* HAS_PPC_PMC_PA6T */
 715#endif /* HAS_PPC_PMC_CLASSIC */
 716
 717static int register_cpu_online(unsigned int cpu)
 718{
 719        struct cpu *c = &per_cpu(cpu_devices, cpu);
 720        struct device *s = &c->dev;
 721        struct device_attribute *attrs, *pmc_attrs;
 722        int i, nattrs;
 723
 724        /* For cpus present at boot a reference was already grabbed in register_cpu() */
 725        if (!s->of_node)
 726                s->of_node = of_get_cpu_node(cpu, NULL);
 727
 728#ifdef CONFIG_PPC64
 729        if (cpu_has_feature(CPU_FTR_SMT))
 730                device_create_file(s, &dev_attr_smt_snooze_delay);
 731#endif
 732
 733        /* PMC stuff */
 734        switch (cur_cpu_spec->pmc_type) {
 735#ifdef HAS_PPC_PMC_IBM
 736        case PPC_PMC_IBM:
 737                attrs = ibm_common_attrs;
 738                nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 739                pmc_attrs = classic_pmc_attrs;
 740                break;
 741#endif /* HAS_PPC_PMC_IBM */
 742#ifdef HAS_PPC_PMC_G4
 743        case PPC_PMC_G4:
 744                attrs = g4_common_attrs;
 745                nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 746                pmc_attrs = classic_pmc_attrs;
 747                break;
 748#endif /* HAS_PPC_PMC_G4 */
 749#ifdef HAS_PPC_PMC_PA6T
 750        case PPC_PMC_PA6T:
 751                /* PA Semi starts counting at PMC0 */
 752                attrs = pa6t_attrs;
 753                nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 754                pmc_attrs = NULL;
 755                break;
 756#endif /* HAS_PPC_PMC_PA6T */
 757        default:
 758                attrs = NULL;
 759                nattrs = 0;
 760                pmc_attrs = NULL;
 761        }
 762
 763        for (i = 0; i < nattrs; i++)
 764                device_create_file(s, &attrs[i]);
 765
 766        if (pmc_attrs)
 767                for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 768                        device_create_file(s, &pmc_attrs[i]);
 769
 770#ifdef CONFIG_PPC64
 771        if (cpu_has_feature(CPU_FTR_MMCRA))
 772                device_create_file(s, &dev_attr_mmcra);
 773
 774        if (cpu_has_feature(CPU_FTR_PURR)) {
 775                if (!firmware_has_feature(FW_FEATURE_LPAR))
 776                        add_write_permission_dev_attr(&dev_attr_purr);
 777                device_create_file(s, &dev_attr_purr);
 778        }
 779
 780        if (cpu_has_feature(CPU_FTR_SPURR))
 781                device_create_file(s, &dev_attr_spurr);
 782
 783        if (cpu_has_feature(CPU_FTR_DSCR))
 784                device_create_file(s, &dev_attr_dscr);
 785
 786        if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 787                device_create_file(s, &dev_attr_pir);
 788
 789        if (cpu_has_feature(CPU_FTR_ARCH_206) &&
 790                !firmware_has_feature(FW_FEATURE_LPAR))
 791                device_create_file(s, &dev_attr_tscr);
 792#endif /* CONFIG_PPC64 */
 793
 794#ifdef CONFIG_PPC_FSL_BOOK3E
 795        if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 796                device_create_file(s, &dev_attr_pw20_state);
 797                device_create_file(s, &dev_attr_pw20_wait_time);
 798
 799                device_create_file(s, &dev_attr_altivec_idle);
 800                device_create_file(s, &dev_attr_altivec_idle_wait_time);
 801        }
 802#endif
 803        cacheinfo_cpu_online(cpu);
 804        return 0;
 805}
 806
 807#ifdef CONFIG_HOTPLUG_CPU
 808static int unregister_cpu_online(unsigned int cpu)
 809{
 810        struct cpu *c = &per_cpu(cpu_devices, cpu);
 811        struct device *s = &c->dev;
 812        struct device_attribute *attrs, *pmc_attrs;
 813        int i, nattrs;
 814
 815        BUG_ON(!c->hotpluggable);
 816
 817#ifdef CONFIG_PPC64
 818        if (cpu_has_feature(CPU_FTR_SMT))
 819                device_remove_file(s, &dev_attr_smt_snooze_delay);
 820#endif
 821
 822        /* PMC stuff */
 823        switch (cur_cpu_spec->pmc_type) {
 824#ifdef HAS_PPC_PMC_IBM
 825        case PPC_PMC_IBM:
 826                attrs = ibm_common_attrs;
 827                nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 828                pmc_attrs = classic_pmc_attrs;
 829                break;
 830#endif /* HAS_PPC_PMC_IBM */
 831#ifdef HAS_PPC_PMC_G4
 832        case PPC_PMC_G4:
 833                attrs = g4_common_attrs;
 834                nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 835                pmc_attrs = classic_pmc_attrs;
 836                break;
 837#endif /* HAS_PPC_PMC_G4 */
 838#ifdef HAS_PPC_PMC_PA6T
 839        case PPC_PMC_PA6T:
 840                /* PA Semi starts counting at PMC0 */
 841                attrs = pa6t_attrs;
 842                nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 843                pmc_attrs = NULL;
 844                break;
 845#endif /* HAS_PPC_PMC_PA6T */
 846        default:
 847                attrs = NULL;
 848                nattrs = 0;
 849                pmc_attrs = NULL;
 850        }
 851
 852        for (i = 0; i < nattrs; i++)
 853                device_remove_file(s, &attrs[i]);
 854
 855        if (pmc_attrs)
 856                for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 857                        device_remove_file(s, &pmc_attrs[i]);
 858
 859#ifdef CONFIG_PPC64
 860        if (cpu_has_feature(CPU_FTR_MMCRA))
 861                device_remove_file(s, &dev_attr_mmcra);
 862
 863        if (cpu_has_feature(CPU_FTR_PURR))
 864                device_remove_file(s, &dev_attr_purr);
 865
 866        if (cpu_has_feature(CPU_FTR_SPURR))
 867                device_remove_file(s, &dev_attr_spurr);
 868
 869        if (cpu_has_feature(CPU_FTR_DSCR))
 870                device_remove_file(s, &dev_attr_dscr);
 871
 872        if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 873                device_remove_file(s, &dev_attr_pir);
 874
 875        if (cpu_has_feature(CPU_FTR_ARCH_206) &&
 876                !firmware_has_feature(FW_FEATURE_LPAR))
 877                device_remove_file(s, &dev_attr_tscr);
 878#endif /* CONFIG_PPC64 */
 879
 880#ifdef CONFIG_PPC_FSL_BOOK3E
 881        if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 882                device_remove_file(s, &dev_attr_pw20_state);
 883                device_remove_file(s, &dev_attr_pw20_wait_time);
 884
 885                device_remove_file(s, &dev_attr_altivec_idle);
 886                device_remove_file(s, &dev_attr_altivec_idle_wait_time);
 887        }
 888#endif
 889        cacheinfo_cpu_offline(cpu);
 890        of_node_put(s->of_node);
 891        s->of_node = NULL;
 892        return 0;
 893}
 894#else /* !CONFIG_HOTPLUG_CPU */
 895#define unregister_cpu_online NULL
 896#endif
 897
 898#ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
 899ssize_t arch_cpu_probe(const char *buf, size_t count)
 900{
 901        if (ppc_md.cpu_probe)
 902                return ppc_md.cpu_probe(buf, count);
 903
 904        return -EINVAL;
 905}
 906
 907ssize_t arch_cpu_release(const char *buf, size_t count)
 908{
 909        if (ppc_md.cpu_release)
 910                return ppc_md.cpu_release(buf, count);
 911
 912        return -EINVAL;
 913}
 914#endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
 915
 916static DEFINE_MUTEX(cpu_mutex);
 917
 918int cpu_add_dev_attr(struct device_attribute *attr)
 919{
 920        int cpu;
 921
 922        mutex_lock(&cpu_mutex);
 923
 924        for_each_possible_cpu(cpu) {
 925                device_create_file(get_cpu_device(cpu), attr);
 926        }
 927
 928        mutex_unlock(&cpu_mutex);
 929        return 0;
 930}
 931EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
 932
 933int cpu_add_dev_attr_group(struct attribute_group *attrs)
 934{
 935        int cpu;
 936        struct device *dev;
 937        int ret;
 938
 939        mutex_lock(&cpu_mutex);
 940
 941        for_each_possible_cpu(cpu) {
 942                dev = get_cpu_device(cpu);
 943                ret = sysfs_create_group(&dev->kobj, attrs);
 944                WARN_ON(ret != 0);
 945        }
 946
 947        mutex_unlock(&cpu_mutex);
 948        return 0;
 949}
 950EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
 951
 952
 953void cpu_remove_dev_attr(struct device_attribute *attr)
 954{
 955        int cpu;
 956
 957        mutex_lock(&cpu_mutex);
 958
 959        for_each_possible_cpu(cpu) {
 960                device_remove_file(get_cpu_device(cpu), attr);
 961        }
 962
 963        mutex_unlock(&cpu_mutex);
 964}
 965EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
 966
 967void cpu_remove_dev_attr_group(struct attribute_group *attrs)
 968{
 969        int cpu;
 970        struct device *dev;
 971
 972        mutex_lock(&cpu_mutex);
 973
 974        for_each_possible_cpu(cpu) {
 975                dev = get_cpu_device(cpu);
 976                sysfs_remove_group(&dev->kobj, attrs);
 977        }
 978
 979        mutex_unlock(&cpu_mutex);
 980}
 981EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
 982
 983
 984/* NUMA stuff */
 985
 986#ifdef CONFIG_NUMA
 987static void register_nodes(void)
 988{
 989        int i;
 990
 991        for (i = 0; i < MAX_NUMNODES; i++)
 992                register_one_node(i);
 993}
 994
 995int sysfs_add_device_to_node(struct device *dev, int nid)
 996{
 997        struct node *node = node_devices[nid];
 998        return sysfs_create_link(&node->dev.kobj, &dev->kobj,
 999                        kobject_name(&dev->kobj));
1000}

1001EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
1002
1003void sysfs_remove_device_from_node(struct device *dev, int nid)
1004{
1005        struct node *node = node_devices[nid];
1006        sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1007}
1008EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1009
1010#else
1011static void register_nodes(void)
1012{
1013        return;
1014}
1015
1016#endif
1017
1018/* Only valid if CPU is present. */
1019static ssize_t show_physical_id(struct device *dev,
1020                                struct device_attribute *attr, char *buf)
1021{
1022        struct cpu *cpu = container_of(dev, struct cpu, dev);
1023
1024        return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1025}
1026static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1027
1028static int __init topology_init(void)
1029{
1030        int cpu, r;
1031
1032        register_nodes();
1033
1034        for_each_possible_cpu(cpu) {
1035                struct cpu *c = &per_cpu(cpu_devices, cpu);
1036
1037                /*
1038                 * For now, we just see if the system supports making
1039                 * the RTAS calls for CPU hotplug.  But, there may be a
1040                 * more comprehensive way to do this for an individual
1041                 * CPU.  For instance, the boot cpu might never be valid
1042                 * for hotplugging.
1043                 */
1044                if (ppc_md.cpu_die)
1045                        c->hotpluggable = 1;
1046
1047                if (cpu_online(cpu) || c->hotpluggable) {
1048                        register_cpu(c, cpu);
1049
1050                        device_create_file(&c->dev, &dev_attr_physical_id);
1051                }
1052        }
1053        r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1054                              register_cpu_online, unregister_cpu_online);
1055        WARN_ON(r < 0);
1056#ifdef CONFIG_PPC64
1057        sysfs_create_dscr_default();
1058#endif /* CONFIG_PPC64 */
1059
1060        return 0;
1061}
1062subsys_initcall(topology_init);
1063