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6
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
14#include <linux/export.h>
15#include <linux/nmi.h>
16
17#include <asm/cpufeature.h>
18#include <asm/hardirq.h>
19#include <asm/intel-family.h>
20#include <asm/apic.h>
21
22#include "../perf_event.h"
23
24
25
26
27static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
28{
29 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
30 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
31 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
32 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
33 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
34 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
35 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
36 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300,
37};
38
39static struct event_constraint intel_core_event_constraints[] __read_mostly =
40{
41 INTEL_EVENT_CONSTRAINT(0x11, 0x2),
42 INTEL_EVENT_CONSTRAINT(0x12, 0x2),
43 INTEL_EVENT_CONSTRAINT(0x13, 0x2),
44 INTEL_EVENT_CONSTRAINT(0x14, 0x1),
45 INTEL_EVENT_CONSTRAINT(0x19, 0x2),
46 INTEL_EVENT_CONSTRAINT(0xc1, 0x1),
47 EVENT_CONSTRAINT_END
48};
49
50static struct event_constraint intel_core2_event_constraints[] __read_mostly =
51{
52 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
53 FIXED_EVENT_CONSTRAINT(0x003c, 1),
54 FIXED_EVENT_CONSTRAINT(0x0300, 2),
55 INTEL_EVENT_CONSTRAINT(0x10, 0x1),
56 INTEL_EVENT_CONSTRAINT(0x11, 0x2),
57 INTEL_EVENT_CONSTRAINT(0x12, 0x2),
58 INTEL_EVENT_CONSTRAINT(0x13, 0x2),
59 INTEL_EVENT_CONSTRAINT(0x14, 0x1),
60 INTEL_EVENT_CONSTRAINT(0x18, 0x1),
61 INTEL_EVENT_CONSTRAINT(0x19, 0x2),
62 INTEL_EVENT_CONSTRAINT(0xa1, 0x1),
63 INTEL_EVENT_CONSTRAINT(0xc9, 0x1),
64 INTEL_EVENT_CONSTRAINT(0xcb, 0x1),
65 EVENT_CONSTRAINT_END
66};
67
68static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
69{
70 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
71 FIXED_EVENT_CONSTRAINT(0x003c, 1),
72 FIXED_EVENT_CONSTRAINT(0x0300, 2),
73 INTEL_EVENT_CONSTRAINT(0x40, 0x3),
74 INTEL_EVENT_CONSTRAINT(0x41, 0x3),
75 INTEL_EVENT_CONSTRAINT(0x42, 0x3),
76 INTEL_EVENT_CONSTRAINT(0x43, 0x3),
77 INTEL_EVENT_CONSTRAINT(0x48, 0x3),
78 INTEL_EVENT_CONSTRAINT(0x4e, 0x3),
79 INTEL_EVENT_CONSTRAINT(0x51, 0x3),
80 INTEL_EVENT_CONSTRAINT(0x63, 0x3),
81 EVENT_CONSTRAINT_END
82};
83
84static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
85{
86
87 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
88 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
89 EVENT_EXTRA_END
90};
91
92static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
93{
94 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
95 FIXED_EVENT_CONSTRAINT(0x003c, 1),
96 FIXED_EVENT_CONSTRAINT(0x0300, 2),
97 INTEL_EVENT_CONSTRAINT(0x51, 0x3),
98 INTEL_EVENT_CONSTRAINT(0x60, 0x1),
99 INTEL_EVENT_CONSTRAINT(0x63, 0x3),
100 INTEL_EVENT_CONSTRAINT(0xb3, 0x1),
101 EVENT_CONSTRAINT_END
102};
103
104static struct event_constraint intel_snb_event_constraints[] __read_mostly =
105{
106 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
107 FIXED_EVENT_CONSTRAINT(0x003c, 1),
108 FIXED_EVENT_CONSTRAINT(0x0300, 2),
109 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
110 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
111 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4),
112 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4),
113 INTEL_EVENT_CONSTRAINT(0x48, 0x4),
114 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2),
115 INTEL_EVENT_CONSTRAINT(0xcd, 0x8),
116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4),
118
119
120
121
122
123 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),
124 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),
125 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),
126 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),
127
128 EVENT_CONSTRAINT_END
129};
130
131static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
132{
133 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
134 FIXED_EVENT_CONSTRAINT(0x003c, 1),
135 FIXED_EVENT_CONSTRAINT(0x0300, 2),
136 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
137 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf),
138 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf),
139 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
140 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
141 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
142 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf),
143 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
144 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
145 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2),
146
147
148
149
150
151 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),
152 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),
153 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),
154 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),
155
156 EVENT_CONSTRAINT_END
157};
158
159static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
160{
161
162 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
163 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
164 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
165 EVENT_EXTRA_END
166};
167
168static struct event_constraint intel_v1_event_constraints[] __read_mostly =
169{
170 EVENT_CONSTRAINT_END
171};
172
173static struct event_constraint intel_gen_event_constraints[] __read_mostly =
174{
175 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
176 FIXED_EVENT_CONSTRAINT(0x003c, 1),
177 FIXED_EVENT_CONSTRAINT(0x0300, 2),
178 EVENT_CONSTRAINT_END
179};
180
181static struct event_constraint intel_slm_event_constraints[] __read_mostly =
182{
183 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
184 FIXED_EVENT_CONSTRAINT(0x003c, 1),
185 FIXED_EVENT_CONSTRAINT(0x0300, 2),
186 EVENT_CONSTRAINT_END
187};
188
189static struct event_constraint intel_skl_event_constraints[] = {
190 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
191 FIXED_EVENT_CONSTRAINT(0x003c, 1),
192 FIXED_EVENT_CONSTRAINT(0x0300, 2),
193 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2),
194
195
196
197
198 INTEL_EVENT_CONSTRAINT(0xd0, 0xf),
199 INTEL_EVENT_CONSTRAINT(0xd1, 0xf),
200 INTEL_EVENT_CONSTRAINT(0xd2, 0xf),
201 INTEL_EVENT_CONSTRAINT(0xcd, 0xf),
202 INTEL_EVENT_CONSTRAINT(0xc6, 0xf),
203
204 EVENT_CONSTRAINT_END
205};
206
207static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
208 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
209 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
210 EVENT_EXTRA_END
211};
212
213static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
214
215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
216 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
218 EVENT_EXTRA_END
219};
220
221static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
222
223 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
224 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
225 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
226 EVENT_EXTRA_END
227};
228
229static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
230 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
231 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
232 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
233
234
235
236
237 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
238 EVENT_EXTRA_END
239};
240
241EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
242EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
243EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
244
245static struct attribute *nhm_events_attrs[] = {
246 EVENT_PTR(mem_ld_nhm),
247 NULL,
248};
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
265 "event=0x3c,umask=0x0",
266 "event=0x3c,umask=0x0,any=1");
267EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
268EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
269 "event=0xe,umask=0x1");
270EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
271 "event=0xc2,umask=0x2");
272EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
273 "event=0x9c,umask=0x1");
274EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
275 "event=0xd,umask=0x3,cmask=1",
276 "event=0xd,umask=0x3,cmask=1,any=1");
277EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
278 "4", "2");
279
280static struct attribute *snb_events_attrs[] = {
281 EVENT_PTR(mem_ld_snb),
282 EVENT_PTR(mem_st_snb),
283 EVENT_PTR(td_slots_issued),
284 EVENT_PTR(td_slots_retired),
285 EVENT_PTR(td_fetch_bubbles),
286 EVENT_PTR(td_total_slots),
287 EVENT_PTR(td_total_slots_scale),
288 EVENT_PTR(td_recovery_bubbles),
289 EVENT_PTR(td_recovery_bubbles_scale),
290 NULL,
291};
292
293static struct event_constraint intel_hsw_event_constraints[] = {
294 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
295 FIXED_EVENT_CONSTRAINT(0x003c, 1),
296 FIXED_EVENT_CONSTRAINT(0x0300, 2),
297 INTEL_UEVENT_CONSTRAINT(0x148, 0x4),
298 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2),
299 INTEL_EVENT_CONSTRAINT(0xcd, 0x8),
300
301 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
302
303 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
304
305 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
306
307
308
309
310
311 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),
312 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),
313 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),
314 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),
315
316 EVENT_CONSTRAINT_END
317};
318
319static struct event_constraint intel_bdw_event_constraints[] = {
320 FIXED_EVENT_CONSTRAINT(0x00c0, 0),
321 FIXED_EVENT_CONSTRAINT(0x003c, 1),
322 FIXED_EVENT_CONSTRAINT(0x0300, 2),
323 INTEL_UEVENT_CONSTRAINT(0x148, 0x4),
324 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4),
325
326
327
328 INTEL_EVENT_CONSTRAINT(0xd0, 0xf),
329 INTEL_EVENT_CONSTRAINT(0xd1, 0xf),
330 INTEL_EVENT_CONSTRAINT(0xd2, 0xf),
331 INTEL_EVENT_CONSTRAINT(0xcd, 0xf),
332 EVENT_CONSTRAINT_END
333};
334
335static u64 intel_pmu_event_map(int hw_event)
336{
337 return intel_perfmon_event_map[hw_event];
338}
339
340
341
342
343
344
345
346
347
348
349#define SKL_DEMAND_DATA_RD BIT_ULL(0)
350#define SKL_DEMAND_RFO BIT_ULL(1)
351#define SKL_ANY_RESPONSE BIT_ULL(16)
352#define SKL_SUPPLIER_NONE BIT_ULL(17)
353#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
354#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
355#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
356#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
357#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
358 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
359 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
360 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
361#define SKL_SPL_HIT BIT_ULL(30)
362#define SKL_SNOOP_NONE BIT_ULL(31)
363#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
364#define SKL_SNOOP_MISS BIT_ULL(33)
365#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
366#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
367#define SKL_SNOOP_HITM BIT_ULL(36)
368#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
369#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
370 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
371 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
372 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
373#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
374#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
375 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
376 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
377 SKL_SNOOP_HITM|SKL_SPL_HIT)
378#define SKL_DEMAND_WRITE SKL_DEMAND_RFO
379#define SKL_LLC_ACCESS SKL_ANY_RESPONSE
380#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
381 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
382 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
383
384static __initconst const u64 skl_hw_cache_event_ids
385 [PERF_COUNT_HW_CACHE_MAX]
386 [PERF_COUNT_HW_CACHE_OP_MAX]
387 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
388{
389 [ C(L1D ) ] = {
390 [ C(OP_READ) ] = {
391 [ C(RESULT_ACCESS) ] = 0x81d0,
392 [ C(RESULT_MISS) ] = 0x151,
393 },
394 [ C(OP_WRITE) ] = {
395 [ C(RESULT_ACCESS) ] = 0x82d0,
396 [ C(RESULT_MISS) ] = 0x0,
397 },
398 [ C(OP_PREFETCH) ] = {
399 [ C(RESULT_ACCESS) ] = 0x0,
400 [ C(RESULT_MISS) ] = 0x0,
401 },
402 },
403 [ C(L1I ) ] = {
404 [ C(OP_READ) ] = {
405 [ C(RESULT_ACCESS) ] = 0x0,
406 [ C(RESULT_MISS) ] = 0x283,
407 },
408 [ C(OP_WRITE) ] = {
409 [ C(RESULT_ACCESS) ] = -1,
410 [ C(RESULT_MISS) ] = -1,
411 },
412 [ C(OP_PREFETCH) ] = {
413 [ C(RESULT_ACCESS) ] = 0x0,
414 [ C(RESULT_MISS) ] = 0x0,
415 },
416 },
417 [ C(LL ) ] = {
418 [ C(OP_READ) ] = {
419 [ C(RESULT_ACCESS) ] = 0x1b7,
420 [ C(RESULT_MISS) ] = 0x1b7,
421 },
422 [ C(OP_WRITE) ] = {
423 [ C(RESULT_ACCESS) ] = 0x1b7,
424 [ C(RESULT_MISS) ] = 0x1b7,
425 },
426 [ C(OP_PREFETCH) ] = {
427 [ C(RESULT_ACCESS) ] = 0x0,
428 [ C(RESULT_MISS) ] = 0x0,
429 },
430 },
431 [ C(DTLB) ] = {
432 [ C(OP_READ) ] = {
433 [ C(RESULT_ACCESS) ] = 0x81d0,
434 [ C(RESULT_MISS) ] = 0xe08,
435 },
436 [ C(OP_WRITE) ] = {
437 [ C(RESULT_ACCESS) ] = 0x82d0,
438 [ C(RESULT_MISS) ] = 0xe49,
439 },
440 [ C(OP_PREFETCH) ] = {
441 [ C(RESULT_ACCESS) ] = 0x0,
442 [ C(RESULT_MISS) ] = 0x0,
443 },
444 },
445 [ C(ITLB) ] = {
446 [ C(OP_READ) ] = {
447 [ C(RESULT_ACCESS) ] = 0x2085,
448 [ C(RESULT_MISS) ] = 0xe85,
449 },
450 [ C(OP_WRITE) ] = {
451 [ C(RESULT_ACCESS) ] = -1,
452 [ C(RESULT_MISS) ] = -1,
453 },
454 [ C(OP_PREFETCH) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
457 },
458 },
459 [ C(BPU ) ] = {
460 [ C(OP_READ) ] = {
461 [ C(RESULT_ACCESS) ] = 0xc4,
462 [ C(RESULT_MISS) ] = 0xc5,
463 },
464 [ C(OP_WRITE) ] = {
465 [ C(RESULT_ACCESS) ] = -1,
466 [ C(RESULT_MISS) ] = -1,
467 },
468 [ C(OP_PREFETCH) ] = {
469 [ C(RESULT_ACCESS) ] = -1,
470 [ C(RESULT_MISS) ] = -1,
471 },
472 },
473 [ C(NODE) ] = {
474 [ C(OP_READ) ] = {
475 [ C(RESULT_ACCESS) ] = 0x1b7,
476 [ C(RESULT_MISS) ] = 0x1b7,
477 },
478 [ C(OP_WRITE) ] = {
479 [ C(RESULT_ACCESS) ] = 0x1b7,
480 [ C(RESULT_MISS) ] = 0x1b7,
481 },
482 [ C(OP_PREFETCH) ] = {
483 [ C(RESULT_ACCESS) ] = 0x0,
484 [ C(RESULT_MISS) ] = 0x0,
485 },
486 },
487};
488
489static __initconst const u64 skl_hw_cache_extra_regs
490 [PERF_COUNT_HW_CACHE_MAX]
491 [PERF_COUNT_HW_CACHE_OP_MAX]
492 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
493{
494 [ C(LL ) ] = {
495 [ C(OP_READ) ] = {
496 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
497 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
498 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
499 SKL_L3_MISS|SKL_ANY_SNOOP|
500 SKL_SUPPLIER_NONE,
501 },
502 [ C(OP_WRITE) ] = {
503 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
504 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
505 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
506 SKL_L3_MISS|SKL_ANY_SNOOP|
507 SKL_SUPPLIER_NONE,
508 },
509 [ C(OP_PREFETCH) ] = {
510 [ C(RESULT_ACCESS) ] = 0x0,
511 [ C(RESULT_MISS) ] = 0x0,
512 },
513 },
514 [ C(NODE) ] = {
515 [ C(OP_READ) ] = {
516 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
517 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
518 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
519 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
520 },
521 [ C(OP_WRITE) ] = {
522 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
523 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
524 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
525 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = 0x0,
529 [ C(RESULT_MISS) ] = 0x0,
530 },
531 },
532};
533
534#define SNB_DMND_DATA_RD (1ULL << 0)
535#define SNB_DMND_RFO (1ULL << 1)
536#define SNB_DMND_IFETCH (1ULL << 2)
537#define SNB_DMND_WB (1ULL << 3)
538#define SNB_PF_DATA_RD (1ULL << 4)
539#define SNB_PF_RFO (1ULL << 5)
540#define SNB_PF_IFETCH (1ULL << 6)
541#define SNB_LLC_DATA_RD (1ULL << 7)
542#define SNB_LLC_RFO (1ULL << 8)
543#define SNB_LLC_IFETCH (1ULL << 9)
544#define SNB_BUS_LOCKS (1ULL << 10)
545#define SNB_STRM_ST (1ULL << 11)
546#define SNB_OTHER (1ULL << 15)
547#define SNB_RESP_ANY (1ULL << 16)
548#define SNB_NO_SUPP (1ULL << 17)
549#define SNB_LLC_HITM (1ULL << 18)
550#define SNB_LLC_HITE (1ULL << 19)
551#define SNB_LLC_HITS (1ULL << 20)
552#define SNB_LLC_HITF (1ULL << 21)
553#define SNB_LOCAL (1ULL << 22)
554#define SNB_REMOTE (0xffULL << 23)
555#define SNB_SNP_NONE (1ULL << 31)
556#define SNB_SNP_NOT_NEEDED (1ULL << 32)
557#define SNB_SNP_MISS (1ULL << 33)
558#define SNB_NO_FWD (1ULL << 34)
559#define SNB_SNP_FWD (1ULL << 35)
560#define SNB_HITM (1ULL << 36)
561#define SNB_NON_DRAM (1ULL << 37)
562
563#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
564#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
565#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
566
567#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
568 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
569 SNB_HITM)
570
571#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
572#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
573
574#define SNB_L3_ACCESS SNB_RESP_ANY
575#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
576
577static __initconst const u64 snb_hw_cache_extra_regs
578 [PERF_COUNT_HW_CACHE_MAX]
579 [PERF_COUNT_HW_CACHE_OP_MAX]
580 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
581{
582 [ C(LL ) ] = {
583 [ C(OP_READ) ] = {
584 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
585 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
586 },
587 [ C(OP_WRITE) ] = {
588 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
589 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
590 },
591 [ C(OP_PREFETCH) ] = {
592 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
593 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
594 },
595 },
596 [ C(NODE) ] = {
597 [ C(OP_READ) ] = {
598 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
599 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
600 },
601 [ C(OP_WRITE) ] = {
602 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
603 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
604 },
605 [ C(OP_PREFETCH) ] = {
606 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
607 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
608 },
609 },
610};
611
612static __initconst const u64 snb_hw_cache_event_ids
613 [PERF_COUNT_HW_CACHE_MAX]
614 [PERF_COUNT_HW_CACHE_OP_MAX]
615 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
616{
617 [ C(L1D) ] = {
618 [ C(OP_READ) ] = {
619 [ C(RESULT_ACCESS) ] = 0xf1d0,
620 [ C(RESULT_MISS) ] = 0x0151,
621 },
622 [ C(OP_WRITE) ] = {
623 [ C(RESULT_ACCESS) ] = 0xf2d0,
624 [ C(RESULT_MISS) ] = 0x0851,
625 },
626 [ C(OP_PREFETCH) ] = {
627 [ C(RESULT_ACCESS) ] = 0x0,
628 [ C(RESULT_MISS) ] = 0x024e,
629 },
630 },
631 [ C(L1I ) ] = {
632 [ C(OP_READ) ] = {
633 [ C(RESULT_ACCESS) ] = 0x0,
634 [ C(RESULT_MISS) ] = 0x0280,
635 },
636 [ C(OP_WRITE) ] = {
637 [ C(RESULT_ACCESS) ] = -1,
638 [ C(RESULT_MISS) ] = -1,
639 },
640 [ C(OP_PREFETCH) ] = {
641 [ C(RESULT_ACCESS) ] = 0x0,
642 [ C(RESULT_MISS) ] = 0x0,
643 },
644 },
645 [ C(LL ) ] = {
646 [ C(OP_READ) ] = {
647
648 [ C(RESULT_ACCESS) ] = 0x01b7,
649
650 [ C(RESULT_MISS) ] = 0x01b7,
651 },
652 [ C(OP_WRITE) ] = {
653
654 [ C(RESULT_ACCESS) ] = 0x01b7,
655
656 [ C(RESULT_MISS) ] = 0x01b7,
657 },
658 [ C(OP_PREFETCH) ] = {
659
660 [ C(RESULT_ACCESS) ] = 0x01b7,
661
662 [ C(RESULT_MISS) ] = 0x01b7,
663 },
664 },
665 [ C(DTLB) ] = {
666 [ C(OP_READ) ] = {
667 [ C(RESULT_ACCESS) ] = 0x81d0,
668 [ C(RESULT_MISS) ] = 0x0108,
669 },
670 [ C(OP_WRITE) ] = {
671 [ C(RESULT_ACCESS) ] = 0x82d0,
672 [ C(RESULT_MISS) ] = 0x0149,
673 },
674 [ C(OP_PREFETCH) ] = {
675 [ C(RESULT_ACCESS) ] = 0x0,
676 [ C(RESULT_MISS) ] = 0x0,
677 },
678 },
679 [ C(ITLB) ] = {
680 [ C(OP_READ) ] = {
681 [ C(RESULT_ACCESS) ] = 0x1085,
682 [ C(RESULT_MISS) ] = 0x0185,
683 },
684 [ C(OP_WRITE) ] = {
685 [ C(RESULT_ACCESS) ] = -1,
686 [ C(RESULT_MISS) ] = -1,
687 },
688 [ C(OP_PREFETCH) ] = {
689 [ C(RESULT_ACCESS) ] = -1,
690 [ C(RESULT_MISS) ] = -1,
691 },
692 },
693 [ C(BPU ) ] = {
694 [ C(OP_READ) ] = {
695 [ C(RESULT_ACCESS) ] = 0x00c4,
696 [ C(RESULT_MISS) ] = 0x00c5,
697 },
698 [ C(OP_WRITE) ] = {
699 [ C(RESULT_ACCESS) ] = -1,
700 [ C(RESULT_MISS) ] = -1,
701 },
702 [ C(OP_PREFETCH) ] = {
703 [ C(RESULT_ACCESS) ] = -1,
704 [ C(RESULT_MISS) ] = -1,
705 },
706 },
707 [ C(NODE) ] = {
708 [ C(OP_READ) ] = {
709 [ C(RESULT_ACCESS) ] = 0x01b7,
710 [ C(RESULT_MISS) ] = 0x01b7,
711 },
712 [ C(OP_WRITE) ] = {
713 [ C(RESULT_ACCESS) ] = 0x01b7,
714 [ C(RESULT_MISS) ] = 0x01b7,
715 },
716 [ C(OP_PREFETCH) ] = {
717 [ C(RESULT_ACCESS) ] = 0x01b7,
718 [ C(RESULT_MISS) ] = 0x01b7,
719 },
720 },
721
722};
723
724
725
726
727
728
729
730
731
732
733#define HSW_DEMAND_DATA_RD BIT_ULL(0)
734#define HSW_DEMAND_RFO BIT_ULL(1)
735#define HSW_ANY_RESPONSE BIT_ULL(16)
736#define HSW_SUPPLIER_NONE BIT_ULL(17)
737#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
738#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
739#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
740#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
741#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
742 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
743 HSW_L3_MISS_REMOTE_HOP2P)
744#define HSW_SNOOP_NONE BIT_ULL(31)
745#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
746#define HSW_SNOOP_MISS BIT_ULL(33)
747#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
748#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
749#define HSW_SNOOP_HITM BIT_ULL(36)
750#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
751#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
752 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
753 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
754 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
755#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
756#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
757#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
758#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
759 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
760#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
761
762#define BDW_L3_MISS_LOCAL BIT(26)
763#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
764 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
765 HSW_L3_MISS_REMOTE_HOP2P)
766
767
768static __initconst const u64 hsw_hw_cache_event_ids
769 [PERF_COUNT_HW_CACHE_MAX]
770 [PERF_COUNT_HW_CACHE_OP_MAX]
771 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
772{
773 [ C(L1D ) ] = {
774 [ C(OP_READ) ] = {
775 [ C(RESULT_ACCESS) ] = 0x81d0,
776 [ C(RESULT_MISS) ] = 0x151,
777 },
778 [ C(OP_WRITE) ] = {
779 [ C(RESULT_ACCESS) ] = 0x82d0,
780 [ C(RESULT_MISS) ] = 0x0,
781 },
782 [ C(OP_PREFETCH) ] = {
783 [ C(RESULT_ACCESS) ] = 0x0,
784 [ C(RESULT_MISS) ] = 0x0,
785 },
786 },
787 [ C(L1I ) ] = {
788 [ C(OP_READ) ] = {
789 [ C(RESULT_ACCESS) ] = 0x0,
790 [ C(RESULT_MISS) ] = 0x280,
791 },
792 [ C(OP_WRITE) ] = {
793 [ C(RESULT_ACCESS) ] = -1,
794 [ C(RESULT_MISS) ] = -1,
795 },
796 [ C(OP_PREFETCH) ] = {
797 [ C(RESULT_ACCESS) ] = 0x0,
798 [ C(RESULT_MISS) ] = 0x0,
799 },
800 },
801 [ C(LL ) ] = {
802 [ C(OP_READ) ] = {
803 [ C(RESULT_ACCESS) ] = 0x1b7,
804 [ C(RESULT_MISS) ] = 0x1b7,
805 },
806 [ C(OP_WRITE) ] = {
807 [ C(RESULT_ACCESS) ] = 0x1b7,
808 [ C(RESULT_MISS) ] = 0x1b7,
809 },
810 [ C(OP_PREFETCH) ] = {
811 [ C(RESULT_ACCESS) ] = 0x0,
812 [ C(RESULT_MISS) ] = 0x0,
813 },
814 },
815 [ C(DTLB) ] = {
816 [ C(OP_READ) ] = {
817 [ C(RESULT_ACCESS) ] = 0x81d0,
818 [ C(RESULT_MISS) ] = 0x108,
819 },
820 [ C(OP_WRITE) ] = {
821 [ C(RESULT_ACCESS) ] = 0x82d0,
822 [ C(RESULT_MISS) ] = 0x149,
823 },
824 [ C(OP_PREFETCH) ] = {
825 [ C(RESULT_ACCESS) ] = 0x0,
826 [ C(RESULT_MISS) ] = 0x0,
827 },
828 },
829 [ C(ITLB) ] = {
830 [ C(OP_READ) ] = {
831 [ C(RESULT_ACCESS) ] = 0x6085,
832 [ C(RESULT_MISS) ] = 0x185,
833 },
834 [ C(OP_WRITE) ] = {
835 [ C(RESULT_ACCESS) ] = -1,
836 [ C(RESULT_MISS) ] = -1,
837 },
838 [ C(OP_PREFETCH) ] = {
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
841 },
842 },
843 [ C(BPU ) ] = {
844 [ C(OP_READ) ] = {
845 [ C(RESULT_ACCESS) ] = 0xc4,
846 [ C(RESULT_MISS) ] = 0xc5,
847 },
848 [ C(OP_WRITE) ] = {
849 [ C(RESULT_ACCESS) ] = -1,
850 [ C(RESULT_MISS) ] = -1,
851 },
852 [ C(OP_PREFETCH) ] = {
853 [ C(RESULT_ACCESS) ] = -1,
854 [ C(RESULT_MISS) ] = -1,
855 },
856 },
857 [ C(NODE) ] = {
858 [ C(OP_READ) ] = {
859 [ C(RESULT_ACCESS) ] = 0x1b7,
860 [ C(RESULT_MISS) ] = 0x1b7,
861 },
862 [ C(OP_WRITE) ] = {
863 [ C(RESULT_ACCESS) ] = 0x1b7,
864 [ C(RESULT_MISS) ] = 0x1b7,
865 },
866 [ C(OP_PREFETCH) ] = {
867 [ C(RESULT_ACCESS) ] = 0x0,
868 [ C(RESULT_MISS) ] = 0x0,
869 },
870 },
871};
872
873static __initconst const u64 hsw_hw_cache_extra_regs
874 [PERF_COUNT_HW_CACHE_MAX]
875 [PERF_COUNT_HW_CACHE_OP_MAX]
876 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
877{
878 [ C(LL ) ] = {
879 [ C(OP_READ) ] = {
880 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
881 HSW_LLC_ACCESS,
882 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
883 HSW_L3_MISS|HSW_ANY_SNOOP,
884 },
885 [ C(OP_WRITE) ] = {
886 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
887 HSW_LLC_ACCESS,
888 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
889 HSW_L3_MISS|HSW_ANY_SNOOP,
890 },
891 [ C(OP_PREFETCH) ] = {
892 [ C(RESULT_ACCESS) ] = 0x0,
893 [ C(RESULT_MISS) ] = 0x0,
894 },
895 },
896 [ C(NODE) ] = {
897 [ C(OP_READ) ] = {
898 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
899 HSW_L3_MISS_LOCAL_DRAM|
900 HSW_SNOOP_DRAM,
901 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
902 HSW_L3_MISS_REMOTE|
903 HSW_SNOOP_DRAM,
904 },
905 [ C(OP_WRITE) ] = {
906 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
907 HSW_L3_MISS_LOCAL_DRAM|
908 HSW_SNOOP_DRAM,
909 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
910 HSW_L3_MISS_REMOTE|
911 HSW_SNOOP_DRAM,
912 },
913 [ C(OP_PREFETCH) ] = {
914 [ C(RESULT_ACCESS) ] = 0x0,
915 [ C(RESULT_MISS) ] = 0x0,
916 },
917 },
918};
919
920static __initconst const u64 westmere_hw_cache_event_ids
921 [PERF_COUNT_HW_CACHE_MAX]
922 [PERF_COUNT_HW_CACHE_OP_MAX]
923 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
924{
925 [ C(L1D) ] = {
926 [ C(OP_READ) ] = {
927 [ C(RESULT_ACCESS) ] = 0x010b,
928 [ C(RESULT_MISS) ] = 0x0151,
929 },
930 [ C(OP_WRITE) ] = {
931 [ C(RESULT_ACCESS) ] = 0x020b,
932 [ C(RESULT_MISS) ] = 0x0251,
933 },
934 [ C(OP_PREFETCH) ] = {
935 [ C(RESULT_ACCESS) ] = 0x014e,
936 [ C(RESULT_MISS) ] = 0x024e,
937 },
938 },
939 [ C(L1I ) ] = {
940 [ C(OP_READ) ] = {
941 [ C(RESULT_ACCESS) ] = 0x0380,
942 [ C(RESULT_MISS) ] = 0x0280,
943 },
944 [ C(OP_WRITE) ] = {
945 [ C(RESULT_ACCESS) ] = -1,
946 [ C(RESULT_MISS) ] = -1,
947 },
948 [ C(OP_PREFETCH) ] = {
949 [ C(RESULT_ACCESS) ] = 0x0,
950 [ C(RESULT_MISS) ] = 0x0,
951 },
952 },
953 [ C(LL ) ] = {
954 [ C(OP_READ) ] = {
955
956 [ C(RESULT_ACCESS) ] = 0x01b7,
957
958 [ C(RESULT_MISS) ] = 0x01b7,
959 },
960
961
962
963
964 [ C(OP_WRITE) ] = {
965
966 [ C(RESULT_ACCESS) ] = 0x01b7,
967
968 [ C(RESULT_MISS) ] = 0x01b7,
969 },
970 [ C(OP_PREFETCH) ] = {
971
972 [ C(RESULT_ACCESS) ] = 0x01b7,
973
974 [ C(RESULT_MISS) ] = 0x01b7,
975 },
976 },
977 [ C(DTLB) ] = {
978 [ C(OP_READ) ] = {
979 [ C(RESULT_ACCESS) ] = 0x010b,
980 [ C(RESULT_MISS) ] = 0x0108,
981 },
982 [ C(OP_WRITE) ] = {
983 [ C(RESULT_ACCESS) ] = 0x020b,
984 [ C(RESULT_MISS) ] = 0x010c,
985 },
986 [ C(OP_PREFETCH) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0,
988 [ C(RESULT_MISS) ] = 0x0,
989 },
990 },
991 [ C(ITLB) ] = {
992 [ C(OP_READ) ] = {
993 [ C(RESULT_ACCESS) ] = 0x01c0,
994 [ C(RESULT_MISS) ] = 0x0185,
995 },
996 [ C(OP_WRITE) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
999 },
1000 [ C(OP_PREFETCH) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 },
1005 [ C(BPU ) ] = {
1006 [ C(OP_READ) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x00c4,
1008 [ C(RESULT_MISS) ] = 0x03e8,
1009 },
1010 [ C(OP_WRITE) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1013 },
1014 [ C(OP_PREFETCH) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 },
1019 [ C(NODE) ] = {
1020 [ C(OP_READ) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x01b7,
1022 [ C(RESULT_MISS) ] = 0x01b7,
1023 },
1024 [ C(OP_WRITE) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1027 },
1028 [ C(OP_PREFETCH) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01b7,
1030 [ C(RESULT_MISS) ] = 0x01b7,
1031 },
1032 },
1033};
1034
1035
1036
1037
1038
1039
1040#define NHM_DMND_DATA_RD (1 << 0)
1041#define NHM_DMND_RFO (1 << 1)
1042#define NHM_DMND_IFETCH (1 << 2)
1043#define NHM_DMND_WB (1 << 3)
1044#define NHM_PF_DATA_RD (1 << 4)
1045#define NHM_PF_DATA_RFO (1 << 5)
1046#define NHM_PF_IFETCH (1 << 6)
1047#define NHM_OFFCORE_OTHER (1 << 7)
1048#define NHM_UNCORE_HIT (1 << 8)
1049#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1050#define NHM_OTHER_CORE_HITM (1 << 10)
1051
1052#define NHM_REMOTE_CACHE_FWD (1 << 12)
1053#define NHM_REMOTE_DRAM (1 << 13)
1054#define NHM_LOCAL_DRAM (1 << 14)
1055#define NHM_NON_DRAM (1 << 15)
1056
1057#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1058#define NHM_REMOTE (NHM_REMOTE_DRAM)
1059
1060#define NHM_DMND_READ (NHM_DMND_DATA_RD)
1061#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1062#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1063
1064#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1065#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1066#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1067
1068static __initconst const u64 nehalem_hw_cache_extra_regs
1069 [PERF_COUNT_HW_CACHE_MAX]
1070 [PERF_COUNT_HW_CACHE_OP_MAX]
1071 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1072{
1073 [ C(LL ) ] = {
1074 [ C(OP_READ) ] = {
1075 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1076 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1077 },
1078 [ C(OP_WRITE) ] = {
1079 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1080 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1081 },
1082 [ C(OP_PREFETCH) ] = {
1083 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1084 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1085 },
1086 },
1087 [ C(NODE) ] = {
1088 [ C(OP_READ) ] = {
1089 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1090 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1091 },
1092 [ C(OP_WRITE) ] = {
1093 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1094 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1095 },
1096 [ C(OP_PREFETCH) ] = {
1097 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1098 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1099 },
1100 },
1101};
1102
1103static __initconst const u64 nehalem_hw_cache_event_ids
1104 [PERF_COUNT_HW_CACHE_MAX]
1105 [PERF_COUNT_HW_CACHE_OP_MAX]
1106 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1107{
1108 [ C(L1D) ] = {
1109 [ C(OP_READ) ] = {
1110 [ C(RESULT_ACCESS) ] = 0x010b,
1111 [ C(RESULT_MISS) ] = 0x0151,
1112 },
1113 [ C(OP_WRITE) ] = {
1114 [ C(RESULT_ACCESS) ] = 0x020b,
1115 [ C(RESULT_MISS) ] = 0x0251,
1116 },
1117 [ C(OP_PREFETCH) ] = {
1118 [ C(RESULT_ACCESS) ] = 0x014e,
1119 [ C(RESULT_MISS) ] = 0x024e,
1120 },
1121 },
1122 [ C(L1I ) ] = {
1123 [ C(OP_READ) ] = {
1124 [ C(RESULT_ACCESS) ] = 0x0380,
1125 [ C(RESULT_MISS) ] = 0x0280,
1126 },
1127 [ C(OP_WRITE) ] = {
1128 [ C(RESULT_ACCESS) ] = -1,
1129 [ C(RESULT_MISS) ] = -1,
1130 },
1131 [ C(OP_PREFETCH) ] = {
1132 [ C(RESULT_ACCESS) ] = 0x0,
1133 [ C(RESULT_MISS) ] = 0x0,
1134 },
1135 },
1136 [ C(LL ) ] = {
1137 [ C(OP_READ) ] = {
1138
1139 [ C(RESULT_ACCESS) ] = 0x01b7,
1140
1141 [ C(RESULT_MISS) ] = 0x01b7,
1142 },
1143
1144
1145
1146
1147 [ C(OP_WRITE) ] = {
1148
1149 [ C(RESULT_ACCESS) ] = 0x01b7,
1150
1151 [ C(RESULT_MISS) ] = 0x01b7,
1152 },
1153 [ C(OP_PREFETCH) ] = {
1154
1155 [ C(RESULT_ACCESS) ] = 0x01b7,
1156
1157 [ C(RESULT_MISS) ] = 0x01b7,
1158 },
1159 },
1160 [ C(DTLB) ] = {
1161 [ C(OP_READ) ] = {
1162 [ C(RESULT_ACCESS) ] = 0x0f40,
1163 [ C(RESULT_MISS) ] = 0x0108,
1164 },
1165 [ C(OP_WRITE) ] = {
1166 [ C(RESULT_ACCESS) ] = 0x0f41,
1167 [ C(RESULT_MISS) ] = 0x010c,
1168 },
1169 [ C(OP_PREFETCH) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0,
1171 [ C(RESULT_MISS) ] = 0x0,
1172 },
1173 },
1174 [ C(ITLB) ] = {
1175 [ C(OP_READ) ] = {
1176 [ C(RESULT_ACCESS) ] = 0x01c0,
1177 [ C(RESULT_MISS) ] = 0x20c8,
1178 },
1179 [ C(OP_WRITE) ] = {
1180 [ C(RESULT_ACCESS) ] = -1,
1181 [ C(RESULT_MISS) ] = -1,
1182 },
1183 [ C(OP_PREFETCH) ] = {
1184 [ C(RESULT_ACCESS) ] = -1,
1185 [ C(RESULT_MISS) ] = -1,
1186 },
1187 },
1188 [ C(BPU ) ] = {
1189 [ C(OP_READ) ] = {
1190 [ C(RESULT_ACCESS) ] = 0x00c4,
1191 [ C(RESULT_MISS) ] = 0x03e8,
1192 },
1193 [ C(OP_WRITE) ] = {
1194 [ C(RESULT_ACCESS) ] = -1,
1195 [ C(RESULT_MISS) ] = -1,
1196 },
1197 [ C(OP_PREFETCH) ] = {
1198 [ C(RESULT_ACCESS) ] = -1,
1199 [ C(RESULT_MISS) ] = -1,
1200 },
1201 },
1202 [ C(NODE) ] = {
1203 [ C(OP_READ) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x01b7,
1205 [ C(RESULT_MISS) ] = 0x01b7,
1206 },
1207 [ C(OP_WRITE) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x01b7,
1209 [ C(RESULT_MISS) ] = 0x01b7,
1210 },
1211 [ C(OP_PREFETCH) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x01b7,
1213 [ C(RESULT_MISS) ] = 0x01b7,
1214 },
1215 },
1216};
1217
1218static __initconst const u64 core2_hw_cache_event_ids
1219 [PERF_COUNT_HW_CACHE_MAX]
1220 [PERF_COUNT_HW_CACHE_OP_MAX]
1221 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1222{
1223 [ C(L1D) ] = {
1224 [ C(OP_READ) ] = {
1225 [ C(RESULT_ACCESS) ] = 0x0f40,
1226 [ C(RESULT_MISS) ] = 0x0140,
1227 },
1228 [ C(OP_WRITE) ] = {
1229 [ C(RESULT_ACCESS) ] = 0x0f41,
1230 [ C(RESULT_MISS) ] = 0x0141,
1231 },
1232 [ C(OP_PREFETCH) ] = {
1233 [ C(RESULT_ACCESS) ] = 0x104e,
1234 [ C(RESULT_MISS) ] = 0,
1235 },
1236 },
1237 [ C(L1I ) ] = {
1238 [ C(OP_READ) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x0080,
1240 [ C(RESULT_MISS) ] = 0x0081,
1241 },
1242 [ C(OP_WRITE) ] = {
1243 [ C(RESULT_ACCESS) ] = -1,
1244 [ C(RESULT_MISS) ] = -1,
1245 },
1246 [ C(OP_PREFETCH) ] = {
1247 [ C(RESULT_ACCESS) ] = 0,
1248 [ C(RESULT_MISS) ] = 0,
1249 },
1250 },
1251 [ C(LL ) ] = {
1252 [ C(OP_READ) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x4f29,
1254 [ C(RESULT_MISS) ] = 0x4129,
1255 },
1256 [ C(OP_WRITE) ] = {
1257 [ C(RESULT_ACCESS) ] = 0x4f2A,
1258 [ C(RESULT_MISS) ] = 0x412A,
1259 },
1260 [ C(OP_PREFETCH) ] = {
1261 [ C(RESULT_ACCESS) ] = 0,
1262 [ C(RESULT_MISS) ] = 0,
1263 },
1264 },
1265 [ C(DTLB) ] = {
1266 [ C(OP_READ) ] = {
1267 [ C(RESULT_ACCESS) ] = 0x0f40,
1268 [ C(RESULT_MISS) ] = 0x0208,
1269 },
1270 [ C(OP_WRITE) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x0f41,
1272 [ C(RESULT_MISS) ] = 0x0808,
1273 },
1274 [ C(OP_PREFETCH) ] = {
1275 [ C(RESULT_ACCESS) ] = 0,
1276 [ C(RESULT_MISS) ] = 0,
1277 },
1278 },
1279 [ C(ITLB) ] = {
1280 [ C(OP_READ) ] = {
1281 [ C(RESULT_ACCESS) ] = 0x00c0,
1282 [ C(RESULT_MISS) ] = 0x1282,
1283 },
1284 [ C(OP_WRITE) ] = {
1285 [ C(RESULT_ACCESS) ] = -1,
1286 [ C(RESULT_MISS) ] = -1,
1287 },
1288 [ C(OP_PREFETCH) ] = {
1289 [ C(RESULT_ACCESS) ] = -1,
1290 [ C(RESULT_MISS) ] = -1,
1291 },
1292 },
1293 [ C(BPU ) ] = {
1294 [ C(OP_READ) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x00c4,
1296 [ C(RESULT_MISS) ] = 0x00c5,
1297 },
1298 [ C(OP_WRITE) ] = {
1299 [ C(RESULT_ACCESS) ] = -1,
1300 [ C(RESULT_MISS) ] = -1,
1301 },
1302 [ C(OP_PREFETCH) ] = {
1303 [ C(RESULT_ACCESS) ] = -1,
1304 [ C(RESULT_MISS) ] = -1,
1305 },
1306 },
1307};
1308
1309static __initconst const u64 atom_hw_cache_event_ids
1310 [PERF_COUNT_HW_CACHE_MAX]
1311 [PERF_COUNT_HW_CACHE_OP_MAX]
1312 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1313{
1314 [ C(L1D) ] = {
1315 [ C(OP_READ) ] = {
1316 [ C(RESULT_ACCESS) ] = 0x2140,
1317 [ C(RESULT_MISS) ] = 0,
1318 },
1319 [ C(OP_WRITE) ] = {
1320 [ C(RESULT_ACCESS) ] = 0x2240,
1321 [ C(RESULT_MISS) ] = 0,
1322 },
1323 [ C(OP_PREFETCH) ] = {
1324 [ C(RESULT_ACCESS) ] = 0x0,
1325 [ C(RESULT_MISS) ] = 0,
1326 },
1327 },
1328 [ C(L1I ) ] = {
1329 [ C(OP_READ) ] = {
1330 [ C(RESULT_ACCESS) ] = 0x0380,
1331 [ C(RESULT_MISS) ] = 0x0280,
1332 },
1333 [ C(OP_WRITE) ] = {
1334 [ C(RESULT_ACCESS) ] = -1,
1335 [ C(RESULT_MISS) ] = -1,
1336 },
1337 [ C(OP_PREFETCH) ] = {
1338 [ C(RESULT_ACCESS) ] = 0,
1339 [ C(RESULT_MISS) ] = 0,
1340 },
1341 },
1342 [ C(LL ) ] = {
1343 [ C(OP_READ) ] = {
1344 [ C(RESULT_ACCESS) ] = 0x4f29,
1345 [ C(RESULT_MISS) ] = 0x4129,
1346 },
1347 [ C(OP_WRITE) ] = {
1348 [ C(RESULT_ACCESS) ] = 0x4f2A,
1349 [ C(RESULT_MISS) ] = 0x412A,
1350 },
1351 [ C(OP_PREFETCH) ] = {
1352 [ C(RESULT_ACCESS) ] = 0,
1353 [ C(RESULT_MISS) ] = 0,
1354 },
1355 },
1356 [ C(DTLB) ] = {
1357 [ C(OP_READ) ] = {
1358 [ C(RESULT_ACCESS) ] = 0x2140,
1359 [ C(RESULT_MISS) ] = 0x0508,
1360 },
1361 [ C(OP_WRITE) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x2240,
1363 [ C(RESULT_MISS) ] = 0x0608,
1364 },
1365 [ C(OP_PREFETCH) ] = {
1366 [ C(RESULT_ACCESS) ] = 0,
1367 [ C(RESULT_MISS) ] = 0,
1368 },
1369 },
1370 [ C(ITLB) ] = {
1371 [ C(OP_READ) ] = {
1372 [ C(RESULT_ACCESS) ] = 0x00c0,
1373 [ C(RESULT_MISS) ] = 0x0282,
1374 },
1375 [ C(OP_WRITE) ] = {
1376 [ C(RESULT_ACCESS) ] = -1,
1377 [ C(RESULT_MISS) ] = -1,
1378 },
1379 [ C(OP_PREFETCH) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1382 },
1383 },
1384 [ C(BPU ) ] = {
1385 [ C(OP_READ) ] = {
1386 [ C(RESULT_ACCESS) ] = 0x00c4,
1387 [ C(RESULT_MISS) ] = 0x00c5,
1388 },
1389 [ C(OP_WRITE) ] = {
1390 [ C(RESULT_ACCESS) ] = -1,
1391 [ C(RESULT_MISS) ] = -1,
1392 },
1393 [ C(OP_PREFETCH) ] = {
1394 [ C(RESULT_ACCESS) ] = -1,
1395 [ C(RESULT_MISS) ] = -1,
1396 },
1397 },
1398};
1399
1400EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1401EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1402
1403EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1404 "event=0xca,umask=0x50");
1405EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1406
1407EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1408 "event=0xc2,umask=0x10");
1409
1410EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1411 "event=0xc2,umask=0x10");
1412
1413static struct attribute *slm_events_attrs[] = {
1414 EVENT_PTR(td_total_slots_slm),
1415 EVENT_PTR(td_total_slots_scale_slm),
1416 EVENT_PTR(td_fetch_bubbles_slm),
1417 EVENT_PTR(td_fetch_bubbles_scale_slm),
1418 EVENT_PTR(td_slots_issued_slm),
1419 EVENT_PTR(td_slots_retired_slm),
1420 NULL
1421};
1422
1423static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1424{
1425
1426 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1427 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1428 EVENT_EXTRA_END
1429};
1430
1431#define SLM_DMND_READ SNB_DMND_DATA_RD
1432#define SLM_DMND_WRITE SNB_DMND_RFO
1433#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1434
1435#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1436#define SLM_LLC_ACCESS SNB_RESP_ANY
1437#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1438
1439static __initconst const u64 slm_hw_cache_extra_regs
1440 [PERF_COUNT_HW_CACHE_MAX]
1441 [PERF_COUNT_HW_CACHE_OP_MAX]
1442 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1443{
1444 [ C(LL ) ] = {
1445 [ C(OP_READ) ] = {
1446 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1447 [ C(RESULT_MISS) ] = 0,
1448 },
1449 [ C(OP_WRITE) ] = {
1450 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1451 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1452 },
1453 [ C(OP_PREFETCH) ] = {
1454 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1455 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1456 },
1457 },
1458};
1459
1460static __initconst const u64 slm_hw_cache_event_ids
1461 [PERF_COUNT_HW_CACHE_MAX]
1462 [PERF_COUNT_HW_CACHE_OP_MAX]
1463 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1464{
1465 [ C(L1D) ] = {
1466 [ C(OP_READ) ] = {
1467 [ C(RESULT_ACCESS) ] = 0,
1468 [ C(RESULT_MISS) ] = 0x0104,
1469 },
1470 [ C(OP_WRITE) ] = {
1471 [ C(RESULT_ACCESS) ] = 0,
1472 [ C(RESULT_MISS) ] = 0,
1473 },
1474 [ C(OP_PREFETCH) ] = {
1475 [ C(RESULT_ACCESS) ] = 0,
1476 [ C(RESULT_MISS) ] = 0,
1477 },
1478 },
1479 [ C(L1I ) ] = {
1480 [ C(OP_READ) ] = {
1481 [ C(RESULT_ACCESS) ] = 0x0380,
1482 [ C(RESULT_MISS) ] = 0x0280,
1483 },
1484 [ C(OP_WRITE) ] = {
1485 [ C(RESULT_ACCESS) ] = -1,
1486 [ C(RESULT_MISS) ] = -1,
1487 },
1488 [ C(OP_PREFETCH) ] = {
1489 [ C(RESULT_ACCESS) ] = 0,
1490 [ C(RESULT_MISS) ] = 0,
1491 },
1492 },
1493 [ C(LL ) ] = {
1494 [ C(OP_READ) ] = {
1495
1496 [ C(RESULT_ACCESS) ] = 0x01b7,
1497 [ C(RESULT_MISS) ] = 0,
1498 },
1499 [ C(OP_WRITE) ] = {
1500
1501 [ C(RESULT_ACCESS) ] = 0x01b7,
1502
1503 [ C(RESULT_MISS) ] = 0x01b7,
1504 },
1505 [ C(OP_PREFETCH) ] = {
1506
1507 [ C(RESULT_ACCESS) ] = 0x01b7,
1508
1509 [ C(RESULT_MISS) ] = 0x01b7,
1510 },
1511 },
1512 [ C(DTLB) ] = {
1513 [ C(OP_READ) ] = {
1514 [ C(RESULT_ACCESS) ] = 0,
1515 [ C(RESULT_MISS) ] = 0x0804,
1516 },
1517 [ C(OP_WRITE) ] = {
1518 [ C(RESULT_ACCESS) ] = 0,
1519 [ C(RESULT_MISS) ] = 0,
1520 },
1521 [ C(OP_PREFETCH) ] = {
1522 [ C(RESULT_ACCESS) ] = 0,
1523 [ C(RESULT_MISS) ] = 0,
1524 },
1525 },
1526 [ C(ITLB) ] = {
1527 [ C(OP_READ) ] = {
1528 [ C(RESULT_ACCESS) ] = 0x00c0,
1529 [ C(RESULT_MISS) ] = 0x40205,
1530 },
1531 [ C(OP_WRITE) ] = {
1532 [ C(RESULT_ACCESS) ] = -1,
1533 [ C(RESULT_MISS) ] = -1,
1534 },
1535 [ C(OP_PREFETCH) ] = {
1536 [ C(RESULT_ACCESS) ] = -1,
1537 [ C(RESULT_MISS) ] = -1,
1538 },
1539 },
1540 [ C(BPU ) ] = {
1541 [ C(OP_READ) ] = {
1542 [ C(RESULT_ACCESS) ] = 0x00c4,
1543 [ C(RESULT_MISS) ] = 0x00c5,
1544 },
1545 [ C(OP_WRITE) ] = {
1546 [ C(RESULT_ACCESS) ] = -1,
1547 [ C(RESULT_MISS) ] = -1,
1548 },
1549 [ C(OP_PREFETCH) ] = {
1550 [ C(RESULT_ACCESS) ] = -1,
1551 [ C(RESULT_MISS) ] = -1,
1552 },
1553 },
1554};
1555
1556EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1557EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1558
1559EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1560
1561EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1562
1563EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1564
1565EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1566
1567static struct attribute *glm_events_attrs[] = {
1568 EVENT_PTR(td_total_slots_glm),
1569 EVENT_PTR(td_total_slots_scale_glm),
1570 EVENT_PTR(td_fetch_bubbles_glm),
1571 EVENT_PTR(td_recovery_bubbles_glm),
1572 EVENT_PTR(td_slots_issued_glm),
1573 EVENT_PTR(td_slots_retired_glm),
1574 NULL
1575};
1576
1577static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1578
1579 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1580 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1581 EVENT_EXTRA_END
1582};
1583
1584#define GLM_DEMAND_DATA_RD BIT_ULL(0)
1585#define GLM_DEMAND_RFO BIT_ULL(1)
1586#define GLM_ANY_RESPONSE BIT_ULL(16)
1587#define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1588#define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1589#define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1590#define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1591#define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1592#define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1593#define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1594
1595static __initconst const u64 glm_hw_cache_event_ids
1596 [PERF_COUNT_HW_CACHE_MAX]
1597 [PERF_COUNT_HW_CACHE_OP_MAX]
1598 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1599 [C(L1D)] = {
1600 [C(OP_READ)] = {
1601 [C(RESULT_ACCESS)] = 0x81d0,
1602 [C(RESULT_MISS)] = 0x0,
1603 },
1604 [C(OP_WRITE)] = {
1605 [C(RESULT_ACCESS)] = 0x82d0,
1606 [C(RESULT_MISS)] = 0x0,
1607 },
1608 [C(OP_PREFETCH)] = {
1609 [C(RESULT_ACCESS)] = 0x0,
1610 [C(RESULT_MISS)] = 0x0,
1611 },
1612 },
1613 [C(L1I)] = {
1614 [C(OP_READ)] = {
1615 [C(RESULT_ACCESS)] = 0x0380,
1616 [C(RESULT_MISS)] = 0x0280,
1617 },
1618 [C(OP_WRITE)] = {
1619 [C(RESULT_ACCESS)] = -1,
1620 [C(RESULT_MISS)] = -1,
1621 },
1622 [C(OP_PREFETCH)] = {
1623 [C(RESULT_ACCESS)] = 0x0,
1624 [C(RESULT_MISS)] = 0x0,
1625 },
1626 },
1627 [C(LL)] = {
1628 [C(OP_READ)] = {
1629 [C(RESULT_ACCESS)] = 0x1b7,
1630 [C(RESULT_MISS)] = 0x1b7,
1631 },
1632 [C(OP_WRITE)] = {
1633 [C(RESULT_ACCESS)] = 0x1b7,
1634 [C(RESULT_MISS)] = 0x1b7,
1635 },
1636 [C(OP_PREFETCH)] = {
1637 [C(RESULT_ACCESS)] = 0x1b7,
1638 [C(RESULT_MISS)] = 0x1b7,
1639 },
1640 },
1641 [C(DTLB)] = {
1642 [C(OP_READ)] = {
1643 [C(RESULT_ACCESS)] = 0x81d0,
1644 [C(RESULT_MISS)] = 0x0,
1645 },
1646 [C(OP_WRITE)] = {
1647 [C(RESULT_ACCESS)] = 0x82d0,
1648 [C(RESULT_MISS)] = 0x0,
1649 },
1650 [C(OP_PREFETCH)] = {
1651 [C(RESULT_ACCESS)] = 0x0,
1652 [C(RESULT_MISS)] = 0x0,
1653 },
1654 },
1655 [C(ITLB)] = {
1656 [C(OP_READ)] = {
1657 [C(RESULT_ACCESS)] = 0x00c0,
1658 [C(RESULT_MISS)] = 0x0481,
1659 },
1660 [C(OP_WRITE)] = {
1661 [C(RESULT_ACCESS)] = -1,
1662 [C(RESULT_MISS)] = -1,
1663 },
1664 [C(OP_PREFETCH)] = {
1665 [C(RESULT_ACCESS)] = -1,
1666 [C(RESULT_MISS)] = -1,
1667 },
1668 },
1669 [C(BPU)] = {
1670 [C(OP_READ)] = {
1671 [C(RESULT_ACCESS)] = 0x00c4,
1672 [C(RESULT_MISS)] = 0x00c5,
1673 },
1674 [C(OP_WRITE)] = {
1675 [C(RESULT_ACCESS)] = -1,
1676 [C(RESULT_MISS)] = -1,
1677 },
1678 [C(OP_PREFETCH)] = {
1679 [C(RESULT_ACCESS)] = -1,
1680 [C(RESULT_MISS)] = -1,
1681 },
1682 },
1683};
1684
1685static __initconst const u64 glm_hw_cache_extra_regs
1686 [PERF_COUNT_HW_CACHE_MAX]
1687 [PERF_COUNT_HW_CACHE_OP_MAX]
1688 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1689 [C(LL)] = {
1690 [C(OP_READ)] = {
1691 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1692 GLM_LLC_ACCESS,
1693 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1694 GLM_LLC_MISS,
1695 },
1696 [C(OP_WRITE)] = {
1697 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1698 GLM_LLC_ACCESS,
1699 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1700 GLM_LLC_MISS,
1701 },
1702 [C(OP_PREFETCH)] = {
1703 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1704 GLM_LLC_ACCESS,
1705 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1706 GLM_LLC_MISS,
1707 },
1708 },
1709};
1710
1711static __initconst const u64 glp_hw_cache_event_ids
1712 [PERF_COUNT_HW_CACHE_MAX]
1713 [PERF_COUNT_HW_CACHE_OP_MAX]
1714 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1715 [C(L1D)] = {
1716 [C(OP_READ)] = {
1717 [C(RESULT_ACCESS)] = 0x81d0,
1718 [C(RESULT_MISS)] = 0x0,
1719 },
1720 [C(OP_WRITE)] = {
1721 [C(RESULT_ACCESS)] = 0x82d0,
1722 [C(RESULT_MISS)] = 0x0,
1723 },
1724 [C(OP_PREFETCH)] = {
1725 [C(RESULT_ACCESS)] = 0x0,
1726 [C(RESULT_MISS)] = 0x0,
1727 },
1728 },
1729 [C(L1I)] = {
1730 [C(OP_READ)] = {
1731 [C(RESULT_ACCESS)] = 0x0380,
1732 [C(RESULT_MISS)] = 0x0280,
1733 },
1734 [C(OP_WRITE)] = {
1735 [C(RESULT_ACCESS)] = -1,
1736 [C(RESULT_MISS)] = -1,
1737 },
1738 [C(OP_PREFETCH)] = {
1739 [C(RESULT_ACCESS)] = 0x0,
1740 [C(RESULT_MISS)] = 0x0,
1741 },
1742 },
1743 [C(LL)] = {
1744 [C(OP_READ)] = {
1745 [C(RESULT_ACCESS)] = 0x1b7,
1746 [C(RESULT_MISS)] = 0x1b7,
1747 },
1748 [C(OP_WRITE)] = {
1749 [C(RESULT_ACCESS)] = 0x1b7,
1750 [C(RESULT_MISS)] = 0x1b7,
1751 },
1752 [C(OP_PREFETCH)] = {
1753 [C(RESULT_ACCESS)] = 0x0,
1754 [C(RESULT_MISS)] = 0x0,
1755 },
1756 },
1757 [C(DTLB)] = {
1758 [C(OP_READ)] = {
1759 [C(RESULT_ACCESS)] = 0x81d0,
1760 [C(RESULT_MISS)] = 0xe08,
1761 },
1762 [C(OP_WRITE)] = {
1763 [C(RESULT_ACCESS)] = 0x82d0,
1764 [C(RESULT_MISS)] = 0xe49,
1765 },
1766 [C(OP_PREFETCH)] = {
1767 [C(RESULT_ACCESS)] = 0x0,
1768 [C(RESULT_MISS)] = 0x0,
1769 },
1770 },
1771 [C(ITLB)] = {
1772 [C(OP_READ)] = {
1773 [C(RESULT_ACCESS)] = 0x00c0,
1774 [C(RESULT_MISS)] = 0x0481,
1775 },
1776 [C(OP_WRITE)] = {
1777 [C(RESULT_ACCESS)] = -1,
1778 [C(RESULT_MISS)] = -1,
1779 },
1780 [C(OP_PREFETCH)] = {
1781 [C(RESULT_ACCESS)] = -1,
1782 [C(RESULT_MISS)] = -1,
1783 },
1784 },
1785 [C(BPU)] = {
1786 [C(OP_READ)] = {
1787 [C(RESULT_ACCESS)] = 0x00c4,
1788 [C(RESULT_MISS)] = 0x00c5,
1789 },
1790 [C(OP_WRITE)] = {
1791 [C(RESULT_ACCESS)] = -1,
1792 [C(RESULT_MISS)] = -1,
1793 },
1794 [C(OP_PREFETCH)] = {
1795 [C(RESULT_ACCESS)] = -1,
1796 [C(RESULT_MISS)] = -1,
1797 },
1798 },
1799};
1800
1801static __initconst const u64 glp_hw_cache_extra_regs
1802 [PERF_COUNT_HW_CACHE_MAX]
1803 [PERF_COUNT_HW_CACHE_OP_MAX]
1804 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1805 [C(LL)] = {
1806 [C(OP_READ)] = {
1807 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1808 GLM_LLC_ACCESS,
1809 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1810 GLM_LLC_MISS,
1811 },
1812 [C(OP_WRITE)] = {
1813 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1814 GLM_LLC_ACCESS,
1815 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1816 GLM_LLC_MISS,
1817 },
1818 [C(OP_PREFETCH)] = {
1819 [C(RESULT_ACCESS)] = 0x0,
1820 [C(RESULT_MISS)] = 0x0,
1821 },
1822 },
1823};
1824
1825#define KNL_OT_L2_HITE BIT_ULL(19)
1826#define KNL_OT_L2_HITF BIT_ULL(20)
1827#define KNL_MCDRAM_LOCAL BIT_ULL(21)
1828#define KNL_MCDRAM_FAR BIT_ULL(22)
1829#define KNL_DDR_LOCAL BIT_ULL(23)
1830#define KNL_DDR_FAR BIT_ULL(24)
1831#define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1832 KNL_DDR_LOCAL | KNL_DDR_FAR)
1833#define KNL_L2_READ SLM_DMND_READ
1834#define KNL_L2_WRITE SLM_DMND_WRITE
1835#define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1836#define KNL_L2_ACCESS SLM_LLC_ACCESS
1837#define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1838 KNL_DRAM_ANY | SNB_SNP_ANY | \
1839 SNB_NON_DRAM)
1840
1841static __initconst const u64 knl_hw_cache_extra_regs
1842 [PERF_COUNT_HW_CACHE_MAX]
1843 [PERF_COUNT_HW_CACHE_OP_MAX]
1844 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1845 [C(LL)] = {
1846 [C(OP_READ)] = {
1847 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1848 [C(RESULT_MISS)] = 0,
1849 },
1850 [C(OP_WRITE)] = {
1851 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1852 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1853 },
1854 [C(OP_PREFETCH)] = {
1855 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1856 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1857 },
1858 },
1859};
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874static void __intel_pmu_disable_all(void)
1875{
1876 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1877
1878 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1879
1880 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1881 intel_pmu_disable_bts();
1882
1883 intel_pmu_pebs_disable_all();
1884}
1885
1886static void intel_pmu_disable_all(void)
1887{
1888 __intel_pmu_disable_all();
1889 intel_pmu_lbr_disable_all();
1890}
1891
1892static void __intel_pmu_enable_all(int added, bool pmi)
1893{
1894 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1895
1896 intel_pmu_pebs_enable_all();
1897 intel_pmu_lbr_enable_all(pmi);
1898 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1899 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1900
1901 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1902 struct perf_event *event =
1903 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1904
1905 if (WARN_ON_ONCE(!event))
1906 return;
1907
1908 intel_pmu_enable_bts(event->hw.config);
1909 }
1910}
1911
1912static void intel_pmu_enable_all(int added)
1913{
1914 __intel_pmu_enable_all(added, false);
1915}
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931static void intel_pmu_nhm_workaround(void)
1932{
1933 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1934 static const unsigned long nhm_magic[4] = {
1935 0x4300B5,
1936 0x4300D2,
1937 0x4300B1,
1938 0x4300B1
1939 };
1940 struct perf_event *event;
1941 int i;
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965 for (i = 0; i < 4; i++) {
1966 event = cpuc->events[i];
1967 if (event)
1968 x86_perf_event_update(event);
1969 }
1970
1971 for (i = 0; i < 4; i++) {
1972 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1973 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1974 }
1975
1976 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1977 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
1978
1979 for (i = 0; i < 4; i++) {
1980 event = cpuc->events[i];
1981
1982 if (event) {
1983 x86_perf_event_set_period(event);
1984 __x86_pmu_enable_event(&event->hw,
1985 ARCH_PERFMON_EVENTSEL_ENABLE);
1986 } else
1987 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
1988 }
1989}
1990
1991static void intel_pmu_nhm_enable_all(int added)
1992{
1993 if (added)
1994 intel_pmu_nhm_workaround();
1995 intel_pmu_enable_all(added);
1996}
1997
1998static inline u64 intel_pmu_get_status(void)
1999{
2000 u64 status;
2001
2002 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2003
2004 return status;
2005}
2006
2007static inline void intel_pmu_ack_status(u64 ack)
2008{
2009 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2010}
2011
2012static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
2013{
2014 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2015 u64 ctrl_val, mask;
2016
2017 mask = 0xfULL << (idx * 4);
2018
2019 rdmsrl(hwc->config_base, ctrl_val);
2020 ctrl_val &= ~mask;
2021 wrmsrl(hwc->config_base, ctrl_val);
2022}
2023
2024static inline bool event_is_checkpointed(struct perf_event *event)
2025{
2026 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2027}
2028
2029static void intel_pmu_disable_event(struct perf_event *event)
2030{
2031 struct hw_perf_event *hwc = &event->hw;
2032 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2033
2034 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2035 intel_pmu_disable_bts();
2036 intel_pmu_drain_bts_buffer();
2037 return;
2038 }
2039
2040 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
2041 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2042 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
2043
2044 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
2045 intel_pmu_disable_fixed(hwc);
2046 return;
2047 }
2048
2049 x86_pmu_disable_event(event);
2050
2051 if (unlikely(event->attr.precise_ip))
2052 intel_pmu_pebs_disable(event);
2053}
2054
2055static void intel_pmu_del_event(struct perf_event *event)
2056{
2057 if (needs_branch_stack(event))
2058 intel_pmu_lbr_del(event);
2059 if (event->attr.precise_ip)
2060 intel_pmu_pebs_del(event);
2061}
2062
2063static void intel_pmu_read_event(struct perf_event *event)
2064{
2065 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2066 intel_pmu_auto_reload_read(event);
2067 else
2068 x86_perf_event_update(event);
2069}
2070
2071static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
2072{
2073 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2074 u64 ctrl_val, bits, mask;
2075
2076
2077
2078
2079
2080
2081 bits = 0x8ULL;
2082 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2083 bits |= 0x2;
2084 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2085 bits |= 0x1;
2086
2087
2088
2089
2090 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2091 bits |= 0x4;
2092
2093 bits <<= (idx * 4);
2094 mask = 0xfULL << (idx * 4);
2095
2096 rdmsrl(hwc->config_base, ctrl_val);
2097 ctrl_val &= ~mask;
2098 ctrl_val |= bits;
2099 wrmsrl(hwc->config_base, ctrl_val);
2100}
2101
2102static void intel_pmu_enable_event(struct perf_event *event)
2103{
2104 struct hw_perf_event *hwc = &event->hw;
2105 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2106
2107 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
2108 if (!__this_cpu_read(cpu_hw_events.enabled))
2109 return;
2110
2111 intel_pmu_enable_bts(hwc->config);
2112 return;
2113 }
2114
2115 if (event->attr.exclude_host)
2116 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
2117 if (event->attr.exclude_guest)
2118 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
2119
2120 if (unlikely(event_is_checkpointed(event)))
2121 cpuc->intel_cp_status |= (1ull << hwc->idx);
2122
2123 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
2124 intel_pmu_enable_fixed(hwc);
2125 return;
2126 }
2127
2128 if (unlikely(event->attr.precise_ip))
2129 intel_pmu_pebs_enable(event);
2130
2131 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2132}
2133
2134static void intel_pmu_add_event(struct perf_event *event)
2135{
2136 if (event->attr.precise_ip)
2137 intel_pmu_pebs_add(event);
2138 if (needs_branch_stack(event))
2139 intel_pmu_lbr_add(event);
2140}
2141
2142
2143
2144
2145
2146int intel_pmu_save_and_restart(struct perf_event *event)
2147{
2148 x86_perf_event_update(event);
2149
2150
2151
2152
2153
2154
2155 if (unlikely(event_is_checkpointed(event))) {
2156
2157 wrmsrl(event->hw.event_base, 0);
2158 local64_set(&event->hw.prev_count, 0);
2159 }
2160 return x86_perf_event_set_period(event);
2161}
2162
2163static void intel_pmu_reset(void)
2164{
2165 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2166 unsigned long flags;
2167 int idx;
2168
2169 if (!x86_pmu.num_counters)
2170 return;
2171
2172 local_irq_save(flags);
2173
2174 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2175
2176 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2177 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2178 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2179 }
2180 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
2181 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2182
2183 if (ds)
2184 ds->bts_index = ds->bts_buffer_base;
2185
2186
2187 if (x86_pmu.version >= 2) {
2188 intel_pmu_ack_status(intel_pmu_get_status());
2189 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2190 }
2191
2192
2193 if (x86_pmu.lbr_nr) {
2194 update_debugctlmsr(get_debugctlmsr() &
2195 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2196 }
2197
2198 local_irq_restore(flags);
2199}
2200
2201
2202
2203
2204
2205static int intel_pmu_handle_irq(struct pt_regs *regs)
2206{
2207 struct perf_sample_data data;
2208 struct cpu_hw_events *cpuc;
2209 int bit, loops;
2210 u64 status;
2211 int handled;
2212 int pmu_enabled;
2213
2214 cpuc = this_cpu_ptr(&cpu_hw_events);
2215
2216
2217
2218
2219
2220 pmu_enabled = cpuc->enabled;
2221
2222
2223
2224
2225 if (!x86_pmu.late_ack)
2226 apic_write(APIC_LVTPC, APIC_DM_NMI);
2227 intel_bts_disable_local();
2228 cpuc->enabled = 0;
2229 __intel_pmu_disable_all();
2230 handled = intel_pmu_drain_bts_buffer();
2231 handled += intel_bts_interrupt();
2232 status = intel_pmu_get_status();
2233 if (!status)
2234 goto done;
2235
2236 loops = 0;
2237again:
2238 intel_pmu_lbr_read();
2239 intel_pmu_ack_status(status);
2240 if (++loops > 100) {
2241 static bool warned = false;
2242 if (!warned) {
2243 WARN(1, "perfevents: irq loop stuck!\n");
2244 perf_event_print_debug();
2245 warned = true;
2246 }
2247 intel_pmu_reset();
2248 goto done;
2249 }
2250
2251 inc_irq_stat(apic_perf_irqs);
2252
2253
2254
2255
2256
2257
2258 status &= ~(GLOBAL_STATUS_COND_CHG |
2259 GLOBAL_STATUS_ASIF |
2260 GLOBAL_STATUS_LBRS_FROZEN);
2261 if (!status)
2262 goto done;
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2284
2285
2286
2287
2288 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2289 handled++;
2290 x86_pmu.drain_pebs(regs);
2291 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2292 }
2293
2294
2295
2296
2297 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2298 handled++;
2299 intel_pt_interrupt();
2300 }
2301
2302
2303
2304
2305
2306
2307 status |= cpuc->intel_cp_status;
2308
2309 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2310 struct perf_event *event = cpuc->events[bit];
2311
2312 handled++;
2313
2314 if (!test_bit(bit, cpuc->active_mask))
2315 continue;
2316
2317 if (!intel_pmu_save_and_restart(event))
2318 continue;
2319
2320 perf_sample_data_init(&data, 0, event->hw.last_period);
2321
2322 if (has_branch_stack(event))
2323 data.br_stack = &cpuc->lbr_stack;
2324
2325 if (perf_event_overflow(event, &data, regs))
2326 x86_pmu_stop(event, 0);
2327 }
2328
2329
2330
2331
2332 status = intel_pmu_get_status();
2333 if (status)
2334 goto again;
2335
2336done:
2337
2338 cpuc->enabled = pmu_enabled;
2339 if (pmu_enabled)
2340 __intel_pmu_enable_all(0, true);
2341 intel_bts_enable_local();
2342
2343
2344
2345
2346
2347
2348 if (x86_pmu.late_ack)
2349 apic_write(APIC_LVTPC, APIC_DM_NMI);
2350 return handled;
2351}
2352
2353static struct event_constraint *
2354intel_bts_constraints(struct perf_event *event)
2355{
2356 struct hw_perf_event *hwc = &event->hw;
2357 unsigned int hw_event, bts_event;
2358
2359 if (event->attr.freq)
2360 return NULL;
2361
2362 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
2363 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
2364
2365 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
2366 return &bts_constraint;
2367
2368 return NULL;
2369}
2370
2371static int intel_alt_er(int idx, u64 config)
2372{
2373 int alt_idx = idx;
2374
2375 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2376 return idx;
2377
2378 if (idx == EXTRA_REG_RSP_0)
2379 alt_idx = EXTRA_REG_RSP_1;
2380
2381 if (idx == EXTRA_REG_RSP_1)
2382 alt_idx = EXTRA_REG_RSP_0;
2383
2384 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2385 return idx;
2386
2387 return alt_idx;
2388}
2389
2390static void intel_fixup_er(struct perf_event *event, int idx)
2391{
2392 event->hw.extra_reg.idx = idx;
2393
2394 if (idx == EXTRA_REG_RSP_0) {
2395 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2396 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2397 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2398 } else if (idx == EXTRA_REG_RSP_1) {
2399 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2400 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2401 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2402 }
2403}
2404
2405
2406
2407
2408
2409
2410
2411
2412static struct event_constraint *
2413__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2414 struct perf_event *event,
2415 struct hw_perf_event_extra *reg)
2416{
2417 struct event_constraint *c = &emptyconstraint;
2418 struct er_account *era;
2419 unsigned long flags;
2420 int idx = reg->idx;
2421
2422
2423
2424
2425
2426
2427 if (reg->alloc && !cpuc->is_fake)
2428 return NULL;
2429
2430again:
2431 era = &cpuc->shared_regs->regs[idx];
2432
2433
2434
2435
2436 raw_spin_lock_irqsave(&era->lock, flags);
2437
2438 if (!atomic_read(&era->ref) || era->config == reg->config) {
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450 if (!cpuc->is_fake) {
2451 if (idx != reg->idx)
2452 intel_fixup_er(event, idx);
2453
2454
2455
2456
2457
2458
2459
2460 reg->alloc = 1;
2461 }
2462
2463
2464 era->config = reg->config;
2465 era->reg = reg->reg;
2466
2467
2468 atomic_inc(&era->ref);
2469
2470
2471
2472
2473
2474 c = NULL;
2475 } else {
2476 idx = intel_alt_er(idx, reg->config);
2477 if (idx != reg->idx) {
2478 raw_spin_unlock_irqrestore(&era->lock, flags);
2479 goto again;
2480 }
2481 }
2482 raw_spin_unlock_irqrestore(&era->lock, flags);
2483
2484 return c;
2485}
2486
2487static void
2488__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2489 struct hw_perf_event_extra *reg)
2490{
2491 struct er_account *era;
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501 if (!reg->alloc || cpuc->is_fake)
2502 return;
2503
2504 era = &cpuc->shared_regs->regs[reg->idx];
2505
2506
2507 atomic_dec(&era->ref);
2508
2509
2510 reg->alloc = 0;
2511}
2512
2513static struct event_constraint *
2514intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2515 struct perf_event *event)
2516{
2517 struct event_constraint *c = NULL, *d;
2518 struct hw_perf_event_extra *xreg, *breg;
2519
2520 xreg = &event->hw.extra_reg;
2521 if (xreg->idx != EXTRA_REG_NONE) {
2522 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2523 if (c == &emptyconstraint)
2524 return c;
2525 }
2526 breg = &event->hw.branch_reg;
2527 if (breg->idx != EXTRA_REG_NONE) {
2528 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2529 if (d == &emptyconstraint) {
2530 __intel_shared_reg_put_constraints(cpuc, xreg);
2531 c = d;
2532 }
2533 }
2534 return c;
2535}
2536
2537struct event_constraint *
2538x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2539 struct perf_event *event)
2540{
2541 struct event_constraint *c;
2542
2543 if (x86_pmu.event_constraints) {
2544 for_each_event_constraint(c, x86_pmu.event_constraints) {
2545 if ((event->hw.config & c->cmask) == c->code) {
2546 event->hw.flags |= c->flags;
2547 return c;
2548 }
2549 }
2550 }
2551
2552 return &unconstrained;
2553}
2554
2555static struct event_constraint *
2556__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2557 struct perf_event *event)
2558{
2559 struct event_constraint *c;
2560
2561 c = intel_bts_constraints(event);
2562 if (c)
2563 return c;
2564
2565 c = intel_shared_regs_constraints(cpuc, event);
2566 if (c)
2567 return c;
2568
2569 c = intel_pebs_constraints(event);
2570 if (c)
2571 return c;
2572
2573 return x86_get_event_constraints(cpuc, idx, event);
2574}
2575
2576static void
2577intel_start_scheduling(struct cpu_hw_events *cpuc)
2578{
2579 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2580 struct intel_excl_states *xl;
2581 int tid = cpuc->excl_thread_id;
2582
2583
2584
2585
2586 if (cpuc->is_fake || !is_ht_workaround_enabled())
2587 return;
2588
2589
2590
2591
2592 if (WARN_ON_ONCE(!excl_cntrs))
2593 return;
2594
2595 xl = &excl_cntrs->states[tid];
2596
2597 xl->sched_started = true;
2598
2599
2600
2601
2602
2603 raw_spin_lock(&excl_cntrs->lock);
2604}
2605
2606static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2607{
2608 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2609 struct event_constraint *c = cpuc->event_constraint[idx];
2610 struct intel_excl_states *xl;
2611 int tid = cpuc->excl_thread_id;
2612
2613 if (cpuc->is_fake || !is_ht_workaround_enabled())
2614 return;
2615
2616 if (WARN_ON_ONCE(!excl_cntrs))
2617 return;
2618
2619 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2620 return;
2621
2622 xl = &excl_cntrs->states[tid];
2623
2624 lockdep_assert_held(&excl_cntrs->lock);
2625
2626 if (c->flags & PERF_X86_EVENT_EXCL)
2627 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
2628 else
2629 xl->state[cntr] = INTEL_EXCL_SHARED;
2630}
2631
2632static void
2633intel_stop_scheduling(struct cpu_hw_events *cpuc)
2634{
2635 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2636 struct intel_excl_states *xl;
2637 int tid = cpuc->excl_thread_id;
2638
2639
2640
2641
2642 if (cpuc->is_fake || !is_ht_workaround_enabled())
2643 return;
2644
2645
2646
2647 if (WARN_ON_ONCE(!excl_cntrs))
2648 return;
2649
2650 xl = &excl_cntrs->states[tid];
2651
2652 xl->sched_started = false;
2653
2654
2655
2656 raw_spin_unlock(&excl_cntrs->lock);
2657}
2658
2659static struct event_constraint *
2660intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2661 int idx, struct event_constraint *c)
2662{
2663 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2664 struct intel_excl_states *xlo;
2665 int tid = cpuc->excl_thread_id;
2666 int is_excl, i;
2667
2668
2669
2670
2671
2672 if (cpuc->is_fake || !is_ht_workaround_enabled())
2673 return c;
2674
2675
2676
2677
2678 if (WARN_ON_ONCE(!excl_cntrs))
2679 return c;
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
2690 struct event_constraint *cx;
2691
2692
2693
2694
2695 cx = &cpuc->constraint_list[idx];
2696
2697
2698
2699
2700
2701 *cx = *c;
2702
2703
2704
2705
2706
2707 cx->flags |= PERF_X86_EVENT_DYNAMIC;
2708 c = cx;
2709 }
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721 xlo = &excl_cntrs->states[tid ^ 1];
2722
2723
2724
2725
2726
2727 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2728 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2729 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2730 if (!cpuc->n_excl++)
2731 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2732 }
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
2743
2744
2745
2746
2747
2748 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
2749 __clear_bit(i, c->idxmsk);
2750
2751
2752
2753
2754
2755 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
2756 __clear_bit(i, c->idxmsk);
2757 }
2758
2759
2760
2761
2762 c->weight = hweight64(c->idxmsk64);
2763
2764
2765
2766
2767
2768
2769 if (c->weight == 0)
2770 c = &emptyconstraint;
2771
2772 return c;
2773}
2774
2775static struct event_constraint *
2776intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2777 struct perf_event *event)
2778{
2779 struct event_constraint *c1 = NULL;
2780 struct event_constraint *c2;
2781
2782 if (idx >= 0)
2783 c1 = cpuc->event_constraint[idx];
2784
2785
2786
2787
2788
2789
2790 c2 = __intel_get_event_constraints(cpuc, idx, event);
2791 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2792 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2793 c1->weight = c2->weight;
2794 c2 = c1;
2795 }
2796
2797 if (cpuc->excl_cntrs)
2798 return intel_get_excl_constraints(cpuc, event, idx, c2);
2799
2800 return c2;
2801}
2802
2803static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2804 struct perf_event *event)
2805{
2806 struct hw_perf_event *hwc = &event->hw;
2807 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2808 int tid = cpuc->excl_thread_id;
2809 struct intel_excl_states *xl;
2810
2811
2812
2813
2814 if (cpuc->is_fake)
2815 return;
2816
2817 if (WARN_ON_ONCE(!excl_cntrs))
2818 return;
2819
2820 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2821 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2822 if (!--cpuc->n_excl)
2823 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2824 }
2825
2826
2827
2828
2829
2830 if (hwc->idx >= 0) {
2831 xl = &excl_cntrs->states[tid];
2832
2833
2834
2835
2836
2837
2838 if (!xl->sched_started)
2839 raw_spin_lock(&excl_cntrs->lock);
2840
2841 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
2842
2843 if (!xl->sched_started)
2844 raw_spin_unlock(&excl_cntrs->lock);
2845 }
2846}
2847
2848static void
2849intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
2850 struct perf_event *event)
2851{
2852 struct hw_perf_event_extra *reg;
2853
2854 reg = &event->hw.extra_reg;
2855 if (reg->idx != EXTRA_REG_NONE)
2856 __intel_shared_reg_put_constraints(cpuc, reg);
2857
2858 reg = &event->hw.branch_reg;
2859 if (reg->idx != EXTRA_REG_NONE)
2860 __intel_shared_reg_put_constraints(cpuc, reg);
2861}
2862
2863static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2864 struct perf_event *event)
2865{
2866 intel_put_shared_regs_event_constraints(cpuc, event);
2867
2868
2869
2870
2871
2872
2873 if (cpuc->excl_cntrs)
2874 intel_put_excl_constraints(cpuc, event);
2875}
2876
2877static void intel_pebs_aliases_core2(struct perf_event *event)
2878{
2879 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2899
2900 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2901 event->hw.config = alt_config;
2902 }
2903}
2904
2905static void intel_pebs_aliases_snb(struct perf_event *event)
2906{
2907 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
2927
2928 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2929 event->hw.config = alt_config;
2930 }
2931}
2932
2933static void intel_pebs_aliases_precdist(struct perf_event *event)
2934{
2935 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
2951
2952 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2953 event->hw.config = alt_config;
2954 }
2955}
2956
2957static void intel_pebs_aliases_ivb(struct perf_event *event)
2958{
2959 if (event->attr.precise_ip < 3)
2960 return intel_pebs_aliases_snb(event);
2961 return intel_pebs_aliases_precdist(event);
2962}
2963
2964static void intel_pebs_aliases_skl(struct perf_event *event)
2965{
2966 if (event->attr.precise_ip < 3)
2967 return intel_pebs_aliases_core2(event);
2968 return intel_pebs_aliases_precdist(event);
2969}
2970
2971static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
2972{
2973 unsigned long flags = x86_pmu.large_pebs_flags;
2974
2975 if (event->attr.use_clockid)
2976 flags &= ~PERF_SAMPLE_TIME;
2977 if (!event->attr.exclude_kernel)
2978 flags &= ~PERF_SAMPLE_REGS_USER;
2979 if (event->attr.sample_regs_user & ~PEBS_REGS)
2980 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
2981 return flags;
2982}
2983
2984static int intel_pmu_hw_config(struct perf_event *event)
2985{
2986 int ret = x86_pmu_hw_config(event);
2987
2988 if (ret)
2989 return ret;
2990
2991 if (event->attr.precise_ip) {
2992 if (!event->attr.freq) {
2993 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
2994 if (!(event->attr.sample_type &
2995 ~intel_pmu_large_pebs_flags(event)))
2996 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
2997 }
2998 if (x86_pmu.pebs_aliases)
2999 x86_pmu.pebs_aliases(event);
3000 }
3001
3002 if (needs_branch_stack(event)) {
3003 ret = intel_pmu_setup_lbr_filter(event);
3004 if (ret)
3005 return ret;
3006
3007
3008
3009
3010 if (!intel_pmu_has_bts(event)) {
3011
3012 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3013 return -EBUSY;
3014
3015 event->destroy = hw_perf_lbr_event_destroy;
3016 }
3017 }
3018
3019 if (event->attr.type != PERF_TYPE_RAW)
3020 return 0;
3021
3022 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3023 return 0;
3024
3025 if (x86_pmu.version < 3)
3026 return -EINVAL;
3027
3028 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
3029 return -EACCES;
3030
3031 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3032
3033 return 0;
3034}
3035
3036struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
3037{
3038 if (x86_pmu.guest_get_msrs)
3039 return x86_pmu.guest_get_msrs(nr);
3040 *nr = 0;
3041 return NULL;
3042}
3043EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
3044
3045static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3046{
3047 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3048 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3049
3050 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3051 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3052 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3053
3054
3055
3056
3057
3058 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3059 arr[1].host = cpuc->pebs_enabled;
3060 arr[1].guest = 0;
3061
3062 *nr = 2;
3063 return arr;
3064}
3065
3066static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3067{
3068 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3069 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3070 int idx;
3071
3072 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3073 struct perf_event *event = cpuc->events[idx];
3074
3075 arr[idx].msr = x86_pmu_config_addr(idx);
3076 arr[idx].host = arr[idx].guest = 0;
3077
3078 if (!test_bit(idx, cpuc->active_mask))
3079 continue;
3080
3081 arr[idx].host = arr[idx].guest =
3082 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3083
3084 if (event->attr.exclude_host)
3085 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3086 else if (event->attr.exclude_guest)
3087 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3088 }
3089
3090 *nr = x86_pmu.num_counters;
3091 return arr;
3092}
3093
3094static void core_pmu_enable_event(struct perf_event *event)
3095{
3096 if (!event->attr.exclude_host)
3097 x86_pmu_enable_event(event);
3098}
3099
3100static void core_pmu_enable_all(int added)
3101{
3102 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3103 int idx;
3104
3105 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3106 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3107
3108 if (!test_bit(idx, cpuc->active_mask) ||
3109 cpuc->events[idx]->attr.exclude_host)
3110 continue;
3111
3112 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3113 }
3114}
3115
3116static int hsw_hw_config(struct perf_event *event)
3117{
3118 int ret = intel_pmu_hw_config(event);
3119
3120 if (ret)
3121 return ret;
3122 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3123 return 0;
3124 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3125
3126
3127
3128
3129
3130
3131 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3132 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3133 event->attr.precise_ip > 0))
3134 return -EOPNOTSUPP;
3135
3136 if (event_is_checkpointed(event)) {
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146 if (event->attr.sample_period > 0 &&
3147 event->attr.sample_period < 0x7fffffff)
3148 return -EOPNOTSUPP;
3149 }
3150 return 0;
3151}
3152
3153static struct event_constraint counter0_constraint =
3154 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3155
3156static struct event_constraint counter2_constraint =
3157 EVENT_CONSTRAINT(0, 0x4, 0);
3158
3159static struct event_constraint *
3160hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3161 struct perf_event *event)
3162{
3163 struct event_constraint *c;
3164
3165 c = intel_get_event_constraints(cpuc, idx, event);
3166
3167
3168 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3169 if (c->idxmsk64 & (1U << 2))
3170 return &counter2_constraint;
3171 return &emptyconstraint;
3172 }
3173
3174 return c;
3175}
3176
3177static struct event_constraint *
3178glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3179 struct perf_event *event)
3180{
3181 struct event_constraint *c;
3182
3183
3184 if (event->attr.precise_ip == 3)
3185 return &counter0_constraint;
3186
3187 c = intel_get_event_constraints(cpuc, idx, event);
3188
3189 return c;
3190}
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207static u64 bdw_limit_period(struct perf_event *event, u64 left)
3208{
3209 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3210 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3211 if (left < 128)
3212 left = 128;
3213 left &= ~0x3fULL;
3214 }
3215 return left;
3216}
3217
3218PMU_FORMAT_ATTR(event, "config:0-7" );
3219PMU_FORMAT_ATTR(umask, "config:8-15" );
3220PMU_FORMAT_ATTR(edge, "config:18" );
3221PMU_FORMAT_ATTR(pc, "config:19" );
3222PMU_FORMAT_ATTR(any, "config:21" );
3223PMU_FORMAT_ATTR(inv, "config:23" );
3224PMU_FORMAT_ATTR(cmask, "config:24-31" );
3225PMU_FORMAT_ATTR(in_tx, "config:32");
3226PMU_FORMAT_ATTR(in_tx_cp, "config:33");
3227
3228static struct attribute *intel_arch_formats_attr[] = {
3229 &format_attr_event.attr,
3230 &format_attr_umask.attr,
3231 &format_attr_edge.attr,
3232 &format_attr_pc.attr,
3233 &format_attr_inv.attr,
3234 &format_attr_cmask.attr,
3235 NULL,
3236};
3237
3238ssize_t intel_event_sysfs_show(char *page, u64 config)
3239{
3240 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3241
3242 return x86_event_sysfs_show(page, config, event);
3243}
3244
3245struct intel_shared_regs *allocate_shared_regs(int cpu)
3246{
3247 struct intel_shared_regs *regs;
3248 int i;
3249
3250 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3251 GFP_KERNEL, cpu_to_node(cpu));
3252 if (regs) {
3253
3254
3255
3256 for (i = 0; i < EXTRA_REG_MAX; i++)
3257 raw_spin_lock_init(®s->regs[i].lock);
3258
3259 regs->core_id = -1;
3260 }
3261 return regs;
3262}
3263
3264static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3265{
3266 struct intel_excl_cntrs *c;
3267
3268 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3269 GFP_KERNEL, cpu_to_node(cpu));
3270 if (c) {
3271 raw_spin_lock_init(&c->lock);
3272 c->core_id = -1;
3273 }
3274 return c;
3275}
3276
3277static int intel_pmu_cpu_prepare(int cpu)
3278{
3279 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3280
3281 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3282 cpuc->shared_regs = allocate_shared_regs(cpu);
3283 if (!cpuc->shared_regs)
3284 goto err;
3285 }
3286
3287 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3288 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3289
3290 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
3291 if (!cpuc->constraint_list)
3292 goto err_shared_regs;
3293
3294 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
3295 if (!cpuc->excl_cntrs)
3296 goto err_constraint_list;
3297
3298 cpuc->excl_thread_id = 0;
3299 }
3300
3301 return 0;
3302
3303err_constraint_list:
3304 kfree(cpuc->constraint_list);
3305 cpuc->constraint_list = NULL;
3306
3307err_shared_regs:
3308 kfree(cpuc->shared_regs);
3309 cpuc->shared_regs = NULL;
3310
3311err:
3312 return -ENOMEM;
3313}
3314
3315static void flip_smm_bit(void *data)
3316{
3317 unsigned long set = *(unsigned long *)data;
3318
3319 if (set > 0) {
3320 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
3321 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3322 } else {
3323 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
3324 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
3325 }
3326}
3327
3328static void intel_pmu_cpu_starting(int cpu)
3329{
3330 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3331 int core_id = topology_core_id(cpu);
3332 int i;
3333
3334 init_debug_store_on_cpu(cpu);
3335
3336
3337
3338 intel_pmu_lbr_reset();
3339
3340 cpuc->lbr_sel = NULL;
3341
3342 if (x86_pmu.version > 1)
3343 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
3344
3345 if (!cpuc->shared_regs)
3346 return;
3347
3348 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
3349 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3350 struct intel_shared_regs *pc;
3351
3352 pc = per_cpu(cpu_hw_events, i).shared_regs;
3353 if (pc && pc->core_id == core_id) {
3354 cpuc->kfree_on_online[0] = cpuc->shared_regs;
3355 cpuc->shared_regs = pc;
3356 break;
3357 }
3358 }
3359 cpuc->shared_regs->core_id = core_id;
3360 cpuc->shared_regs->refcnt++;
3361 }
3362
3363 if (x86_pmu.lbr_sel_map)
3364 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
3365
3366 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3367 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
3368 struct cpu_hw_events *sibling;
3369 struct intel_excl_cntrs *c;
3370
3371 sibling = &per_cpu(cpu_hw_events, i);
3372 c = sibling->excl_cntrs;
3373 if (c && c->core_id == core_id) {
3374 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3375 cpuc->excl_cntrs = c;
3376 if (!sibling->excl_thread_id)
3377 cpuc->excl_thread_id = 1;
3378 break;
3379 }
3380 }
3381 cpuc->excl_cntrs->core_id = core_id;
3382 cpuc->excl_cntrs->refcnt++;
3383 }
3384}
3385
3386static void free_excl_cntrs(int cpu)
3387{
3388 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3389 struct intel_excl_cntrs *c;
3390
3391 c = cpuc->excl_cntrs;
3392 if (c) {
3393 if (c->core_id == -1 || --c->refcnt == 0)
3394 kfree(c);
3395 cpuc->excl_cntrs = NULL;
3396 kfree(cpuc->constraint_list);
3397 cpuc->constraint_list = NULL;
3398 }
3399}
3400
3401static void intel_pmu_cpu_dying(int cpu)
3402{
3403 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3404 struct intel_shared_regs *pc;
3405
3406 pc = cpuc->shared_regs;
3407 if (pc) {
3408 if (pc->core_id == -1 || --pc->refcnt == 0)
3409 kfree(pc);
3410 cpuc->shared_regs = NULL;
3411 }
3412
3413 free_excl_cntrs(cpu);
3414
3415 fini_debug_store_on_cpu(cpu);
3416}
3417
3418static void intel_pmu_sched_task(struct perf_event_context *ctx,
3419 bool sched_in)
3420{
3421 intel_pmu_pebs_sched_task(ctx, sched_in);
3422 intel_pmu_lbr_sched_task(ctx, sched_in);
3423}
3424
3425PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3426
3427PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3428
3429PMU_FORMAT_ATTR(frontend, "config1:0-23");
3430
3431static struct attribute *intel_arch3_formats_attr[] = {
3432 &format_attr_event.attr,
3433 &format_attr_umask.attr,
3434 &format_attr_edge.attr,
3435 &format_attr_pc.attr,
3436 &format_attr_any.attr,
3437 &format_attr_inv.attr,
3438 &format_attr_cmask.attr,
3439 NULL,
3440};
3441
3442static struct attribute *hsw_format_attr[] = {
3443 &format_attr_in_tx.attr,
3444 &format_attr_in_tx_cp.attr,
3445 &format_attr_offcore_rsp.attr,
3446 &format_attr_ldlat.attr,
3447 NULL
3448};
3449
3450static struct attribute *nhm_format_attr[] = {
3451 &format_attr_offcore_rsp.attr,
3452 &format_attr_ldlat.attr,
3453 NULL
3454};
3455
3456static struct attribute *slm_format_attr[] = {
3457 &format_attr_offcore_rsp.attr,
3458 NULL
3459};
3460
3461static struct attribute *skl_format_attr[] = {
3462 &format_attr_frontend.attr,
3463 NULL,
3464};
3465
3466static __initconst const struct x86_pmu core_pmu = {
3467 .name = "core",
3468 .handle_irq = x86_pmu_handle_irq,
3469 .disable_all = x86_pmu_disable_all,
3470 .enable_all = core_pmu_enable_all,
3471 .enable = core_pmu_enable_event,
3472 .disable = x86_pmu_disable_event,
3473 .hw_config = x86_pmu_hw_config,
3474 .schedule_events = x86_schedule_events,
3475 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3476 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3477 .event_map = intel_pmu_event_map,
3478 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3479 .apic = 1,
3480 .large_pebs_flags = LARGE_PEBS_FLAGS,
3481
3482
3483
3484
3485
3486
3487 .max_period = (1ULL<<31) - 1,
3488 .get_event_constraints = intel_get_event_constraints,
3489 .put_event_constraints = intel_put_event_constraints,
3490 .event_constraints = intel_core_event_constraints,
3491 .guest_get_msrs = core_guest_get_msrs,
3492 .format_attrs = intel_arch_formats_attr,
3493 .events_sysfs_show = intel_event_sysfs_show,
3494
3495
3496
3497
3498
3499
3500
3501 .cpu_prepare = intel_pmu_cpu_prepare,
3502 .cpu_starting = intel_pmu_cpu_starting,
3503 .cpu_dying = intel_pmu_cpu_dying,
3504};
3505
3506static struct attribute *intel_pmu_attrs[];
3507
3508static __initconst const struct x86_pmu intel_pmu = {
3509 .name = "Intel",
3510 .handle_irq = intel_pmu_handle_irq,
3511 .disable_all = intel_pmu_disable_all,
3512 .enable_all = intel_pmu_enable_all,
3513 .enable = intel_pmu_enable_event,
3514 .disable = intel_pmu_disable_event,
3515 .add = intel_pmu_add_event,
3516 .del = intel_pmu_del_event,
3517 .read = intel_pmu_read_event,
3518 .hw_config = intel_pmu_hw_config,
3519 .schedule_events = x86_schedule_events,
3520 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3521 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3522 .event_map = intel_pmu_event_map,
3523 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3524 .apic = 1,
3525 .large_pebs_flags = LARGE_PEBS_FLAGS,
3526
3527
3528
3529
3530
3531 .max_period = (1ULL << 31) - 1,
3532 .get_event_constraints = intel_get_event_constraints,
3533 .put_event_constraints = intel_put_event_constraints,
3534 .pebs_aliases = intel_pebs_aliases_core2,
3535
3536 .format_attrs = intel_arch3_formats_attr,
3537 .events_sysfs_show = intel_event_sysfs_show,
3538
3539 .attrs = intel_pmu_attrs,
3540
3541 .cpu_prepare = intel_pmu_cpu_prepare,
3542 .cpu_starting = intel_pmu_cpu_starting,
3543 .cpu_dying = intel_pmu_cpu_dying,
3544 .guest_get_msrs = intel_guest_get_msrs,
3545 .sched_task = intel_pmu_sched_task,
3546};
3547
3548static __init void intel_clovertown_quirk(void)
3549{
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569 pr_warn("PEBS disabled due to CPU errata\n");
3570 x86_pmu.pebs = 0;
3571 x86_pmu.pebs_constraints = NULL;
3572}
3573
3574static int intel_snb_pebs_broken(int cpu)
3575{
3576 u32 rev = UINT_MAX;
3577
3578 switch (cpu_data(cpu).x86_model) {
3579 case INTEL_FAM6_SANDYBRIDGE:
3580 rev = 0x28;
3581 break;
3582
3583 case INTEL_FAM6_SANDYBRIDGE_X:
3584 switch (cpu_data(cpu).x86_stepping) {
3585 case 6: rev = 0x618; break;
3586 case 7: rev = 0x70c; break;
3587 }
3588 }
3589
3590 return (cpu_data(cpu).microcode < rev);
3591}
3592
3593static void intel_snb_check_microcode(void)
3594{
3595 int pebs_broken = 0;
3596 int cpu;
3597
3598 for_each_online_cpu(cpu) {
3599 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3600 break;
3601 }
3602
3603 if (pebs_broken == x86_pmu.pebs_broken)
3604 return;
3605
3606
3607
3608
3609 if (x86_pmu.pebs_broken) {
3610 pr_info("PEBS enabled due to microcode update\n");
3611 x86_pmu.pebs_broken = 0;
3612 } else {
3613 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3614 x86_pmu.pebs_broken = 1;
3615 }
3616}
3617
3618static bool is_lbr_from(unsigned long msr)
3619{
3620 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
3621
3622 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
3623}
3624
3625
3626
3627
3628
3629static bool check_msr(unsigned long msr, u64 mask)
3630{
3631 u64 val_old, val_new, val_tmp;
3632
3633
3634
3635
3636
3637
3638 if (rdmsrl_safe(msr, &val_old))
3639 return false;
3640
3641
3642
3643
3644 val_tmp = val_old ^ mask;
3645
3646 if (is_lbr_from(msr))
3647 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
3648
3649 if (wrmsrl_safe(msr, val_tmp) ||
3650 rdmsrl_safe(msr, &val_new))
3651 return false;
3652
3653
3654
3655
3656
3657 if (val_new != val_tmp)
3658 return false;
3659
3660 if (is_lbr_from(msr))
3661 val_old = lbr_from_signext_quirk_wr(val_old);
3662
3663
3664
3665
3666 wrmsrl(msr, val_old);
3667
3668 return true;
3669}
3670
3671static __init void intel_sandybridge_quirk(void)
3672{
3673 x86_pmu.check_microcode = intel_snb_check_microcode;
3674 cpus_read_lock();
3675 intel_snb_check_microcode();
3676 cpus_read_unlock();
3677}
3678
3679static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3680 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3681 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3682 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3683 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3684 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3685 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3686 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
3687};
3688
3689static __init void intel_arch_events_quirk(void)
3690{
3691 int bit;
3692
3693
3694 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3695 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
3696 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3697 intel_arch_events_map[bit].name);
3698 }
3699}
3700
3701static __init void intel_nehalem_quirk(void)
3702{
3703 union cpuid10_ebx ebx;
3704
3705 ebx.full = x86_pmu.events_maskl;
3706 if (ebx.split.no_branch_misses_retired) {
3707
3708
3709
3710
3711
3712
3713 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3714 ebx.split.no_branch_misses_retired = 0;
3715 x86_pmu.events_maskl = ebx.full;
3716 pr_info("CPU erratum AAJ80 worked around\n");
3717 }
3718}
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732static __init void intel_ht_bug(void)
3733{
3734 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
3735
3736 x86_pmu.start_scheduling = intel_start_scheduling;
3737 x86_pmu.commit_scheduling = intel_commit_scheduling;
3738 x86_pmu.stop_scheduling = intel_stop_scheduling;
3739}
3740
3741EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3742EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
3743
3744
3745EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3746EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3747EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3748EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3749EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3750EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3751EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3752EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3753EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3754EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3755EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3756EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
3757
3758static struct attribute *hsw_events_attrs[] = {
3759 EVENT_PTR(mem_ld_hsw),
3760 EVENT_PTR(mem_st_hsw),
3761 EVENT_PTR(td_slots_issued),
3762 EVENT_PTR(td_slots_retired),
3763 EVENT_PTR(td_fetch_bubbles),
3764 EVENT_PTR(td_total_slots),
3765 EVENT_PTR(td_total_slots_scale),
3766 EVENT_PTR(td_recovery_bubbles),
3767 EVENT_PTR(td_recovery_bubbles_scale),
3768 NULL
3769};
3770
3771static struct attribute *hsw_tsx_events_attrs[] = {
3772 EVENT_PTR(tx_start),
3773 EVENT_PTR(tx_commit),
3774 EVENT_PTR(tx_abort),
3775 EVENT_PTR(tx_capacity),
3776 EVENT_PTR(tx_conflict),
3777 EVENT_PTR(el_start),
3778 EVENT_PTR(el_commit),
3779 EVENT_PTR(el_abort),
3780 EVENT_PTR(el_capacity),
3781 EVENT_PTR(el_conflict),
3782 EVENT_PTR(cycles_t),
3783 EVENT_PTR(cycles_ct),
3784 NULL
3785};
3786
3787static __init struct attribute **get_hsw_events_attrs(void)
3788{
3789 return boot_cpu_has(X86_FEATURE_RTM) ?
3790 merge_attr(hsw_events_attrs, hsw_tsx_events_attrs) :
3791 hsw_events_attrs;
3792}
3793
3794static ssize_t freeze_on_smi_show(struct device *cdev,
3795 struct device_attribute *attr,
3796 char *buf)
3797{
3798 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
3799}
3800
3801static DEFINE_MUTEX(freeze_on_smi_mutex);
3802
3803static ssize_t freeze_on_smi_store(struct device *cdev,
3804 struct device_attribute *attr,
3805 const char *buf, size_t count)
3806{
3807 unsigned long val;
3808 ssize_t ret;
3809
3810 ret = kstrtoul(buf, 0, &val);
3811 if (ret)
3812 return ret;
3813
3814 if (val > 1)
3815 return -EINVAL;
3816
3817 mutex_lock(&freeze_on_smi_mutex);
3818
3819 if (x86_pmu.attr_freeze_on_smi == val)
3820 goto done;
3821
3822 x86_pmu.attr_freeze_on_smi = val;
3823
3824 get_online_cpus();
3825 on_each_cpu(flip_smm_bit, &val, 1);
3826 put_online_cpus();
3827done:
3828 mutex_unlock(&freeze_on_smi_mutex);
3829
3830 return count;
3831}
3832
3833static DEVICE_ATTR_RW(freeze_on_smi);
3834
3835static ssize_t branches_show(struct device *cdev,
3836 struct device_attribute *attr,
3837 char *buf)
3838{
3839 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
3840}
3841
3842static DEVICE_ATTR_RO(branches);
3843
3844static struct attribute *lbr_attrs[] = {
3845 &dev_attr_branches.attr,
3846 NULL
3847};
3848
3849static char pmu_name_str[30];
3850
3851static ssize_t pmu_name_show(struct device *cdev,
3852 struct device_attribute *attr,
3853 char *buf)
3854{
3855 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
3856}
3857
3858static DEVICE_ATTR_RO(pmu_name);
3859
3860static struct attribute *intel_pmu_caps_attrs[] = {
3861 &dev_attr_pmu_name.attr,
3862 NULL
3863};
3864
3865static struct attribute *intel_pmu_attrs[] = {
3866 &dev_attr_freeze_on_smi.attr,
3867 NULL,
3868};
3869
3870__init int intel_pmu_init(void)
3871{
3872 struct attribute **extra_attr = NULL;
3873 struct attribute **to_free = NULL;
3874 union cpuid10_edx edx;
3875 union cpuid10_eax eax;
3876 union cpuid10_ebx ebx;
3877 struct event_constraint *c;
3878 unsigned int unused;
3879 struct extra_reg *er;
3880 int version, i;
3881 char *name;
3882
3883 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
3884 switch (boot_cpu_data.x86) {
3885 case 0x6:
3886 return p6_pmu_init();
3887 case 0xb:
3888 return knc_pmu_init();
3889 case 0xf:
3890 return p4_pmu_init();
3891 }
3892 return -ENODEV;
3893 }
3894
3895
3896
3897
3898
3899 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3900 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
3901 return -ENODEV;
3902
3903 version = eax.split.version_id;
3904 if (version < 2)
3905 x86_pmu = core_pmu;
3906 else
3907 x86_pmu = intel_pmu;
3908
3909 x86_pmu.version = version;
3910 x86_pmu.num_counters = eax.split.num_counters;
3911 x86_pmu.cntval_bits = eax.split.bit_width;
3912 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
3913
3914 x86_pmu.events_maskl = ebx.full;
3915 x86_pmu.events_mask_len = eax.split.mask_length;
3916
3917 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3918
3919
3920
3921
3922
3923 if (version > 1) {
3924 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
3925
3926 x86_pmu.num_counters_fixed =
3927 max((int)edx.split.num_counters_fixed, assume);
3928 }
3929
3930 if (boot_cpu_has(X86_FEATURE_PDCM)) {
3931 u64 capabilities;
3932
3933 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3934 x86_pmu.intel_cap.capabilities = capabilities;
3935 }
3936
3937 intel_ds_init();
3938
3939 x86_add_quirk(intel_arch_events_quirk);
3940
3941
3942
3943
3944 switch (boot_cpu_data.x86_model) {
3945 case INTEL_FAM6_CORE_YONAH:
3946 pr_cont("Core events, ");
3947 name = "core";
3948 break;
3949
3950 case INTEL_FAM6_CORE2_MEROM:
3951 x86_add_quirk(intel_clovertown_quirk);
3952 case INTEL_FAM6_CORE2_MEROM_L:
3953 case INTEL_FAM6_CORE2_PENRYN:
3954 case INTEL_FAM6_CORE2_DUNNINGTON:
3955 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3956 sizeof(hw_cache_event_ids));
3957
3958 intel_pmu_lbr_init_core();
3959
3960 x86_pmu.event_constraints = intel_core2_event_constraints;
3961 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
3962 pr_cont("Core2 events, ");
3963 name = "core2";
3964 break;
3965
3966 case INTEL_FAM6_NEHALEM:
3967 case INTEL_FAM6_NEHALEM_EP:
3968 case INTEL_FAM6_NEHALEM_EX:
3969 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3970 sizeof(hw_cache_event_ids));
3971 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3972 sizeof(hw_cache_extra_regs));
3973
3974 intel_pmu_lbr_init_nhm();
3975
3976 x86_pmu.event_constraints = intel_nehalem_event_constraints;
3977 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
3978 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
3979 x86_pmu.extra_regs = intel_nehalem_extra_regs;
3980
3981 x86_pmu.cpu_events = nhm_events_attrs;
3982
3983
3984 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3985 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3986
3987 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3988 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
3989
3990 intel_pmu_pebs_data_source_nhm();
3991 x86_add_quirk(intel_nehalem_quirk);
3992 x86_pmu.pebs_no_tlb = 1;
3993 extra_attr = nhm_format_attr;
3994
3995 pr_cont("Nehalem events, ");
3996 name = "nehalem";
3997 break;
3998
3999 case INTEL_FAM6_ATOM_PINEVIEW:
4000 case INTEL_FAM6_ATOM_LINCROFT:
4001 case INTEL_FAM6_ATOM_PENWELL:
4002 case INTEL_FAM6_ATOM_CLOVERVIEW:
4003 case INTEL_FAM6_ATOM_CEDARVIEW:
4004 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
4005 sizeof(hw_cache_event_ids));
4006
4007 intel_pmu_lbr_init_atom();
4008
4009 x86_pmu.event_constraints = intel_gen_event_constraints;
4010 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
4011 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
4012 pr_cont("Atom events, ");
4013 name = "bonnell";
4014 break;
4015
4016 case INTEL_FAM6_ATOM_SILVERMONT1:
4017 case INTEL_FAM6_ATOM_SILVERMONT2:
4018 case INTEL_FAM6_ATOM_AIRMONT:
4019 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
4020 sizeof(hw_cache_event_ids));
4021 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
4022 sizeof(hw_cache_extra_regs));
4023
4024 intel_pmu_lbr_init_slm();
4025
4026 x86_pmu.event_constraints = intel_slm_event_constraints;
4027 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4028 x86_pmu.extra_regs = intel_slm_extra_regs;
4029 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4030 x86_pmu.cpu_events = slm_events_attrs;
4031 extra_attr = slm_format_attr;
4032 pr_cont("Silvermont events, ");
4033 name = "silvermont";
4034 break;
4035
4036 case INTEL_FAM6_ATOM_GOLDMONT:
4037 case INTEL_FAM6_ATOM_DENVERTON:
4038 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
4039 sizeof(hw_cache_event_ids));
4040 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
4041 sizeof(hw_cache_extra_regs));
4042
4043 intel_pmu_lbr_init_skl();
4044
4045 x86_pmu.event_constraints = intel_slm_event_constraints;
4046 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
4047 x86_pmu.extra_regs = intel_glm_extra_regs;
4048
4049
4050
4051
4052
4053 x86_pmu.pebs_aliases = NULL;
4054 x86_pmu.pebs_prec_dist = true;
4055 x86_pmu.lbr_pt_coexist = true;
4056 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4057 x86_pmu.cpu_events = glm_events_attrs;
4058 extra_attr = slm_format_attr;
4059 pr_cont("Goldmont events, ");
4060 name = "goldmont";
4061 break;
4062
4063 case INTEL_FAM6_ATOM_GEMINI_LAKE:
4064 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
4065 sizeof(hw_cache_event_ids));
4066 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
4067 sizeof(hw_cache_extra_regs));
4068
4069 intel_pmu_lbr_init_skl();
4070
4071 x86_pmu.event_constraints = intel_slm_event_constraints;
4072 x86_pmu.pebs_constraints = intel_glp_pebs_event_constraints;
4073 x86_pmu.extra_regs = intel_glm_extra_regs;
4074
4075
4076
4077
4078 x86_pmu.pebs_aliases = NULL;
4079 x86_pmu.pebs_prec_dist = true;
4080 x86_pmu.lbr_pt_coexist = true;
4081 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4082 x86_pmu.get_event_constraints = glp_get_event_constraints;
4083 x86_pmu.cpu_events = glm_events_attrs;
4084
4085 event_attr_td_total_slots_scale_glm.event_str = "4";
4086 extra_attr = slm_format_attr;
4087 pr_cont("Goldmont plus events, ");
4088 name = "goldmont_plus";
4089 break;
4090
4091 case INTEL_FAM6_WESTMERE:
4092 case INTEL_FAM6_WESTMERE_EP:
4093 case INTEL_FAM6_WESTMERE_EX:
4094 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
4095 sizeof(hw_cache_event_ids));
4096 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
4097 sizeof(hw_cache_extra_regs));
4098
4099 intel_pmu_lbr_init_nhm();
4100
4101 x86_pmu.event_constraints = intel_westmere_event_constraints;
4102 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
4103 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
4104 x86_pmu.extra_regs = intel_westmere_extra_regs;
4105 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4106
4107 x86_pmu.cpu_events = nhm_events_attrs;
4108
4109
4110 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4111 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4112
4113 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4114 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
4115
4116 intel_pmu_pebs_data_source_nhm();
4117 extra_attr = nhm_format_attr;
4118 pr_cont("Westmere events, ");
4119 name = "westmere";
4120 break;
4121
4122 case INTEL_FAM6_SANDYBRIDGE:
4123 case INTEL_FAM6_SANDYBRIDGE_X:
4124 x86_add_quirk(intel_sandybridge_quirk);
4125 x86_add_quirk(intel_ht_bug);
4126 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4127 sizeof(hw_cache_event_ids));
4128 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4129 sizeof(hw_cache_extra_regs));
4130
4131 intel_pmu_lbr_init_snb();
4132
4133 x86_pmu.event_constraints = intel_snb_event_constraints;
4134 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
4135 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
4136 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
4137 x86_pmu.extra_regs = intel_snbep_extra_regs;
4138 else
4139 x86_pmu.extra_regs = intel_snb_extra_regs;
4140
4141
4142
4143 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4144 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4145
4146 x86_pmu.cpu_events = snb_events_attrs;
4147
4148
4149 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4150 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4151
4152 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
4153 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
4154
4155 extra_attr = nhm_format_attr;
4156
4157 pr_cont("SandyBridge events, ");
4158 name = "sandybridge";
4159 break;
4160
4161 case INTEL_FAM6_IVYBRIDGE:
4162 case INTEL_FAM6_IVYBRIDGE_X:
4163 x86_add_quirk(intel_ht_bug);
4164 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
4165 sizeof(hw_cache_event_ids));
4166
4167 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108;
4168
4169 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
4170 sizeof(hw_cache_extra_regs));
4171
4172 intel_pmu_lbr_init_snb();
4173
4174 x86_pmu.event_constraints = intel_ivb_event_constraints;
4175 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
4176 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4177 x86_pmu.pebs_prec_dist = true;
4178 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
4179 x86_pmu.extra_regs = intel_snbep_extra_regs;
4180 else
4181 x86_pmu.extra_regs = intel_snb_extra_regs;
4182
4183 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4184 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4185
4186 x86_pmu.cpu_events = snb_events_attrs;
4187
4188
4189 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
4190 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
4191
4192 extra_attr = nhm_format_attr;
4193
4194 pr_cont("IvyBridge events, ");
4195 name = "ivybridge";
4196 break;
4197
4198
4199 case INTEL_FAM6_HASWELL_CORE:
4200 case INTEL_FAM6_HASWELL_X:
4201 case INTEL_FAM6_HASWELL_ULT:
4202 case INTEL_FAM6_HASWELL_GT3E:
4203 x86_add_quirk(intel_ht_bug);
4204 x86_pmu.late_ack = true;
4205 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4206 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4207
4208 intel_pmu_lbr_init_hsw();
4209
4210 x86_pmu.event_constraints = intel_hsw_event_constraints;
4211 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
4212 x86_pmu.extra_regs = intel_snbep_extra_regs;
4213 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4214 x86_pmu.pebs_prec_dist = true;
4215
4216 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4217 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4218
4219 x86_pmu.hw_config = hsw_hw_config;
4220 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4221 x86_pmu.cpu_events = get_hsw_events_attrs();
4222 x86_pmu.lbr_double_abort = true;
4223 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4224 hsw_format_attr : nhm_format_attr;
4225 pr_cont("Haswell events, ");
4226 name = "haswell";
4227 break;
4228
4229 case INTEL_FAM6_BROADWELL_CORE:
4230 case INTEL_FAM6_BROADWELL_XEON_D:
4231 case INTEL_FAM6_BROADWELL_GT3E:
4232 case INTEL_FAM6_BROADWELL_X:
4233 x86_pmu.late_ack = true;
4234 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4235 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4236
4237
4238 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
4239 BDW_L3_MISS|HSW_SNOOP_DRAM;
4240 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
4241 HSW_SNOOP_DRAM;
4242 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
4243 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4244 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
4245 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
4246
4247 intel_pmu_lbr_init_hsw();
4248
4249 x86_pmu.event_constraints = intel_bdw_event_constraints;
4250 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
4251 x86_pmu.extra_regs = intel_snbep_extra_regs;
4252 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
4253 x86_pmu.pebs_prec_dist = true;
4254
4255 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4256 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4257
4258 x86_pmu.hw_config = hsw_hw_config;
4259 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4260 x86_pmu.cpu_events = get_hsw_events_attrs();
4261 x86_pmu.limit_period = bdw_limit_period;
4262 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4263 hsw_format_attr : nhm_format_attr;
4264 pr_cont("Broadwell events, ");
4265 name = "broadwell";
4266 break;
4267
4268 case INTEL_FAM6_XEON_PHI_KNL:
4269 case INTEL_FAM6_XEON_PHI_KNM:
4270 memcpy(hw_cache_event_ids,
4271 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4272 memcpy(hw_cache_extra_regs,
4273 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4274 intel_pmu_lbr_init_knl();
4275
4276 x86_pmu.event_constraints = intel_slm_event_constraints;
4277 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
4278 x86_pmu.extra_regs = intel_knl_extra_regs;
4279
4280
4281 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4282 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4283 extra_attr = slm_format_attr;
4284 pr_cont("Knights Landing/Mill events, ");
4285 name = "knights-landing";
4286 break;
4287
4288 case INTEL_FAM6_SKYLAKE_MOBILE:
4289 case INTEL_FAM6_SKYLAKE_DESKTOP:
4290 case INTEL_FAM6_SKYLAKE_X:
4291 case INTEL_FAM6_KABYLAKE_MOBILE:
4292 case INTEL_FAM6_KABYLAKE_DESKTOP:
4293 x86_pmu.late_ack = true;
4294 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
4295 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
4296 intel_pmu_lbr_init_skl();
4297
4298
4299 event_attr_td_recovery_bubbles.event_str_noht =
4300 "event=0xd,umask=0x1,cmask=1";
4301 event_attr_td_recovery_bubbles.event_str_ht =
4302 "event=0xd,umask=0x1,cmask=1,any=1";
4303
4304 x86_pmu.event_constraints = intel_skl_event_constraints;
4305 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
4306 x86_pmu.extra_regs = intel_skl_extra_regs;
4307 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
4308 x86_pmu.pebs_prec_dist = true;
4309
4310 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
4311 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
4312
4313 x86_pmu.hw_config = hsw_hw_config;
4314 x86_pmu.get_event_constraints = hsw_get_event_constraints;
4315 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
4316 hsw_format_attr : nhm_format_attr;
4317 extra_attr = merge_attr(extra_attr, skl_format_attr);
4318 to_free = extra_attr;
4319 x86_pmu.cpu_events = get_hsw_events_attrs();
4320 intel_pmu_pebs_data_source_skl(
4321 boot_cpu_data.x86_model == INTEL_FAM6_SKYLAKE_X);
4322 pr_cont("Skylake events, ");
4323 name = "skylake";
4324 break;
4325
4326 default:
4327 switch (x86_pmu.version) {
4328 case 1:
4329 x86_pmu.event_constraints = intel_v1_event_constraints;
4330 pr_cont("generic architected perfmon v1, ");
4331 name = "generic_arch_v1";
4332 break;
4333 default:
4334
4335
4336
4337 x86_pmu.event_constraints = intel_gen_event_constraints;
4338 pr_cont("generic architected perfmon, ");
4339 name = "generic_arch_v2+";
4340 break;
4341 }
4342 }
4343
4344 snprintf(pmu_name_str, sizeof pmu_name_str, "%s", name);
4345
4346 if (version >= 2 && extra_attr) {
4347 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
4348 extra_attr);
4349 WARN_ON(!x86_pmu.format_attrs);
4350 }
4351
4352 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
4353 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
4354 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
4355 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
4356 }
4357 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
4358
4359 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
4360 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
4361 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
4362 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
4363 }
4364
4365 x86_pmu.intel_ctrl |=
4366 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
4367
4368 if (x86_pmu.event_constraints) {
4369
4370
4371
4372
4373 for_each_event_constraint(c, x86_pmu.event_constraints) {
4374 if (c->cmask == FIXED_EVENT_FLAGS
4375 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
4376 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
4377 }
4378 c->idxmsk64 &=
4379 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
4380 c->weight = hweight64(c->idxmsk64);
4381 }
4382 }
4383
4384
4385
4386
4387
4388
4389
4390 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
4391 x86_pmu.lbr_nr = 0;
4392 for (i = 0; i < x86_pmu.lbr_nr; i++) {
4393 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
4394 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
4395 x86_pmu.lbr_nr = 0;
4396 }
4397
4398 x86_pmu.caps_attrs = intel_pmu_caps_attrs;
4399
4400 if (x86_pmu.lbr_nr) {
4401 x86_pmu.caps_attrs = merge_attr(x86_pmu.caps_attrs, lbr_attrs);
4402 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
4403 }
4404
4405
4406
4407
4408
4409
4410 if (x86_pmu.extra_regs) {
4411 for (er = x86_pmu.extra_regs; er->msr; er++) {
4412 er->extra_msr_access = check_msr(er->msr, 0x11UL);
4413
4414 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
4415 x86_pmu.lbr_sel_map = NULL;
4416 }
4417 }
4418
4419
4420 if (x86_pmu.intel_cap.full_width_write) {
4421 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
4422 x86_pmu.perfctr = MSR_IA32_PMC0;
4423 pr_cont("full-width counters, ");
4424 }
4425
4426 kfree(to_free);
4427 return 0;
4428}
4429
4430
4431
4432
4433
4434
4435
4436static __init int fixup_ht_bug(void)
4437{
4438 int c;
4439
4440
4441
4442 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
4443 return 0;
4444
4445 if (topology_max_smt_threads() > 1) {
4446 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
4447 return 0;
4448 }
4449
4450 cpus_read_lock();
4451
4452 hardlockup_detector_perf_stop();
4453
4454 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
4455
4456 x86_pmu.start_scheduling = NULL;
4457 x86_pmu.commit_scheduling = NULL;
4458 x86_pmu.stop_scheduling = NULL;
4459
4460 hardlockup_detector_perf_restart();
4461
4462 for_each_online_cpu(c)
4463 free_excl_cntrs(c);
4464
4465 cpus_read_unlock();
4466 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
4467 return 0;
4468}
4469subsys_initcall(fixup_ht_bug)
4470
