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11#include <linux/suspend.h>
12#include <linux/export.h>
13#include <linux/smp.h>
14#include <linux/perf_event.h>
15#include <linux/tboot.h>
16
17#include <asm/pgtable.h>
18#include <asm/proto.h>
19#include <asm/mtrr.h>
20#include <asm/page.h>
21#include <asm/mce.h>
22#include <asm/suspend.h>
23#include <asm/fpu/internal.h>
24#include <asm/debugreg.h>
25#include <asm/cpu.h>
26#include <asm/mmu_context.h>
27#include <linux/dmi.h>
28
29#ifdef CONFIG_X86_32
30__visible unsigned long saved_context_ebx;
31__visible unsigned long saved_context_esp, saved_context_ebp;
32__visible unsigned long saved_context_esi, saved_context_edi;
33__visible unsigned long saved_context_eflags;
34#endif
35struct saved_context saved_context;
36
37static void msr_save_context(struct saved_context *ctxt)
38{
39 struct saved_msr *msr = ctxt->saved_msrs.array;
40 struct saved_msr *end = msr + ctxt->saved_msrs.num;
41
42 while (msr < end) {
43 msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q);
44 msr++;
45 }
46}
47
48static void msr_restore_context(struct saved_context *ctxt)
49{
50 struct saved_msr *msr = ctxt->saved_msrs.array;
51 struct saved_msr *end = msr + ctxt->saved_msrs.num;
52
53 while (msr < end) {
54 if (msr->valid)
55 wrmsrl(msr->info.msr_no, msr->info.reg.q);
56 msr++;
57 }
58}
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74
75static void __save_processor_state(struct saved_context *ctxt)
76{
77#ifdef CONFIG_X86_32
78 mtrr_save_fixed_ranges(NULL);
79#endif
80 kernel_fpu_begin();
81
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84
85 store_idt(&ctxt->idt);
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92
93 ctxt->gdt_desc.size = GDT_SIZE - 1;
94 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
95
96 store_tr(ctxt->tr);
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101
102#ifdef CONFIG_X86_32_LAZY_GS
103 savesegment(gs, ctxt->gs);
104#endif
105#ifdef CONFIG_X86_64
106 savesegment(gs, ctxt->gs);
107 savesegment(fs, ctxt->fs);
108 savesegment(ds, ctxt->ds);
109 savesegment(es, ctxt->es);
110
111 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
112 rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
113 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
114 mtrr_save_fixed_ranges(NULL);
115
116 rdmsrl(MSR_EFER, ctxt->efer);
117#endif
118
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120
121
122 ctxt->cr0 = read_cr0();
123 ctxt->cr2 = read_cr2();
124 ctxt->cr3 = __read_cr3();
125 ctxt->cr4 = __read_cr4();
126#ifdef CONFIG_X86_64
127 ctxt->cr8 = read_cr8();
128#endif
129 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
130 &ctxt->misc_enable);
131 msr_save_context(ctxt);
132}
133
134
135void save_processor_state(void)
136{
137 __save_processor_state(&saved_context);
138 x86_platform.save_sched_clock_state();
139}
140#ifdef CONFIG_X86_32
141EXPORT_SYMBOL(save_processor_state);
142#endif
143
144static void do_fpu_end(void)
145{
146
147
148
149 kernel_fpu_end();
150}
151
152static void fix_processor_context(void)
153{
154 int cpu = smp_processor_id();
155#ifdef CONFIG_X86_64
156 struct desc_struct *desc = get_cpu_gdt_rw(cpu);
157 tss_desc tss;
158#endif
159
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167 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
168
169#ifdef CONFIG_X86_64
170 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
171 tss.type = 0x9;
172 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
173
174 syscall_init();
175#else
176 if (boot_cpu_has(X86_FEATURE_SEP))
177 enable_sep_cpu();
178#endif
179 load_TR_desc();
180 load_mm_ldt(current->active_mm);
181 initialize_tlbstate_and_flush();
182
183 fpu__resume_cpu();
184
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186 load_fixmap_gdt(cpu);
187}
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196
197static void notrace __restore_processor_state(struct saved_context *ctxt)
198{
199 if (ctxt->misc_enable_saved)
200 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
201
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204
205#ifdef CONFIG_X86_32
206 if (ctxt->cr4)
207 __write_cr4(ctxt->cr4);
208#else
209
210 wrmsrl(MSR_EFER, ctxt->efer);
211 write_cr8(ctxt->cr8);
212 __write_cr4(ctxt->cr4);
213#endif
214 write_cr3(ctxt->cr3);
215 write_cr2(ctxt->cr2);
216 write_cr0(ctxt->cr0);
217
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219 load_idt(&ctxt->idt);
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224
225 loadsegment(ss, __KERNEL_DS);
226 loadsegment(ds, __USER_DS);
227 loadsegment(es, __USER_DS);
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232
233#ifdef CONFIG_X86_64
234 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base);
235#else
236 loadsegment(fs, __KERNEL_PERCPU);
237 loadsegment(gs, __KERNEL_STACK_CANARY);
238#endif
239
240
241 fix_processor_context();
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246
247#ifdef CONFIG_X86_64
248 loadsegment(ds, ctxt->es);
249 loadsegment(es, ctxt->es);
250 loadsegment(fs, ctxt->fs);
251 load_gs_index(ctxt->gs);
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258 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
259 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base);
260#elif defined(CONFIG_X86_32_LAZY_GS)
261 loadsegment(gs, ctxt->gs);
262#endif
263
264 do_fpu_end();
265 tsc_verify_tsc_adjust(true);
266 x86_platform.restore_sched_clock_state();
267 mtrr_bp_restore();
268 perf_restore_debug_store();
269 msr_restore_context(ctxt);
270}
271
272
273void notrace restore_processor_state(void)
274{
275 __restore_processor_state(&saved_context);
276}
277#ifdef CONFIG_X86_32
278EXPORT_SYMBOL(restore_processor_state);
279#endif
280
281#if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
282static void resume_play_dead(void)
283{
284 play_dead_common();
285 tboot_shutdown(TB_SHUTDOWN_WFS);
286 hlt_play_dead();
287}
288
289int hibernate_resume_nonboot_cpu_disable(void)
290{
291 void (*play_dead)(void) = smp_ops.play_dead;
292 int ret;
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303 smp_ops.play_dead = resume_play_dead;
304 ret = disable_nonboot_cpus();
305 smp_ops.play_dead = play_dead;
306 return ret;
307}
308#endif
309
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315static int bsp_check(void)
316{
317 if (cpumask_first(cpu_online_mask) != 0) {
318 pr_warn("CPU0 is offline.\n");
319 return -ENODEV;
320 }
321
322 return 0;
323}
324
325static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
326 void *ptr)
327{
328 int ret = 0;
329
330 switch (action) {
331 case PM_SUSPEND_PREPARE:
332 case PM_HIBERNATION_PREPARE:
333 ret = bsp_check();
334 break;
335#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
336 case PM_RESTORE_PREPARE:
337
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341
342 if (!cpu_online(0))
343 _debug_hotplug_cpu(0, 1);
344 break;
345 case PM_POST_RESTORE:
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369 _debug_hotplug_cpu(0, 0);
370 break;
371#endif
372 default:
373 break;
374 }
375 return notifier_from_errno(ret);
376}
377
378static int __init bsp_pm_check_init(void)
379{
380
381
382
383
384
385 pm_notifier(bsp_pm_callback, -INT_MAX);
386 return 0;
387}
388
389core_initcall(bsp_pm_check_init);
390
391static int msr_init_context(const u32 *msr_id, const int total_num)
392{
393 int i = 0;
394 struct saved_msr *msr_array;
395
396 if (saved_context.saved_msrs.array || saved_context.saved_msrs.num > 0) {
397 pr_err("x86/pm: MSR quirk already applied, please check your DMI match table.\n");
398 return -EINVAL;
399 }
400
401 msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
402 if (!msr_array) {
403 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
404 return -ENOMEM;
405 }
406
407 for (i = 0; i < total_num; i++) {
408 msr_array[i].info.msr_no = msr_id[i];
409 msr_array[i].valid = false;
410 msr_array[i].info.reg.q = 0;
411 }
412 saved_context.saved_msrs.num = total_num;
413 saved_context.saved_msrs.array = msr_array;
414
415 return 0;
416}
417
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428static int msr_initialize_bdw(const struct dmi_system_id *d)
429{
430
431 u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
432
433 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
434 return msr_init_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
435}
436
437static const struct dmi_system_id msr_save_dmi_table[] = {
438 {
439 .callback = msr_initialize_bdw,
440 .ident = "BROADWELL BDX_EP",
441 .matches = {
442 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
443 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
444 },
445 },
446 {}
447};
448
449static int pm_check_save_msr(void)
450{
451 dmi_check_system(msr_save_dmi_table);
452 return 0;
453}
454
455device_initcall(pm_check_save_msr);
456