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41#include <linux/sched/mm.h>
42#include <linux/highmem.h>
43#include <linux/debugfs.h>
44#include <linux/bug.h>
45#include <linux/vmalloc.h>
46#include <linux/export.h>
47#include <linux/init.h>
48#include <linux/gfp.h>
49#include <linux/memblock.h>
50#include <linux/seq_file.h>
51#include <linux/crash_dump.h>
52#ifdef CONFIG_KEXEC_CORE
53#include <linux/kexec.h>
54#endif
55
56#include <trace/events/xen.h>
57
58#include <asm/pgtable.h>
59#include <asm/tlbflush.h>
60#include <asm/fixmap.h>
61#include <asm/mmu_context.h>
62#include <asm/setup.h>
63#include <asm/paravirt.h>
64#include <asm/e820/api.h>
65#include <asm/linkage.h>
66#include <asm/page.h>
67#include <asm/init.h>
68#include <asm/pat.h>
69#include <asm/smp.h>
70
71#include <asm/xen/hypercall.h>
72#include <asm/xen/hypervisor.h>
73
74#include <xen/xen.h>
75#include <xen/page.h>
76#include <xen/interface/xen.h>
77#include <xen/interface/hvm/hvm_op.h>
78#include <xen/interface/version.h>
79#include <xen/interface/memory.h>
80#include <xen/hvc-console.h>
81
82#include "multicalls.h"
83#include "mmu.h"
84#include "debugfs.h"
85
86#ifdef CONFIG_X86_32
87
88
89
90
91
92#define LEVEL1_IDENT_ENTRIES (PTRS_PER_PTE * 4)
93static RESERVE_BRK_ARRAY(pte_t, level1_ident_pgt, LEVEL1_IDENT_ENTRIES);
94#endif
95#ifdef CONFIG_X86_64
96
97static pud_t level3_user_vsyscall[PTRS_PER_PUD] __page_aligned_bss;
98#endif
99
100
101
102
103
104
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111
112
113
114DEFINE_PER_CPU(unsigned long, xen_cr3);
115DEFINE_PER_CPU(unsigned long, xen_current_cr3);
116
117static phys_addr_t xen_pt_base, xen_pt_size __initdata;
118
119static DEFINE_STATIC_KEY_FALSE(xen_struct_pages_ready);
120
121
122
123
124
125#define USER_LIMIT ((STACK_TOP_MAX + PGDIR_SIZE - 1) & PGDIR_MASK)
126
127void make_lowmem_page_readonly(void *vaddr)
128{
129 pte_t *pte, ptev;
130 unsigned long address = (unsigned long)vaddr;
131 unsigned int level;
132
133 pte = lookup_address(address, &level);
134 if (pte == NULL)
135 return;
136
137 ptev = pte_wrprotect(*pte);
138
139 if (HYPERVISOR_update_va_mapping(address, ptev, 0))
140 BUG();
141}
142
143void make_lowmem_page_readwrite(void *vaddr)
144{
145 pte_t *pte, ptev;
146 unsigned long address = (unsigned long)vaddr;
147 unsigned int level;
148
149 pte = lookup_address(address, &level);
150 if (pte == NULL)
151 return;
152
153 ptev = pte_mkwrite(*pte);
154
155 if (HYPERVISOR_update_va_mapping(address, ptev, 0))
156 BUG();
157}
158
159
160
161
162
163
164static bool xen_page_pinned(void *ptr)
165{
166 if (static_branch_likely(&xen_struct_pages_ready)) {
167 struct page *page = virt_to_page(ptr);
168
169 return PagePinned(page);
170 }
171 return true;
172}
173
174static void xen_extend_mmu_update(const struct mmu_update *update)
175{
176 struct multicall_space mcs;
177 struct mmu_update *u;
178
179 mcs = xen_mc_extend_args(__HYPERVISOR_mmu_update, sizeof(*u));
180
181 if (mcs.mc != NULL) {
182 mcs.mc->args[1]++;
183 } else {
184 mcs = __xen_mc_entry(sizeof(*u));
185 MULTI_mmu_update(mcs.mc, mcs.args, 1, NULL, DOMID_SELF);
186 }
187
188 u = mcs.args;
189 *u = *update;
190}
191
192static void xen_extend_mmuext_op(const struct mmuext_op *op)
193{
194 struct multicall_space mcs;
195 struct mmuext_op *u;
196
197 mcs = xen_mc_extend_args(__HYPERVISOR_mmuext_op, sizeof(*u));
198
199 if (mcs.mc != NULL) {
200 mcs.mc->args[1]++;
201 } else {
202 mcs = __xen_mc_entry(sizeof(*u));
203 MULTI_mmuext_op(mcs.mc, mcs.args, 1, NULL, DOMID_SELF);
204 }
205
206 u = mcs.args;
207 *u = *op;
208}
209
210static void xen_set_pmd_hyper(pmd_t *ptr, pmd_t val)
211{
212 struct mmu_update u;
213
214 preempt_disable();
215
216 xen_mc_batch();
217
218
219 u.ptr = arbitrary_virt_to_machine(ptr).maddr;
220 u.val = pmd_val_ma(val);
221 xen_extend_mmu_update(&u);
222
223 xen_mc_issue(PARAVIRT_LAZY_MMU);
224
225 preempt_enable();
226}
227
228static void xen_set_pmd(pmd_t *ptr, pmd_t val)
229{
230 trace_xen_mmu_set_pmd(ptr, val);
231
232
233
234 if (!xen_page_pinned(ptr)) {
235 *ptr = val;
236 return;
237 }
238
239 xen_set_pmd_hyper(ptr, val);
240}
241
242
243
244
245
246void set_pte_mfn(unsigned long vaddr, unsigned long mfn, pgprot_t flags)
247{
248 set_pte_vaddr(vaddr, mfn_pte(mfn, flags));
249}
250
251static bool xen_batched_set_pte(pte_t *ptep, pte_t pteval)
252{
253 struct mmu_update u;
254
255 if (paravirt_get_lazy_mode() != PARAVIRT_LAZY_MMU)
256 return false;
257
258 xen_mc_batch();
259
260 u.ptr = virt_to_machine(ptep).maddr | MMU_NORMAL_PT_UPDATE;
261 u.val = pte_val_ma(pteval);
262 xen_extend_mmu_update(&u);
263
264 xen_mc_issue(PARAVIRT_LAZY_MMU);
265
266 return true;
267}
268
269static inline void __xen_set_pte(pte_t *ptep, pte_t pteval)
270{
271 if (!xen_batched_set_pte(ptep, pteval)) {
272
273
274
275
276
277
278
279 struct mmu_update u;
280
281 u.ptr = virt_to_machine(ptep).maddr | MMU_NORMAL_PT_UPDATE;
282 u.val = pte_val_ma(pteval);
283 HYPERVISOR_mmu_update(&u, 1, NULL, DOMID_SELF);
284 }
285}
286
287static void xen_set_pte(pte_t *ptep, pte_t pteval)
288{
289 trace_xen_mmu_set_pte(ptep, pteval);
290 __xen_set_pte(ptep, pteval);
291}
292
293static void xen_set_pte_at(struct mm_struct *mm, unsigned long addr,
294 pte_t *ptep, pte_t pteval)
295{
296 trace_xen_mmu_set_pte_at(mm, addr, ptep, pteval);
297 __xen_set_pte(ptep, pteval);
298}
299
300pte_t xen_ptep_modify_prot_start(struct mm_struct *mm,
301 unsigned long addr, pte_t *ptep)
302{
303
304 trace_xen_mmu_ptep_modify_prot_start(mm, addr, ptep, *ptep);
305 return *ptep;
306}
307
308void xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
309 pte_t *ptep, pte_t pte)
310{
311 struct mmu_update u;
312
313 trace_xen_mmu_ptep_modify_prot_commit(mm, addr, ptep, pte);
314 xen_mc_batch();
315
316 u.ptr = virt_to_machine(ptep).maddr | MMU_PT_UPDATE_PRESERVE_AD;
317 u.val = pte_val_ma(pte);
318 xen_extend_mmu_update(&u);
319
320 xen_mc_issue(PARAVIRT_LAZY_MMU);
321}
322
323
324static pteval_t pte_mfn_to_pfn(pteval_t val)
325{
326 if (val & _PAGE_PRESENT) {
327 unsigned long mfn = (val & XEN_PTE_MFN_MASK) >> PAGE_SHIFT;
328 unsigned long pfn = mfn_to_pfn(mfn);
329
330 pteval_t flags = val & PTE_FLAGS_MASK;
331 if (unlikely(pfn == ~0))
332 val = flags & ~_PAGE_PRESENT;
333 else
334 val = ((pteval_t)pfn << PAGE_SHIFT) | flags;
335 }
336
337 return val;
338}
339
340static pteval_t pte_pfn_to_mfn(pteval_t val)
341{
342 if (val & _PAGE_PRESENT) {
343 unsigned long pfn = (val & PTE_PFN_MASK) >> PAGE_SHIFT;
344 pteval_t flags = val & PTE_FLAGS_MASK;
345 unsigned long mfn;
346
347 mfn = __pfn_to_mfn(pfn);
348
349
350
351
352
353
354
355 if (unlikely(mfn == INVALID_P2M_ENTRY)) {
356 mfn = 0;
357 flags = 0;
358 } else
359 mfn &= ~(FOREIGN_FRAME_BIT | IDENTITY_FRAME_BIT);
360 val = ((pteval_t)mfn << PAGE_SHIFT) | flags;
361 }
362
363 return val;
364}
365
366__visible pteval_t xen_pte_val(pte_t pte)
367{
368 pteval_t pteval = pte.pte;
369
370 return pte_mfn_to_pfn(pteval);
371}
372PV_CALLEE_SAVE_REGS_THUNK(xen_pte_val);
373
374__visible pgdval_t xen_pgd_val(pgd_t pgd)
375{
376 return pte_mfn_to_pfn(pgd.pgd);
377}
378PV_CALLEE_SAVE_REGS_THUNK(xen_pgd_val);
379
380__visible pte_t xen_make_pte(pteval_t pte)
381{
382 pte = pte_pfn_to_mfn(pte);
383
384 return native_make_pte(pte);
385}
386PV_CALLEE_SAVE_REGS_THUNK(xen_make_pte);
387
388__visible pgd_t xen_make_pgd(pgdval_t pgd)
389{
390 pgd = pte_pfn_to_mfn(pgd);
391 return native_make_pgd(pgd);
392}
393PV_CALLEE_SAVE_REGS_THUNK(xen_make_pgd);
394
395__visible pmdval_t xen_pmd_val(pmd_t pmd)
396{
397 return pte_mfn_to_pfn(pmd.pmd);
398}
399PV_CALLEE_SAVE_REGS_THUNK(xen_pmd_val);
400
401static void xen_set_pud_hyper(pud_t *ptr, pud_t val)
402{
403 struct mmu_update u;
404
405 preempt_disable();
406
407 xen_mc_batch();
408
409
410 u.ptr = arbitrary_virt_to_machine(ptr).maddr;
411 u.val = pud_val_ma(val);
412 xen_extend_mmu_update(&u);
413
414 xen_mc_issue(PARAVIRT_LAZY_MMU);
415
416 preempt_enable();
417}
418
419static void xen_set_pud(pud_t *ptr, pud_t val)
420{
421 trace_xen_mmu_set_pud(ptr, val);
422
423
424
425 if (!xen_page_pinned(ptr)) {
426 *ptr = val;
427 return;
428 }
429
430 xen_set_pud_hyper(ptr, val);
431}
432
433#ifdef CONFIG_X86_PAE
434static void xen_set_pte_atomic(pte_t *ptep, pte_t pte)
435{
436 trace_xen_mmu_set_pte_atomic(ptep, pte);
437 set_64bit((u64 *)ptep, native_pte_val(pte));
438}
439
440static void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
441{
442 trace_xen_mmu_pte_clear(mm, addr, ptep);
443 if (!xen_batched_set_pte(ptep, native_make_pte(0)))
444 native_pte_clear(mm, addr, ptep);
445}
446
447static void xen_pmd_clear(pmd_t *pmdp)
448{
449 trace_xen_mmu_pmd_clear(pmdp);
450 set_pmd(pmdp, __pmd(0));
451}
452#endif
453
454__visible pmd_t xen_make_pmd(pmdval_t pmd)
455{
456 pmd = pte_pfn_to_mfn(pmd);
457 return native_make_pmd(pmd);
458}
459PV_CALLEE_SAVE_REGS_THUNK(xen_make_pmd);
460
461#ifdef CONFIG_X86_64
462__visible pudval_t xen_pud_val(pud_t pud)
463{
464 return pte_mfn_to_pfn(pud.pud);
465}
466PV_CALLEE_SAVE_REGS_THUNK(xen_pud_val);
467
468__visible pud_t xen_make_pud(pudval_t pud)
469{
470 pud = pte_pfn_to_mfn(pud);
471
472 return native_make_pud(pud);
473}
474PV_CALLEE_SAVE_REGS_THUNK(xen_make_pud);
475
476static pgd_t *xen_get_user_pgd(pgd_t *pgd)
477{
478 pgd_t *pgd_page = (pgd_t *)(((unsigned long)pgd) & PAGE_MASK);
479 unsigned offset = pgd - pgd_page;
480 pgd_t *user_ptr = NULL;
481
482 if (offset < pgd_index(USER_LIMIT)) {
483 struct page *page = virt_to_page(pgd_page);
484 user_ptr = (pgd_t *)page->private;
485 if (user_ptr)
486 user_ptr += offset;
487 }
488
489 return user_ptr;
490}
491
492static void __xen_set_p4d_hyper(p4d_t *ptr, p4d_t val)
493{
494 struct mmu_update u;
495
496 u.ptr = virt_to_machine(ptr).maddr;
497 u.val = p4d_val_ma(val);
498 xen_extend_mmu_update(&u);
499}
500
501
502
503
504
505
506
507
508static void __init xen_set_p4d_hyper(p4d_t *ptr, p4d_t val)
509{
510 preempt_disable();
511
512 xen_mc_batch();
513
514 __xen_set_p4d_hyper(ptr, val);
515
516 xen_mc_issue(PARAVIRT_LAZY_MMU);
517
518 preempt_enable();
519}
520
521static void xen_set_p4d(p4d_t *ptr, p4d_t val)
522{
523 pgd_t *user_ptr = xen_get_user_pgd((pgd_t *)ptr);
524 pgd_t pgd_val;
525
526 trace_xen_mmu_set_p4d(ptr, (p4d_t *)user_ptr, val);
527
528
529
530 if (!xen_page_pinned(ptr)) {
531 *ptr = val;
532 if (user_ptr) {
533 WARN_ON(xen_page_pinned(user_ptr));
534 pgd_val.pgd = p4d_val_ma(val);
535 *user_ptr = pgd_val;
536 }
537 return;
538 }
539
540
541
542 xen_mc_batch();
543
544 __xen_set_p4d_hyper(ptr, val);
545 if (user_ptr)
546 __xen_set_p4d_hyper((p4d_t *)user_ptr, val);
547
548 xen_mc_issue(PARAVIRT_LAZY_MMU);
549}
550
551#if CONFIG_PGTABLE_LEVELS >= 5
552__visible p4dval_t xen_p4d_val(p4d_t p4d)
553{
554 return pte_mfn_to_pfn(p4d.p4d);
555}
556PV_CALLEE_SAVE_REGS_THUNK(xen_p4d_val);
557
558__visible p4d_t xen_make_p4d(p4dval_t p4d)
559{
560 p4d = pte_pfn_to_mfn(p4d);
561
562 return native_make_p4d(p4d);
563}
564PV_CALLEE_SAVE_REGS_THUNK(xen_make_p4d);
565#endif
566#endif
567
568static int xen_pmd_walk(struct mm_struct *mm, pmd_t *pmd,
569 int (*func)(struct mm_struct *mm, struct page *, enum pt_level),
570 bool last, unsigned long limit)
571{
572 int i, nr, flush = 0;
573
574 nr = last ? pmd_index(limit) + 1 : PTRS_PER_PMD;
575 for (i = 0; i < nr; i++) {
576 if (!pmd_none(pmd[i]))
577 flush |= (*func)(mm, pmd_page(pmd[i]), PT_PTE);
578 }
579 return flush;
580}
581
582static int xen_pud_walk(struct mm_struct *mm, pud_t *pud,
583 int (*func)(struct mm_struct *mm, struct page *, enum pt_level),
584 bool last, unsigned long limit)
585{
586 int i, nr, flush = 0;
587
588 nr = last ? pud_index(limit) + 1 : PTRS_PER_PUD;
589 for (i = 0; i < nr; i++) {
590 pmd_t *pmd;
591
592 if (pud_none(pud[i]))
593 continue;
594
595 pmd = pmd_offset(&pud[i], 0);
596 if (PTRS_PER_PMD > 1)
597 flush |= (*func)(mm, virt_to_page(pmd), PT_PMD);
598 flush |= xen_pmd_walk(mm, pmd, func,
599 last && i == nr - 1, limit);
600 }
601 return flush;
602}
603
604static int xen_p4d_walk(struct mm_struct *mm, p4d_t *p4d,
605 int (*func)(struct mm_struct *mm, struct page *, enum pt_level),
606 bool last, unsigned long limit)
607{
608 int flush = 0;
609 pud_t *pud;
610
611
612 if (p4d_none(*p4d))
613 return flush;
614
615 pud = pud_offset(p4d, 0);
616 if (PTRS_PER_PUD > 1)
617 flush |= (*func)(mm, virt_to_page(pud), PT_PUD);
618 flush |= xen_pud_walk(mm, pud, func, last, limit);
619 return flush;
620}
621
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635
636
637static int __xen_pgd_walk(struct mm_struct *mm, pgd_t *pgd,
638 int (*func)(struct mm_struct *mm, struct page *,
639 enum pt_level),
640 unsigned long limit)
641{
642 int i, nr, flush = 0;
643 unsigned hole_low, hole_high;
644
645
646 limit--;
647 BUG_ON(limit >= FIXADDR_TOP);
648
649
650
651
652
653
654 hole_low = pgd_index(USER_LIMIT);
655 hole_high = pgd_index(PAGE_OFFSET);
656
657 nr = pgd_index(limit) + 1;
658 for (i = 0; i < nr; i++) {
659 p4d_t *p4d;
660
661 if (i >= hole_low && i < hole_high)
662 continue;
663
664 if (pgd_none(pgd[i]))
665 continue;
666
667 p4d = p4d_offset(&pgd[i], 0);
668 flush |= xen_p4d_walk(mm, p4d, func, i == nr - 1, limit);
669 }
670
671
672
673 flush |= (*func)(mm, virt_to_page(pgd), PT_PGD);
674
675 return flush;
676}
677
678static int xen_pgd_walk(struct mm_struct *mm,
679 int (*func)(struct mm_struct *mm, struct page *,
680 enum pt_level),
681 unsigned long limit)
682{
683 return __xen_pgd_walk(mm, mm->pgd, func, limit);
684}
685
686
687
688static spinlock_t *xen_pte_lock(struct page *page, struct mm_struct *mm)
689{
690 spinlock_t *ptl = NULL;
691
692#if USE_SPLIT_PTE_PTLOCKS
693 ptl = ptlock_ptr(page);
694 spin_lock_nest_lock(ptl, &mm->page_table_lock);
695#endif
696
697 return ptl;
698}
699
700static void xen_pte_unlock(void *v)
701{
702 spinlock_t *ptl = v;
703 spin_unlock(ptl);
704}
705
706static void xen_do_pin(unsigned level, unsigned long pfn)
707{
708 struct mmuext_op op;
709
710 op.cmd = level;
711 op.arg1.mfn = pfn_to_mfn(pfn);
712
713 xen_extend_mmuext_op(&op);
714}
715
716static int xen_pin_page(struct mm_struct *mm, struct page *page,
717 enum pt_level level)
718{
719 unsigned pgfl = TestSetPagePinned(page);
720 int flush;
721
722 if (pgfl)
723 flush = 0;
724 else if (PageHighMem(page))
725
726
727 flush = 1;
728 else {
729 void *pt = lowmem_page_address(page);
730 unsigned long pfn = page_to_pfn(page);
731 struct multicall_space mcs = __xen_mc_entry(0);
732 spinlock_t *ptl;
733
734 flush = 0;
735
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743
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746
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749
750
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754
755
756 ptl = NULL;
757 if (level == PT_PTE)
758 ptl = xen_pte_lock(page, mm);
759
760 MULTI_update_va_mapping(mcs.mc, (unsigned long)pt,
761 pfn_pte(pfn, PAGE_KERNEL_RO),
762 level == PT_PGD ? UVMF_TLB_FLUSH : 0);
763
764 if (ptl) {
765 xen_do_pin(MMUEXT_PIN_L1_TABLE, pfn);
766
767
768
769 xen_mc_callback(xen_pte_unlock, ptl);
770 }
771 }
772
773 return flush;
774}
775
776
777
778
779static void __xen_pgd_pin(struct mm_struct *mm, pgd_t *pgd)
780{
781 trace_xen_mmu_pgd_pin(mm, pgd);
782
783 xen_mc_batch();
784
785 if (__xen_pgd_walk(mm, pgd, xen_pin_page, USER_LIMIT)) {
786
787 xen_mc_issue(0);
788
789 kmap_flush_unused();
790
791 xen_mc_batch();
792 }
793
794#ifdef CONFIG_X86_64
795 {
796 pgd_t *user_pgd = xen_get_user_pgd(pgd);
797
798 xen_do_pin(MMUEXT_PIN_L4_TABLE, PFN_DOWN(__pa(pgd)));
799
800 if (user_pgd) {
801 xen_pin_page(mm, virt_to_page(user_pgd), PT_PGD);
802 xen_do_pin(MMUEXT_PIN_L4_TABLE,
803 PFN_DOWN(__pa(user_pgd)));
804 }
805 }
806#else
807#ifdef CONFIG_X86_PAE
808
809 xen_pin_page(mm, pgd_page(pgd[pgd_index(TASK_SIZE)]),
810 PT_PMD);
811#endif
812 xen_do_pin(MMUEXT_PIN_L3_TABLE, PFN_DOWN(__pa(pgd)));
813#endif
814 xen_mc_issue(0);
815}
816
817static void xen_pgd_pin(struct mm_struct *mm)
818{
819 __xen_pgd_pin(mm, mm->pgd);
820}
821
822
823
824
825
826
827
828
829
830
831
832void xen_mm_pin_all(void)
833{
834 struct page *page;
835
836 spin_lock(&pgd_lock);
837
838 list_for_each_entry(page, &pgd_list, lru) {
839 if (!PagePinned(page)) {
840 __xen_pgd_pin(&init_mm, (pgd_t *)page_address(page));
841 SetPageSavePinned(page);
842 }
843 }
844
845 spin_unlock(&pgd_lock);
846}
847
848static int __init xen_mark_pinned(struct mm_struct *mm, struct page *page,
849 enum pt_level level)
850{
851 SetPagePinned(page);
852 return 0;
853}
854
855
856
857
858
859
860
861static void __init xen_after_bootmem(void)
862{
863 static_branch_enable(&xen_struct_pages_ready);
864#ifdef CONFIG_X86_64
865 SetPagePinned(virt_to_page(level3_user_vsyscall));
866#endif
867 xen_pgd_walk(&init_mm, xen_mark_pinned, FIXADDR_TOP);
868}
869
870static int xen_unpin_page(struct mm_struct *mm, struct page *page,
871 enum pt_level level)
872{
873 unsigned pgfl = TestClearPagePinned(page);
874
875 if (pgfl && !PageHighMem(page)) {
876 void *pt = lowmem_page_address(page);
877 unsigned long pfn = page_to_pfn(page);
878 spinlock_t *ptl = NULL;
879 struct multicall_space mcs;
880
881
882
883
884
885
886
887
888 if (level == PT_PTE) {
889 ptl = xen_pte_lock(page, mm);
890
891 if (ptl)
892 xen_do_pin(MMUEXT_UNPIN_TABLE, pfn);
893 }
894
895 mcs = __xen_mc_entry(0);
896
897 MULTI_update_va_mapping(mcs.mc, (unsigned long)pt,
898 pfn_pte(pfn, PAGE_KERNEL),
899 level == PT_PGD ? UVMF_TLB_FLUSH : 0);
900
901 if (ptl) {
902
903 xen_mc_callback(xen_pte_unlock, ptl);
904 }
905 }
906
907 return 0;
908}
909
910
911static void __xen_pgd_unpin(struct mm_struct *mm, pgd_t *pgd)
912{
913 trace_xen_mmu_pgd_unpin(mm, pgd);
914
915 xen_mc_batch();
916
917 xen_do_pin(MMUEXT_UNPIN_TABLE, PFN_DOWN(__pa(pgd)));
918
919#ifdef CONFIG_X86_64
920 {
921 pgd_t *user_pgd = xen_get_user_pgd(pgd);
922
923 if (user_pgd) {
924 xen_do_pin(MMUEXT_UNPIN_TABLE,
925 PFN_DOWN(__pa(user_pgd)));
926 xen_unpin_page(mm, virt_to_page(user_pgd), PT_PGD);
927 }
928 }
929#endif
930
931#ifdef CONFIG_X86_PAE
932
933 xen_unpin_page(mm, pgd_page(pgd[pgd_index(TASK_SIZE)]),
934 PT_PMD);
935#endif
936
937 __xen_pgd_walk(mm, pgd, xen_unpin_page, USER_LIMIT);
938
939 xen_mc_issue(0);
940}
941
942static void xen_pgd_unpin(struct mm_struct *mm)
943{
944 __xen_pgd_unpin(mm, mm->pgd);
945}
946
947
948
949
950
951void xen_mm_unpin_all(void)
952{
953 struct page *page;
954
955 spin_lock(&pgd_lock);
956
957 list_for_each_entry(page, &pgd_list, lru) {
958 if (PageSavePinned(page)) {
959 BUG_ON(!PagePinned(page));
960 __xen_pgd_unpin(&init_mm, (pgd_t *)page_address(page));
961 ClearPageSavePinned(page);
962 }
963 }
964
965 spin_unlock(&pgd_lock);
966}
967
968static void xen_activate_mm(struct mm_struct *prev, struct mm_struct *next)
969{
970 spin_lock(&next->page_table_lock);
971 xen_pgd_pin(next);
972 spin_unlock(&next->page_table_lock);
973}
974
975static void xen_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm)
976{
977 spin_lock(&mm->page_table_lock);
978 xen_pgd_pin(mm);
979 spin_unlock(&mm->page_table_lock);
980}
981
982static void drop_mm_ref_this_cpu(void *info)
983{
984 struct mm_struct *mm = info;
985
986 if (this_cpu_read(cpu_tlbstate.loaded_mm) == mm)
987 leave_mm(smp_processor_id());
988
989
990
991
992
993 if (this_cpu_read(xen_current_cr3) == __pa(mm->pgd))
994 xen_mc_flush();
995}
996
997#ifdef CONFIG_SMP
998
999
1000
1001
1002static void xen_drop_mm_ref(struct mm_struct *mm)
1003{
1004 cpumask_var_t mask;
1005 unsigned cpu;
1006
1007 drop_mm_ref_this_cpu(mm);
1008
1009
1010 if (!alloc_cpumask_var(&mask, GFP_ATOMIC)) {
1011 for_each_online_cpu(cpu) {
1012 if (per_cpu(xen_current_cr3, cpu) != __pa(mm->pgd))
1013 continue;
1014 smp_call_function_single(cpu, drop_mm_ref_this_cpu, mm, 1);
1015 }
1016 return;
1017 }
1018
1019
1020
1021
1022
1023
1024
1025
1026 cpumask_clear(mask);
1027 for_each_online_cpu(cpu) {
1028 if (per_cpu(xen_current_cr3, cpu) == __pa(mm->pgd))
1029 cpumask_set_cpu(cpu, mask);
1030 }
1031
1032 smp_call_function_many(mask, drop_mm_ref_this_cpu, mm, 1);
1033 free_cpumask_var(mask);
1034}
1035#else
1036static void xen_drop_mm_ref(struct mm_struct *mm)
1037{
1038 drop_mm_ref_this_cpu(mm);
1039}
1040#endif
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056static void xen_exit_mmap(struct mm_struct *mm)
1057{
1058 get_cpu();
1059 xen_drop_mm_ref(mm);
1060 put_cpu();
1061
1062 spin_lock(&mm->page_table_lock);
1063
1064
1065 if (xen_page_pinned(mm->pgd))
1066 xen_pgd_unpin(mm);
1067
1068 spin_unlock(&mm->page_table_lock);
1069}
1070
1071static void xen_post_allocator_init(void);
1072
1073static void __init pin_pagetable_pfn(unsigned cmd, unsigned long pfn)
1074{
1075 struct mmuext_op op;
1076
1077 op.cmd = cmd;
1078 op.arg1.mfn = pfn_to_mfn(pfn);
1079 if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF))
1080 BUG();
1081}
1082
1083#ifdef CONFIG_X86_64
1084static void __init xen_cleanhighmap(unsigned long vaddr,
1085 unsigned long vaddr_end)
1086{
1087 unsigned long kernel_end = roundup((unsigned long)_brk_end, PMD_SIZE) - 1;
1088 pmd_t *pmd = level2_kernel_pgt + pmd_index(vaddr);
1089
1090
1091
1092 for (; vaddr <= vaddr_end && (pmd < (level2_kernel_pgt + PTRS_PER_PMD));
1093 pmd++, vaddr += PMD_SIZE) {
1094 if (pmd_none(*pmd))
1095 continue;
1096 if (vaddr < (unsigned long) _text || vaddr > kernel_end)
1097 set_pmd(pmd, __pmd(0));
1098 }
1099
1100
1101 xen_mc_flush();
1102}
1103
1104
1105
1106
1107static void __init xen_free_ro_pages(unsigned long paddr, unsigned long size)
1108{
1109 void *vaddr = __va(paddr);
1110 void *vaddr_end = vaddr + size;
1111
1112 for (; vaddr < vaddr_end; vaddr += PAGE_SIZE)
1113 make_lowmem_page_readwrite(vaddr);
1114
1115 memblock_free(paddr, size);
1116}
1117
1118static void __init xen_cleanmfnmap_free_pgtbl(void *pgtbl, bool unpin)
1119{
1120 unsigned long pa = __pa(pgtbl) & PHYSICAL_PAGE_MASK;
1121
1122 if (unpin)
1123 pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, PFN_DOWN(pa));
1124 ClearPagePinned(virt_to_page(__va(pa)));
1125 xen_free_ro_pages(pa, PAGE_SIZE);
1126}
1127
1128static void __init xen_cleanmfnmap_pmd(pmd_t *pmd, bool unpin)
1129{
1130 unsigned long pa;
1131 pte_t *pte_tbl;
1132 int i;
1133
1134 if (pmd_large(*pmd)) {
1135 pa = pmd_val(*pmd) & PHYSICAL_PAGE_MASK;
1136 xen_free_ro_pages(pa, PMD_SIZE);
1137 return;
1138 }
1139
1140 pte_tbl = pte_offset_kernel(pmd, 0);
1141 for (i = 0; i < PTRS_PER_PTE; i++) {
1142 if (pte_none(pte_tbl[i]))
1143 continue;
1144 pa = pte_pfn(pte_tbl[i]) << PAGE_SHIFT;
1145 xen_free_ro_pages(pa, PAGE_SIZE);
1146 }
1147 set_pmd(pmd, __pmd(0));
1148 xen_cleanmfnmap_free_pgtbl(pte_tbl, unpin);
1149}
1150
1151static void __init xen_cleanmfnmap_pud(pud_t *pud, bool unpin)
1152{
1153 unsigned long pa;
1154 pmd_t *pmd_tbl;
1155 int i;
1156
1157 if (pud_large(*pud)) {
1158 pa = pud_val(*pud) & PHYSICAL_PAGE_MASK;
1159 xen_free_ro_pages(pa, PUD_SIZE);
1160 return;
1161 }
1162
1163 pmd_tbl = pmd_offset(pud, 0);
1164 for (i = 0; i < PTRS_PER_PMD; i++) {
1165 if (pmd_none(pmd_tbl[i]))
1166 continue;
1167 xen_cleanmfnmap_pmd(pmd_tbl + i, unpin);
1168 }
1169 set_pud(pud, __pud(0));
1170 xen_cleanmfnmap_free_pgtbl(pmd_tbl, unpin);
1171}
1172
1173static void __init xen_cleanmfnmap_p4d(p4d_t *p4d, bool unpin)
1174{
1175 unsigned long pa;
1176 pud_t *pud_tbl;
1177 int i;
1178
1179 if (p4d_large(*p4d)) {
1180 pa = p4d_val(*p4d) & PHYSICAL_PAGE_MASK;
1181 xen_free_ro_pages(pa, P4D_SIZE);
1182 return;
1183 }
1184
1185 pud_tbl = pud_offset(p4d, 0);
1186 for (i = 0; i < PTRS_PER_PUD; i++) {
1187 if (pud_none(pud_tbl[i]))
1188 continue;
1189 xen_cleanmfnmap_pud(pud_tbl + i, unpin);
1190 }
1191 set_p4d(p4d, __p4d(0));
1192 xen_cleanmfnmap_free_pgtbl(pud_tbl, unpin);
1193}
1194
1195
1196
1197
1198
1199static void __init xen_cleanmfnmap(unsigned long vaddr)
1200{
1201 pgd_t *pgd;
1202 p4d_t *p4d;
1203 bool unpin;
1204
1205 unpin = (vaddr == 2 * PGDIR_SIZE);
1206 vaddr &= PMD_MASK;
1207 pgd = pgd_offset_k(vaddr);
1208 p4d = p4d_offset(pgd, 0);
1209 if (!p4d_none(*p4d))
1210 xen_cleanmfnmap_p4d(p4d, unpin);
1211}
1212
1213static void __init xen_pagetable_p2m_free(void)
1214{
1215 unsigned long size;
1216 unsigned long addr;
1217
1218 size = PAGE_ALIGN(xen_start_info->nr_pages * sizeof(unsigned long));
1219
1220
1221 if ((unsigned long)xen_p2m_addr == xen_start_info->mfn_list)
1222 return;
1223
1224
1225 memset((void *)xen_start_info->mfn_list, 0xff, size);
1226
1227 addr = xen_start_info->mfn_list;
1228
1229
1230
1231
1232
1233
1234
1235
1236 size = roundup(size, PMD_SIZE);
1237
1238 if (addr >= __START_KERNEL_map) {
1239 xen_cleanhighmap(addr, addr + size);
1240 size = PAGE_ALIGN(xen_start_info->nr_pages *
1241 sizeof(unsigned long));
1242 memblock_free(__pa(addr), size);
1243 } else {
1244 xen_cleanmfnmap(addr);
1245 }
1246}
1247
1248static void __init xen_pagetable_cleanhighmap(void)
1249{
1250 unsigned long size;
1251 unsigned long addr;
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262 addr = xen_start_info->pt_base;
1263 size = xen_start_info->nr_pt_frames * PAGE_SIZE;
1264
1265 xen_cleanhighmap(addr, roundup(addr + size, PMD_SIZE * 2));
1266 xen_start_info->pt_base = (unsigned long)__va(__pa(xen_start_info->pt_base));
1267}
1268#endif
1269
1270static void __init xen_pagetable_p2m_setup(void)
1271{
1272 xen_vmalloc_p2m_tree();
1273
1274#ifdef CONFIG_X86_64
1275 xen_pagetable_p2m_free();
1276
1277 xen_pagetable_cleanhighmap();
1278#endif
1279
1280 xen_start_info->mfn_list = (unsigned long)xen_p2m_addr;
1281}
1282
1283static void __init xen_pagetable_init(void)
1284{
1285 paging_init();
1286 xen_post_allocator_init();
1287
1288 xen_pagetable_p2m_setup();
1289
1290
1291 xen_build_mfn_list_list();
1292
1293
1294 xen_remap_memory();
1295
1296 xen_setup_shared_info();
1297}
1298static void xen_write_cr2(unsigned long cr2)
1299{
1300 this_cpu_read(xen_vcpu)->arch.cr2 = cr2;
1301}
1302
1303static unsigned long xen_read_cr2(void)
1304{
1305 return this_cpu_read(xen_vcpu)->arch.cr2;
1306}
1307
1308unsigned long xen_read_cr2_direct(void)
1309{
1310 return this_cpu_read(xen_vcpu_info.arch.cr2);
1311}
1312
1313static noinline void xen_flush_tlb(void)
1314{
1315 struct mmuext_op *op;
1316 struct multicall_space mcs;
1317
1318 preempt_disable();
1319
1320 mcs = xen_mc_entry(sizeof(*op));
1321
1322 op = mcs.args;
1323 op->cmd = MMUEXT_TLB_FLUSH_LOCAL;
1324 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF);
1325
1326 xen_mc_issue(PARAVIRT_LAZY_MMU);
1327
1328 preempt_enable();
1329}
1330
1331static void xen_flush_tlb_one_user(unsigned long addr)
1332{
1333 struct mmuext_op *op;
1334 struct multicall_space mcs;
1335
1336 trace_xen_mmu_flush_tlb_one_user(addr);
1337
1338 preempt_disable();
1339
1340 mcs = xen_mc_entry(sizeof(*op));
1341 op = mcs.args;
1342 op->cmd = MMUEXT_INVLPG_LOCAL;
1343 op->arg1.linear_addr = addr & PAGE_MASK;
1344 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF);
1345
1346 xen_mc_issue(PARAVIRT_LAZY_MMU);
1347
1348 preempt_enable();
1349}
1350
1351static void xen_flush_tlb_others(const struct cpumask *cpus,
1352 const struct flush_tlb_info *info)
1353{
1354 struct {
1355 struct mmuext_op op;
1356 DECLARE_BITMAP(mask, NR_CPUS);
1357 } *args;
1358 struct multicall_space mcs;
1359 const size_t mc_entry_size = sizeof(args->op) +
1360 sizeof(args->mask[0]) * BITS_TO_LONGS(num_possible_cpus());
1361
1362 trace_xen_mmu_flush_tlb_others(cpus, info->mm, info->start, info->end);
1363
1364 if (cpumask_empty(cpus))
1365 return;
1366
1367 mcs = xen_mc_entry(mc_entry_size);
1368 args = mcs.args;
1369 args->op.arg2.vcpumask = to_cpumask(args->mask);
1370
1371
1372 cpumask_and(to_cpumask(args->mask), cpus, cpu_online_mask);
1373 cpumask_clear_cpu(smp_processor_id(), to_cpumask(args->mask));
1374
1375 args->op.cmd = MMUEXT_TLB_FLUSH_MULTI;
1376 if (info->end != TLB_FLUSH_ALL &&
1377 (info->end - info->start) <= PAGE_SIZE) {
1378 args->op.cmd = MMUEXT_INVLPG_MULTI;
1379 args->op.arg1.linear_addr = info->start;
1380 }
1381
1382 MULTI_mmuext_op(mcs.mc, &args->op, 1, NULL, DOMID_SELF);
1383
1384 xen_mc_issue(PARAVIRT_LAZY_MMU);
1385}
1386
1387static unsigned long xen_read_cr3(void)
1388{
1389 return this_cpu_read(xen_cr3);
1390}
1391
1392static void set_current_cr3(void *v)
1393{
1394 this_cpu_write(xen_current_cr3, (unsigned long)v);
1395}
1396
1397static void __xen_write_cr3(bool kernel, unsigned long cr3)
1398{
1399 struct mmuext_op op;
1400 unsigned long mfn;
1401
1402 trace_xen_mmu_write_cr3(kernel, cr3);
1403
1404 if (cr3)
1405 mfn = pfn_to_mfn(PFN_DOWN(cr3));
1406 else
1407 mfn = 0;
1408
1409 WARN_ON(mfn == 0 && kernel);
1410
1411 op.cmd = kernel ? MMUEXT_NEW_BASEPTR : MMUEXT_NEW_USER_BASEPTR;
1412 op.arg1.mfn = mfn;
1413
1414 xen_extend_mmuext_op(&op);
1415
1416 if (kernel) {
1417 this_cpu_write(xen_cr3, cr3);
1418
1419
1420
1421 xen_mc_callback(set_current_cr3, (void *)cr3);
1422 }
1423}
1424static void xen_write_cr3(unsigned long cr3)
1425{
1426 BUG_ON(preemptible());
1427
1428 xen_mc_batch();
1429
1430
1431
1432 this_cpu_write(xen_cr3, cr3);
1433
1434 __xen_write_cr3(true, cr3);
1435
1436#ifdef CONFIG_X86_64
1437 {
1438 pgd_t *user_pgd = xen_get_user_pgd(__va(cr3));
1439 if (user_pgd)
1440 __xen_write_cr3(false, __pa(user_pgd));
1441 else
1442 __xen_write_cr3(false, 0);
1443 }
1444#endif
1445
1446 xen_mc_issue(PARAVIRT_LAZY_CPU);
1447}
1448
1449#ifdef CONFIG_X86_64
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470static void __init xen_write_cr3_init(unsigned long cr3)
1471{
1472 BUG_ON(preemptible());
1473
1474 xen_mc_batch();
1475
1476
1477
1478 this_cpu_write(xen_cr3, cr3);
1479
1480 __xen_write_cr3(true, cr3);
1481
1482 xen_mc_issue(PARAVIRT_LAZY_CPU);
1483}
1484#endif
1485
1486static int xen_pgd_alloc(struct mm_struct *mm)
1487{
1488 pgd_t *pgd = mm->pgd;
1489 int ret = 0;
1490
1491 BUG_ON(PagePinned(virt_to_page(pgd)));
1492
1493#ifdef CONFIG_X86_64
1494 {
1495 struct page *page = virt_to_page(pgd);
1496 pgd_t *user_pgd;
1497
1498 BUG_ON(page->private != 0);
1499
1500 ret = -ENOMEM;
1501
1502 user_pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
1503 page->private = (unsigned long)user_pgd;
1504
1505 if (user_pgd != NULL) {
1506#ifdef CONFIG_X86_VSYSCALL_EMULATION
1507 user_pgd[pgd_index(VSYSCALL_ADDR)] =
1508 __pgd(__pa(level3_user_vsyscall) | _PAGE_TABLE);
1509#endif
1510 ret = 0;
1511 }
1512
1513 BUG_ON(PagePinned(virt_to_page(xen_get_user_pgd(pgd))));
1514 }
1515#endif
1516 return ret;
1517}
1518
1519static void xen_pgd_free(struct mm_struct *mm, pgd_t *pgd)
1520{
1521#ifdef CONFIG_X86_64
1522 pgd_t *user_pgd = xen_get_user_pgd(pgd);
1523
1524 if (user_pgd)
1525 free_page((unsigned long)user_pgd);
1526#endif
1527}
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543__visible pte_t xen_make_pte_init(pteval_t pte)
1544{
1545#ifdef CONFIG_X86_64
1546 unsigned long pfn;
1547
1548
1549
1550
1551
1552
1553
1554 pfn = (pte & PTE_PFN_MASK) >> PAGE_SHIFT;
1555 if (xen_start_info->mfn_list < __START_KERNEL_map &&
1556 pfn >= xen_start_info->first_p2m_pfn &&
1557 pfn < xen_start_info->first_p2m_pfn + xen_start_info->nr_p2m_frames)
1558 pte &= ~_PAGE_RW;
1559#endif
1560 pte = pte_pfn_to_mfn(pte);
1561 return native_make_pte(pte);
1562}
1563PV_CALLEE_SAVE_REGS_THUNK(xen_make_pte_init);
1564
1565static void __init xen_set_pte_init(pte_t *ptep, pte_t pte)
1566{
1567#ifdef CONFIG_X86_32
1568
1569 if (pte_mfn(pte) != INVALID_P2M_ENTRY
1570 && pte_val_ma(*ptep) & _PAGE_PRESENT)
1571 pte = __pte_ma(((pte_val_ma(*ptep) & _PAGE_RW) | ~_PAGE_RW) &
1572 pte_val_ma(pte));
1573#endif
1574 native_set_pte(ptep, pte);
1575}
1576
1577
1578
1579static void __init xen_alloc_pte_init(struct mm_struct *mm, unsigned long pfn)
1580{
1581#ifdef CONFIG_FLATMEM
1582 BUG_ON(mem_map);
1583#endif
1584 make_lowmem_page_readonly(__va(PFN_PHYS(pfn)));
1585 pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn);
1586}
1587
1588
1589static void __init xen_alloc_pmd_init(struct mm_struct *mm, unsigned long pfn)
1590{
1591#ifdef CONFIG_FLATMEM
1592 BUG_ON(mem_map);
1593#endif
1594 make_lowmem_page_readonly(__va(PFN_PHYS(pfn)));
1595}
1596
1597
1598
1599static void __init xen_release_pte_init(unsigned long pfn)
1600{
1601 pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, pfn);
1602 make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
1603}
1604
1605static void __init xen_release_pmd_init(unsigned long pfn)
1606{
1607 make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
1608}
1609
1610static inline void __pin_pagetable_pfn(unsigned cmd, unsigned long pfn)
1611{
1612 struct multicall_space mcs;
1613 struct mmuext_op *op;
1614
1615 mcs = __xen_mc_entry(sizeof(*op));
1616 op = mcs.args;
1617 op->cmd = cmd;
1618 op->arg1.mfn = pfn_to_mfn(pfn);
1619
1620 MULTI_mmuext_op(mcs.mc, mcs.args, 1, NULL, DOMID_SELF);
1621}
1622
1623static inline void __set_pfn_prot(unsigned long pfn, pgprot_t prot)
1624{
1625 struct multicall_space mcs;
1626 unsigned long addr = (unsigned long)__va(pfn << PAGE_SHIFT);
1627
1628 mcs = __xen_mc_entry(0);
1629 MULTI_update_va_mapping(mcs.mc, (unsigned long)addr,
1630 pfn_pte(pfn, prot), 0);
1631}
1632
1633
1634
1635static inline void xen_alloc_ptpage(struct mm_struct *mm, unsigned long pfn,
1636 unsigned level)
1637{
1638 bool pinned = xen_page_pinned(mm->pgd);
1639
1640 trace_xen_mmu_alloc_ptpage(mm, pfn, level, pinned);
1641
1642 if (pinned) {
1643 struct page *page = pfn_to_page(pfn);
1644
1645 if (static_branch_likely(&xen_struct_pages_ready))
1646 SetPagePinned(page);
1647
1648 if (!PageHighMem(page)) {
1649 xen_mc_batch();
1650
1651 __set_pfn_prot(pfn, PAGE_KERNEL_RO);
1652
1653 if (level == PT_PTE && USE_SPLIT_PTE_PTLOCKS)
1654 __pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn);
1655
1656 xen_mc_issue(PARAVIRT_LAZY_MMU);
1657 } else {
1658
1659
1660 kmap_flush_unused();
1661 }
1662 }
1663}
1664
1665static void xen_alloc_pte(struct mm_struct *mm, unsigned long pfn)
1666{
1667 xen_alloc_ptpage(mm, pfn, PT_PTE);
1668}
1669
1670static void xen_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
1671{
1672 xen_alloc_ptpage(mm, pfn, PT_PMD);
1673}
1674
1675
1676static inline void xen_release_ptpage(unsigned long pfn, unsigned level)
1677{
1678 struct page *page = pfn_to_page(pfn);
1679 bool pinned = PagePinned(page);
1680
1681 trace_xen_mmu_release_ptpage(pfn, level, pinned);
1682
1683 if (pinned) {
1684 if (!PageHighMem(page)) {
1685 xen_mc_batch();
1686
1687 if (level == PT_PTE && USE_SPLIT_PTE_PTLOCKS)
1688 __pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, pfn);
1689
1690 __set_pfn_prot(pfn, PAGE_KERNEL);
1691
1692 xen_mc_issue(PARAVIRT_LAZY_MMU);
1693 }
1694 ClearPagePinned(page);
1695 }
1696}
1697
1698static void xen_release_pte(unsigned long pfn)
1699{
1700 xen_release_ptpage(pfn, PT_PTE);
1701}
1702
1703static void xen_release_pmd(unsigned long pfn)
1704{
1705 xen_release_ptpage(pfn, PT_PMD);
1706}
1707
1708#ifdef CONFIG_X86_64
1709static void xen_alloc_pud(struct mm_struct *mm, unsigned long pfn)
1710{
1711 xen_alloc_ptpage(mm, pfn, PT_PUD);
1712}
1713
1714static void xen_release_pud(unsigned long pfn)
1715{
1716 xen_release_ptpage(pfn, PT_PUD);
1717}
1718#endif
1719
1720void __init xen_reserve_top(void)
1721{
1722#ifdef CONFIG_X86_32
1723 unsigned long top = HYPERVISOR_VIRT_START;
1724 struct xen_platform_parameters pp;
1725
1726 if (HYPERVISOR_xen_version(XENVER_platform_parameters, &pp) == 0)
1727 top = pp.virt_start;
1728
1729 reserve_top_address(-top);
1730#endif
1731}
1732
1733
1734
1735
1736
1737static void * __init __ka(phys_addr_t paddr)
1738{
1739#ifdef CONFIG_X86_64
1740 return (void *)(paddr + __START_KERNEL_map);
1741#else
1742 return __va(paddr);
1743#endif
1744}
1745
1746
1747static unsigned long __init m2p(phys_addr_t maddr)
1748{
1749 phys_addr_t paddr;
1750
1751 maddr &= XEN_PTE_MFN_MASK;
1752 paddr = mfn_to_pfn(maddr >> PAGE_SHIFT) << PAGE_SHIFT;
1753
1754 return paddr;
1755}
1756
1757
1758static void * __init m2v(phys_addr_t maddr)
1759{
1760 return __ka(m2p(maddr));
1761}
1762
1763
1764static void __init set_page_prot_flags(void *addr, pgprot_t prot,
1765 unsigned long flags)
1766{
1767 unsigned long pfn = __pa(addr) >> PAGE_SHIFT;
1768 pte_t pte = pfn_pte(pfn, prot);
1769
1770 if (HYPERVISOR_update_va_mapping((unsigned long)addr, pte, flags))
1771 BUG();
1772}
1773static void __init set_page_prot(void *addr, pgprot_t prot)
1774{
1775 return set_page_prot_flags(addr, prot, UVMF_NONE);
1776}
1777#ifdef CONFIG_X86_32
1778static void __init xen_map_identity_early(pmd_t *pmd, unsigned long max_pfn)
1779{
1780 unsigned pmdidx, pteidx;
1781 unsigned ident_pte;
1782 unsigned long pfn;
1783
1784 level1_ident_pgt = extend_brk(sizeof(pte_t) * LEVEL1_IDENT_ENTRIES,
1785 PAGE_SIZE);
1786
1787 ident_pte = 0;
1788 pfn = 0;
1789 for (pmdidx = 0; pmdidx < PTRS_PER_PMD && pfn < max_pfn; pmdidx++) {
1790 pte_t *pte_page;
1791
1792
1793 if (pmd_present(pmd[pmdidx]))
1794 pte_page = m2v(pmd[pmdidx].pmd);
1795 else {
1796
1797 if (ident_pte == LEVEL1_IDENT_ENTRIES)
1798 break;
1799
1800 pte_page = &level1_ident_pgt[ident_pte];
1801 ident_pte += PTRS_PER_PTE;
1802
1803 pmd[pmdidx] = __pmd(__pa(pte_page) | _PAGE_TABLE);
1804 }
1805
1806
1807 for (pteidx = 0; pteidx < PTRS_PER_PTE; pteidx++, pfn++) {
1808 pte_t pte;
1809
1810 if (pfn > max_pfn_mapped)
1811 max_pfn_mapped = pfn;
1812
1813 if (!pte_none(pte_page[pteidx]))
1814 continue;
1815
1816 pte = pfn_pte(pfn, PAGE_KERNEL_EXEC);
1817 pte_page[pteidx] = pte;
1818 }
1819 }
1820
1821 for (pteidx = 0; pteidx < ident_pte; pteidx += PTRS_PER_PTE)
1822 set_page_prot(&level1_ident_pgt[pteidx], PAGE_KERNEL_RO);
1823
1824 set_page_prot(pmd, PAGE_KERNEL_RO);
1825}
1826#endif
1827void __init xen_setup_machphys_mapping(void)
1828{
1829 struct xen_machphys_mapping mapping;
1830
1831 if (HYPERVISOR_memory_op(XENMEM_machphys_mapping, &mapping) == 0) {
1832 machine_to_phys_mapping = (unsigned long *)mapping.v_start;
1833 machine_to_phys_nr = mapping.max_mfn + 1;
1834 } else {
1835 machine_to_phys_nr = MACH2PHYS_NR_ENTRIES;
1836 }
1837#ifdef CONFIG_X86_32
1838 WARN_ON((machine_to_phys_mapping + (machine_to_phys_nr - 1))
1839 < machine_to_phys_mapping);
1840#endif
1841}
1842
1843#ifdef CONFIG_X86_64
1844static void __init convert_pfn_mfn(void *v)
1845{
1846 pte_t *pte = v;
1847 int i;
1848
1849
1850
1851 for (i = 0; i < PTRS_PER_PTE; i++)
1852 pte[i] = xen_make_pte(pte[i].pte);
1853}
1854static void __init check_pt_base(unsigned long *pt_base, unsigned long *pt_end,
1855 unsigned long addr)
1856{
1857 if (*pt_base == PFN_DOWN(__pa(addr))) {
1858 set_page_prot_flags((void *)addr, PAGE_KERNEL, UVMF_INVLPG);
1859 clear_page((void *)addr);
1860 (*pt_base)++;
1861 }
1862 if (*pt_end == PFN_DOWN(__pa(addr))) {
1863 set_page_prot_flags((void *)addr, PAGE_KERNEL, UVMF_INVLPG);
1864 clear_page((void *)addr);
1865 (*pt_end)--;
1866 }
1867}
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
1879{
1880 pud_t *l3;
1881 pmd_t *l2;
1882 unsigned long addr[3];
1883 unsigned long pt_base, pt_end;
1884 unsigned i;
1885
1886
1887
1888
1889
1890 if (xen_start_info->mfn_list < __START_KERNEL_map)
1891 max_pfn_mapped = xen_start_info->first_p2m_pfn;
1892 else
1893 max_pfn_mapped = PFN_DOWN(__pa(xen_start_info->mfn_list));
1894
1895 pt_base = PFN_DOWN(__pa(xen_start_info->pt_base));
1896 pt_end = pt_base + xen_start_info->nr_pt_frames;
1897
1898
1899 init_top_pgt[0] = __pgd(0);
1900
1901
1902
1903
1904 convert_pfn_mfn(init_top_pgt);
1905
1906
1907 convert_pfn_mfn(level3_ident_pgt);
1908
1909
1910 convert_pfn_mfn(level3_kernel_pgt);
1911
1912
1913 convert_pfn_mfn(level2_fixmap_pgt);
1914
1915
1916 l3 = m2v(pgd[pgd_index(__START_KERNEL_map)].pgd);
1917 l2 = m2v(l3[pud_index(__START_KERNEL_map)].pud);
1918
1919 addr[0] = (unsigned long)pgd;
1920 addr[1] = (unsigned long)l3;
1921 addr[2] = (unsigned long)l2;
1922
1923
1924
1925
1926
1927
1928 copy_page(level2_ident_pgt, l2);
1929
1930 copy_page(level2_kernel_pgt, l2);
1931
1932
1933
1934
1935
1936 if (__supported_pte_mask & _PAGE_NX) {
1937 for (i = 0; i < PTRS_PER_PMD; ++i) {
1938 if (pmd_none(level2_ident_pgt[i]))
1939 continue;
1940 level2_ident_pgt[i] = pmd_set_flags(level2_ident_pgt[i], _PAGE_NX);
1941 }
1942 }
1943
1944
1945 i = pgd_index(xen_start_info->mfn_list);
1946 if (i && i < pgd_index(__START_KERNEL_map))
1947 init_top_pgt[i] = ((pgd_t *)xen_start_info->pt_base)[i];
1948
1949
1950 set_page_prot(init_top_pgt, PAGE_KERNEL_RO);
1951 set_page_prot(level3_ident_pgt, PAGE_KERNEL_RO);
1952 set_page_prot(level3_kernel_pgt, PAGE_KERNEL_RO);
1953 set_page_prot(level3_user_vsyscall, PAGE_KERNEL_RO);
1954 set_page_prot(level2_ident_pgt, PAGE_KERNEL_RO);
1955 set_page_prot(level2_kernel_pgt, PAGE_KERNEL_RO);
1956 set_page_prot(level2_fixmap_pgt, PAGE_KERNEL_RO);
1957 set_page_prot(level1_fixmap_pgt, PAGE_KERNEL_RO);
1958
1959
1960 pin_pagetable_pfn(MMUEXT_PIN_L4_TABLE,
1961 PFN_DOWN(__pa_symbol(init_top_pgt)));
1962
1963
1964 pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, PFN_DOWN(__pa(pgd)));
1965
1966
1967
1968
1969
1970 xen_mc_batch();
1971 __xen_write_cr3(true, __pa(init_top_pgt));
1972 xen_mc_issue(PARAVIRT_LAZY_CPU);
1973
1974
1975
1976
1977
1978
1979
1980 for (i = 0; i < ARRAY_SIZE(addr); i++)
1981 check_pt_base(&pt_base, &pt_end, addr[i]);
1982
1983
1984 xen_pt_base = PFN_PHYS(pt_base);
1985 xen_pt_size = (pt_end - pt_base) * PAGE_SIZE;
1986 memblock_reserve(xen_pt_base, xen_pt_size);
1987
1988
1989 xen_start_info = (struct start_info *)__va(__pa(xen_start_info));
1990}
1991
1992
1993
1994
1995static unsigned long __init xen_read_phys_ulong(phys_addr_t addr)
1996{
1997 unsigned long *vaddr;
1998 unsigned long val;
1999
2000 vaddr = early_memremap_ro(addr, sizeof(val));
2001 val = *vaddr;
2002 early_memunmap(vaddr, sizeof(val));
2003 return val;
2004}
2005
2006
2007
2008
2009
2010
2011static phys_addr_t __init xen_early_virt_to_phys(unsigned long vaddr)
2012{
2013 phys_addr_t pa;
2014 pgd_t pgd;
2015 pud_t pud;
2016 pmd_t pmd;
2017 pte_t pte;
2018
2019 pa = read_cr3_pa();
2020 pgd = native_make_pgd(xen_read_phys_ulong(pa + pgd_index(vaddr) *
2021 sizeof(pgd)));
2022 if (!pgd_present(pgd))
2023 return 0;
2024
2025 pa = pgd_val(pgd) & PTE_PFN_MASK;
2026 pud = native_make_pud(xen_read_phys_ulong(pa + pud_index(vaddr) *
2027 sizeof(pud)));
2028 if (!pud_present(pud))
2029 return 0;
2030 pa = pud_val(pud) & PTE_PFN_MASK;
2031 if (pud_large(pud))
2032 return pa + (vaddr & ~PUD_MASK);
2033
2034 pmd = native_make_pmd(xen_read_phys_ulong(pa + pmd_index(vaddr) *
2035 sizeof(pmd)));
2036 if (!pmd_present(pmd))
2037 return 0;
2038 pa = pmd_val(pmd) & PTE_PFN_MASK;
2039 if (pmd_large(pmd))
2040 return pa + (vaddr & ~PMD_MASK);
2041
2042 pte = native_make_pte(xen_read_phys_ulong(pa + pte_index(vaddr) *
2043 sizeof(pte)));
2044 if (!pte_present(pte))
2045 return 0;
2046 pa = pte_pfn(pte) << PAGE_SHIFT;
2047
2048 return pa | (vaddr & ~PAGE_MASK);
2049}
2050
2051
2052
2053
2054
2055void __init xen_relocate_p2m(void)
2056{
2057 phys_addr_t size, new_area, pt_phys, pmd_phys, pud_phys;
2058 unsigned long p2m_pfn, p2m_pfn_end, n_frames, pfn, pfn_end;
2059 int n_pte, n_pt, n_pmd, n_pud, idx_pte, idx_pt, idx_pmd, idx_pud;
2060 pte_t *pt;
2061 pmd_t *pmd;
2062 pud_t *pud;
2063 pgd_t *pgd;
2064 unsigned long *new_p2m;
2065 int save_pud;
2066
2067 size = PAGE_ALIGN(xen_start_info->nr_pages * sizeof(unsigned long));
2068 n_pte = roundup(size, PAGE_SIZE) >> PAGE_SHIFT;
2069 n_pt = roundup(size, PMD_SIZE) >> PMD_SHIFT;
2070 n_pmd = roundup(size, PUD_SIZE) >> PUD_SHIFT;
2071 n_pud = roundup(size, P4D_SIZE) >> P4D_SHIFT;
2072 n_frames = n_pte + n_pt + n_pmd + n_pud;
2073
2074 new_area = xen_find_free_area(PFN_PHYS(n_frames));
2075 if (!new_area) {
2076 xen_raw_console_write("Can't find new memory area for p2m needed due to E820 map conflict\n");
2077 BUG();
2078 }
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088 pud_phys = new_area;
2089 pmd_phys = pud_phys + PFN_PHYS(n_pud);
2090 pt_phys = pmd_phys + PFN_PHYS(n_pmd);
2091 p2m_pfn = PFN_DOWN(pt_phys) + n_pt;
2092
2093 pgd = __va(read_cr3_pa());
2094 new_p2m = (unsigned long *)(2 * PGDIR_SIZE);
2095 save_pud = n_pud;
2096 for (idx_pud = 0; idx_pud < n_pud; idx_pud++) {
2097 pud = early_memremap(pud_phys, PAGE_SIZE);
2098 clear_page(pud);
2099 for (idx_pmd = 0; idx_pmd < min(n_pmd, PTRS_PER_PUD);
2100 idx_pmd++) {
2101 pmd = early_memremap(pmd_phys, PAGE_SIZE);
2102 clear_page(pmd);
2103 for (idx_pt = 0; idx_pt < min(n_pt, PTRS_PER_PMD);
2104 idx_pt++) {
2105 pt = early_memremap(pt_phys, PAGE_SIZE);
2106 clear_page(pt);
2107 for (idx_pte = 0;
2108 idx_pte < min(n_pte, PTRS_PER_PTE);
2109 idx_pte++) {
2110 set_pte(pt + idx_pte,
2111 pfn_pte(p2m_pfn, PAGE_KERNEL));
2112 p2m_pfn++;
2113 }
2114 n_pte -= PTRS_PER_PTE;
2115 early_memunmap(pt, PAGE_SIZE);
2116 make_lowmem_page_readonly(__va(pt_phys));
2117 pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE,
2118 PFN_DOWN(pt_phys));
2119 set_pmd(pmd + idx_pt,
2120 __pmd(_PAGE_TABLE | pt_phys));
2121 pt_phys += PAGE_SIZE;
2122 }
2123 n_pt -= PTRS_PER_PMD;
2124 early_memunmap(pmd, PAGE_SIZE);
2125 make_lowmem_page_readonly(__va(pmd_phys));
2126 pin_pagetable_pfn(MMUEXT_PIN_L2_TABLE,
2127 PFN_DOWN(pmd_phys));
2128 set_pud(pud + idx_pmd, __pud(_PAGE_TABLE | pmd_phys));
2129 pmd_phys += PAGE_SIZE;
2130 }
2131 n_pmd -= PTRS_PER_PUD;
2132 early_memunmap(pud, PAGE_SIZE);
2133 make_lowmem_page_readonly(__va(pud_phys));
2134 pin_pagetable_pfn(MMUEXT_PIN_L3_TABLE, PFN_DOWN(pud_phys));
2135 set_pgd(pgd + 2 + idx_pud, __pgd(_PAGE_TABLE | pud_phys));
2136 pud_phys += PAGE_SIZE;
2137 }
2138
2139
2140 memcpy(new_p2m, xen_p2m_addr, size);
2141 xen_p2m_addr = new_p2m;
2142
2143
2144 p2m_pfn = PFN_DOWN(xen_early_virt_to_phys(xen_start_info->mfn_list));
2145 BUG_ON(!p2m_pfn);
2146 p2m_pfn_end = p2m_pfn + PFN_DOWN(size);
2147
2148 if (xen_start_info->mfn_list < __START_KERNEL_map) {
2149 pfn = xen_start_info->first_p2m_pfn;
2150 pfn_end = xen_start_info->first_p2m_pfn +
2151 xen_start_info->nr_p2m_frames;
2152 set_pgd(pgd + 1, __pgd(0));
2153 } else {
2154 pfn = p2m_pfn;
2155 pfn_end = p2m_pfn_end;
2156 }
2157
2158 memblock_free(PFN_PHYS(pfn), PAGE_SIZE * (pfn_end - pfn));
2159 while (pfn < pfn_end) {
2160 if (pfn == p2m_pfn) {
2161 pfn = p2m_pfn_end;
2162 continue;
2163 }
2164 make_lowmem_page_readwrite(__va(PFN_PHYS(pfn)));
2165 pfn++;
2166 }
2167
2168 xen_start_info->mfn_list = (unsigned long)xen_p2m_addr;
2169 xen_start_info->first_p2m_pfn = PFN_DOWN(new_area);
2170 xen_start_info->nr_p2m_frames = n_frames;
2171}
2172
2173#else
2174static RESERVE_BRK_ARRAY(pmd_t, initial_kernel_pmd, PTRS_PER_PMD);
2175static RESERVE_BRK_ARRAY(pmd_t, swapper_kernel_pmd, PTRS_PER_PMD);
2176
2177static void __init xen_write_cr3_init(unsigned long cr3)
2178{
2179 unsigned long pfn = PFN_DOWN(__pa(swapper_pg_dir));
2180
2181 BUG_ON(read_cr3_pa() != __pa(initial_page_table));
2182 BUG_ON(cr3 != __pa(swapper_pg_dir));
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194 swapper_kernel_pmd =
2195 extend_brk(sizeof(pmd_t) * PTRS_PER_PMD, PAGE_SIZE);
2196 copy_page(swapper_kernel_pmd, initial_kernel_pmd);
2197 swapper_pg_dir[KERNEL_PGD_BOUNDARY] =
2198 __pgd(__pa(swapper_kernel_pmd) | _PAGE_PRESENT);
2199 set_page_prot(swapper_kernel_pmd, PAGE_KERNEL_RO);
2200
2201 set_page_prot(swapper_pg_dir, PAGE_KERNEL_RO);
2202 xen_write_cr3(cr3);
2203 pin_pagetable_pfn(MMUEXT_PIN_L3_TABLE, pfn);
2204
2205 pin_pagetable_pfn(MMUEXT_UNPIN_TABLE,
2206 PFN_DOWN(__pa(initial_page_table)));
2207 set_page_prot(initial_page_table, PAGE_KERNEL);
2208 set_page_prot(initial_kernel_pmd, PAGE_KERNEL);
2209
2210 pv_mmu_ops.write_cr3 = &xen_write_cr3;
2211}
2212
2213
2214
2215
2216
2217
2218static phys_addr_t __init xen_find_pt_base(pmd_t *pmd)
2219{
2220 phys_addr_t pt_base, paddr;
2221 unsigned pmdidx;
2222
2223 pt_base = min(__pa(xen_start_info->pt_base), __pa(pmd));
2224
2225 for (pmdidx = 0; pmdidx < PTRS_PER_PMD; pmdidx++)
2226 if (pmd_present(pmd[pmdidx]) && !pmd_large(pmd[pmdidx])) {
2227 paddr = m2p(pmd[pmdidx].pmd);
2228 pt_base = min(pt_base, paddr);
2229 }
2230
2231 return pt_base;
2232}
2233
2234void __init xen_setup_kernel_pagetable(pgd_t *pgd, unsigned long max_pfn)
2235{
2236 pmd_t *kernel_pmd;
2237
2238 kernel_pmd = m2v(pgd[KERNEL_PGD_BOUNDARY].pgd);
2239
2240 xen_pt_base = xen_find_pt_base(kernel_pmd);
2241 xen_pt_size = xen_start_info->nr_pt_frames * PAGE_SIZE;
2242
2243 initial_kernel_pmd =
2244 extend_brk(sizeof(pmd_t) * PTRS_PER_PMD, PAGE_SIZE);
2245
2246 max_pfn_mapped = PFN_DOWN(xen_pt_base + xen_pt_size + 512 * 1024);
2247
2248 copy_page(initial_kernel_pmd, kernel_pmd);
2249
2250 xen_map_identity_early(initial_kernel_pmd, max_pfn);
2251
2252 copy_page(initial_page_table, pgd);
2253 initial_page_table[KERNEL_PGD_BOUNDARY] =
2254 __pgd(__pa(initial_kernel_pmd) | _PAGE_PRESENT);
2255
2256 set_page_prot(initial_kernel_pmd, PAGE_KERNEL_RO);
2257 set_page_prot(initial_page_table, PAGE_KERNEL_RO);
2258 set_page_prot(empty_zero_page, PAGE_KERNEL_RO);
2259
2260 pin_pagetable_pfn(MMUEXT_UNPIN_TABLE, PFN_DOWN(__pa(pgd)));
2261
2262 pin_pagetable_pfn(MMUEXT_PIN_L3_TABLE,
2263 PFN_DOWN(__pa(initial_page_table)));
2264 xen_write_cr3(__pa(initial_page_table));
2265
2266 memblock_reserve(xen_pt_base, xen_pt_size);
2267}
2268#endif
2269
2270void __init xen_reserve_special_pages(void)
2271{
2272 phys_addr_t paddr;
2273
2274 memblock_reserve(__pa(xen_start_info), PAGE_SIZE);
2275 if (xen_start_info->store_mfn) {
2276 paddr = PFN_PHYS(mfn_to_pfn(xen_start_info->store_mfn));
2277 memblock_reserve(paddr, PAGE_SIZE);
2278 }
2279 if (!xen_initial_domain()) {
2280 paddr = PFN_PHYS(mfn_to_pfn(xen_start_info->console.domU.mfn));
2281 memblock_reserve(paddr, PAGE_SIZE);
2282 }
2283}
2284
2285void __init xen_pt_check_e820(void)
2286{
2287 if (xen_is_e820_reserved(xen_pt_base, xen_pt_size)) {
2288 xen_raw_console_write("Xen hypervisor allocated page table memory conflicts with E820 map\n");
2289 BUG();
2290 }
2291}
2292
2293static unsigned char dummy_mapping[PAGE_SIZE] __page_aligned_bss;
2294
2295static void xen_set_fixmap(unsigned idx, phys_addr_t phys, pgprot_t prot)
2296{
2297 pte_t pte;
2298
2299 phys >>= PAGE_SHIFT;
2300
2301 switch (idx) {
2302 case FIX_BTMAP_END ... FIX_BTMAP_BEGIN:
2303#ifdef CONFIG_X86_32
2304 case FIX_WP_TEST:
2305# ifdef CONFIG_HIGHMEM
2306 case FIX_KMAP_BEGIN ... FIX_KMAP_END:
2307# endif
2308#elif defined(CONFIG_X86_VSYSCALL_EMULATION)
2309 case VSYSCALL_PAGE:
2310#endif
2311 case FIX_TEXT_POKE0:
2312 case FIX_TEXT_POKE1:
2313
2314 pte = pfn_pte(phys, prot);
2315 break;
2316
2317#ifdef CONFIG_X86_LOCAL_APIC
2318 case FIX_APIC_BASE:
2319 pte = pfn_pte(PFN_DOWN(__pa(dummy_mapping)), PAGE_KERNEL);
2320 break;
2321#endif
2322
2323#ifdef CONFIG_X86_IO_APIC
2324 case FIX_IO_APIC_BASE_0 ... FIX_IO_APIC_BASE_END:
2325
2326
2327
2328
2329 pte = pfn_pte(PFN_DOWN(__pa(dummy_mapping)), PAGE_KERNEL);
2330 break;
2331#endif
2332
2333 case FIX_PARAVIRT_BOOTMAP:
2334
2335
2336 pte = mfn_pte(phys, prot);
2337 break;
2338
2339 default:
2340
2341 pte = mfn_pte(phys, prot);
2342 break;
2343 }
2344
2345 __native_set_fixmap(idx, pte);
2346
2347#ifdef CONFIG_X86_VSYSCALL_EMULATION
2348
2349
2350 if (idx == VSYSCALL_PAGE) {
2351 unsigned long vaddr = __fix_to_virt(idx);
2352 set_pte_vaddr_pud(level3_user_vsyscall, vaddr, pte);
2353 }
2354#endif
2355}
2356
2357static void __init xen_post_allocator_init(void)
2358{
2359 pv_mmu_ops.set_pte = xen_set_pte;
2360 pv_mmu_ops.set_pmd = xen_set_pmd;
2361 pv_mmu_ops.set_pud = xen_set_pud;
2362#ifdef CONFIG_X86_64
2363 pv_mmu_ops.set_p4d = xen_set_p4d;
2364#endif
2365
2366
2367
2368 pv_mmu_ops.alloc_pte = xen_alloc_pte;
2369 pv_mmu_ops.alloc_pmd = xen_alloc_pmd;
2370 pv_mmu_ops.release_pte = xen_release_pte;
2371 pv_mmu_ops.release_pmd = xen_release_pmd;
2372#ifdef CONFIG_X86_64
2373 pv_mmu_ops.alloc_pud = xen_alloc_pud;
2374 pv_mmu_ops.release_pud = xen_release_pud;
2375#endif
2376 pv_mmu_ops.make_pte = PV_CALLEE_SAVE(xen_make_pte);
2377
2378#ifdef CONFIG_X86_64
2379 pv_mmu_ops.write_cr3 = &xen_write_cr3;
2380#endif
2381}
2382
2383static void xen_leave_lazy_mmu(void)
2384{
2385 preempt_disable();
2386 xen_mc_flush();
2387 paravirt_leave_lazy_mmu();
2388 preempt_enable();
2389}
2390
2391static const struct pv_mmu_ops xen_mmu_ops __initconst = {
2392 .read_cr2 = xen_read_cr2,
2393 .write_cr2 = xen_write_cr2,
2394
2395 .read_cr3 = xen_read_cr3,
2396 .write_cr3 = xen_write_cr3_init,
2397
2398 .flush_tlb_user = xen_flush_tlb,
2399 .flush_tlb_kernel = xen_flush_tlb,
2400 .flush_tlb_one_user = xen_flush_tlb_one_user,
2401 .flush_tlb_others = xen_flush_tlb_others,
2402
2403 .pgd_alloc = xen_pgd_alloc,
2404 .pgd_free = xen_pgd_free,
2405
2406 .alloc_pte = xen_alloc_pte_init,
2407 .release_pte = xen_release_pte_init,
2408 .alloc_pmd = xen_alloc_pmd_init,
2409 .release_pmd = xen_release_pmd_init,
2410
2411 .set_pte = xen_set_pte_init,
2412 .set_pte_at = xen_set_pte_at,
2413 .set_pmd = xen_set_pmd_hyper,
2414
2415 .ptep_modify_prot_start = __ptep_modify_prot_start,
2416 .ptep_modify_prot_commit = __ptep_modify_prot_commit,
2417
2418 .pte_val = PV_CALLEE_SAVE(xen_pte_val),
2419 .pgd_val = PV_CALLEE_SAVE(xen_pgd_val),
2420
2421 .make_pte = PV_CALLEE_SAVE(xen_make_pte_init),
2422 .make_pgd = PV_CALLEE_SAVE(xen_make_pgd),
2423
2424#ifdef CONFIG_X86_PAE
2425 .set_pte_atomic = xen_set_pte_atomic,
2426 .pte_clear = xen_pte_clear,
2427 .pmd_clear = xen_pmd_clear,
2428#endif
2429 .set_pud = xen_set_pud_hyper,
2430
2431 .make_pmd = PV_CALLEE_SAVE(xen_make_pmd),
2432 .pmd_val = PV_CALLEE_SAVE(xen_pmd_val),
2433
2434#ifdef CONFIG_X86_64
2435 .pud_val = PV_CALLEE_SAVE(xen_pud_val),
2436 .make_pud = PV_CALLEE_SAVE(xen_make_pud),
2437 .set_p4d = xen_set_p4d_hyper,
2438
2439 .alloc_pud = xen_alloc_pmd_init,
2440 .release_pud = xen_release_pmd_init,
2441
2442#if CONFIG_PGTABLE_LEVELS >= 5
2443 .p4d_val = PV_CALLEE_SAVE(xen_p4d_val),
2444 .make_p4d = PV_CALLEE_SAVE(xen_make_p4d),
2445#endif
2446#endif
2447
2448 .activate_mm = xen_activate_mm,
2449 .dup_mmap = xen_dup_mmap,
2450 .exit_mmap = xen_exit_mmap,
2451
2452 .lazy_mode = {
2453 .enter = paravirt_enter_lazy_mmu,
2454 .leave = xen_leave_lazy_mmu,
2455 .flush = paravirt_flush_lazy_mmu,
2456 },
2457
2458 .set_fixmap = xen_set_fixmap,
2459};
2460
2461void __init xen_init_mmu_ops(void)
2462{
2463 x86_init.paging.pagetable_init = xen_pagetable_init;
2464 x86_init.hyper.init_after_bootmem = xen_after_bootmem;
2465
2466 pv_mmu_ops = xen_mmu_ops;
2467
2468 memset(dummy_mapping, 0xff, PAGE_SIZE);
2469}
2470
2471
2472#define MAX_CONTIG_ORDER 9
2473static unsigned long discontig_frames[1<<MAX_CONTIG_ORDER];
2474
2475#define VOID_PTE (mfn_pte(0, __pgprot(0)))
2476static void xen_zap_pfn_range(unsigned long vaddr, unsigned int order,
2477 unsigned long *in_frames,
2478 unsigned long *out_frames)
2479{
2480 int i;
2481 struct multicall_space mcs;
2482
2483 xen_mc_batch();
2484 for (i = 0; i < (1UL<<order); i++, vaddr += PAGE_SIZE) {
2485 mcs = __xen_mc_entry(0);
2486
2487 if (in_frames)
2488 in_frames[i] = virt_to_mfn(vaddr);
2489
2490 MULTI_update_va_mapping(mcs.mc, vaddr, VOID_PTE, 0);
2491 __set_phys_to_machine(virt_to_pfn(vaddr), INVALID_P2M_ENTRY);
2492
2493 if (out_frames)
2494 out_frames[i] = virt_to_pfn(vaddr);
2495 }
2496 xen_mc_issue(0);
2497}
2498
2499
2500
2501
2502
2503
2504static void xen_remap_exchanged_ptes(unsigned long vaddr, int order,
2505 unsigned long *mfns,
2506 unsigned long first_mfn)
2507{
2508 unsigned i, limit;
2509 unsigned long mfn;
2510
2511 xen_mc_batch();
2512
2513 limit = 1u << order;
2514 for (i = 0; i < limit; i++, vaddr += PAGE_SIZE) {
2515 struct multicall_space mcs;
2516 unsigned flags;
2517
2518 mcs = __xen_mc_entry(0);
2519 if (mfns)
2520 mfn = mfns[i];
2521 else
2522 mfn = first_mfn + i;
2523
2524 if (i < (limit - 1))
2525 flags = 0;
2526 else {
2527 if (order == 0)
2528 flags = UVMF_INVLPG | UVMF_ALL;
2529 else
2530 flags = UVMF_TLB_FLUSH | UVMF_ALL;
2531 }
2532
2533 MULTI_update_va_mapping(mcs.mc, vaddr,
2534 mfn_pte(mfn, PAGE_KERNEL), flags);
2535
2536 set_phys_to_machine(virt_to_pfn(vaddr), mfn);
2537 }
2538
2539 xen_mc_issue(0);
2540}
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550static int xen_exchange_memory(unsigned long extents_in, unsigned int order_in,
2551 unsigned long *pfns_in,
2552 unsigned long extents_out,
2553 unsigned int order_out,
2554 unsigned long *mfns_out,
2555 unsigned int address_bits)
2556{
2557 long rc;
2558 int success;
2559
2560 struct xen_memory_exchange exchange = {
2561 .in = {
2562 .nr_extents = extents_in,
2563 .extent_order = order_in,
2564 .extent_start = pfns_in,
2565 .domid = DOMID_SELF
2566 },
2567 .out = {
2568 .nr_extents = extents_out,
2569 .extent_order = order_out,
2570 .extent_start = mfns_out,
2571 .address_bits = address_bits,
2572 .domid = DOMID_SELF
2573 }
2574 };
2575
2576 BUG_ON(extents_in << order_in != extents_out << order_out);
2577
2578 rc = HYPERVISOR_memory_op(XENMEM_exchange, &exchange);
2579 success = (exchange.nr_exchanged == extents_in);
2580
2581 BUG_ON(!success && ((exchange.nr_exchanged != 0) || (rc == 0)));
2582 BUG_ON(success && (rc != 0));
2583
2584 return success;
2585}
2586
2587int xen_create_contiguous_region(phys_addr_t pstart, unsigned int order,
2588 unsigned int address_bits,
2589 dma_addr_t *dma_handle)
2590{
2591 unsigned long *in_frames = discontig_frames, out_frame;
2592 unsigned long flags;
2593 int success;
2594 unsigned long vstart = (unsigned long)phys_to_virt(pstart);
2595
2596
2597
2598
2599
2600
2601
2602 if (unlikely(order > MAX_CONTIG_ORDER))
2603 return -ENOMEM;
2604
2605 memset((void *) vstart, 0, PAGE_SIZE << order);
2606
2607 spin_lock_irqsave(&xen_reservation_lock, flags);
2608
2609
2610 xen_zap_pfn_range(vstart, order, in_frames, NULL);
2611
2612
2613 out_frame = virt_to_pfn(vstart);
2614 success = xen_exchange_memory(1UL << order, 0, in_frames,
2615 1, order, &out_frame,
2616 address_bits);
2617
2618
2619 if (success)
2620 xen_remap_exchanged_ptes(vstart, order, NULL, out_frame);
2621 else
2622 xen_remap_exchanged_ptes(vstart, order, in_frames, 0);
2623
2624 spin_unlock_irqrestore(&xen_reservation_lock, flags);
2625
2626 *dma_handle = virt_to_machine(vstart).maddr;
2627 return success ? 0 : -ENOMEM;
2628}
2629EXPORT_SYMBOL_GPL(xen_create_contiguous_region);
2630
2631void xen_destroy_contiguous_region(phys_addr_t pstart, unsigned int order)
2632{
2633 unsigned long *out_frames = discontig_frames, in_frame;
2634 unsigned long flags;
2635 int success;
2636 unsigned long vstart;
2637
2638 if (unlikely(order > MAX_CONTIG_ORDER))
2639 return;
2640
2641 vstart = (unsigned long)phys_to_virt(pstart);
2642 memset((void *) vstart, 0, PAGE_SIZE << order);
2643
2644 spin_lock_irqsave(&xen_reservation_lock, flags);
2645
2646
2647 in_frame = virt_to_mfn(vstart);
2648
2649
2650 xen_zap_pfn_range(vstart, order, NULL, out_frames);
2651
2652
2653 success = xen_exchange_memory(1, order, &in_frame, 1UL << order,
2654 0, out_frames, 0);
2655
2656
2657 if (success)
2658 xen_remap_exchanged_ptes(vstart, order, out_frames, 0);
2659 else
2660 xen_remap_exchanged_ptes(vstart, order, NULL, in_frame);
2661
2662 spin_unlock_irqrestore(&xen_reservation_lock, flags);
2663}
2664EXPORT_SYMBOL_GPL(xen_destroy_contiguous_region);
2665
2666#ifdef CONFIG_KEXEC_CORE
2667phys_addr_t paddr_vmcoreinfo_note(void)
2668{
2669 if (xen_pv_domain())
2670 return virt_to_machine(vmcoreinfo_note).maddr;
2671 else
2672 return __pa(vmcoreinfo_note);
2673}
2674#endif
2675