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35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <linux/dmi.h>
44#include <linux/gfp.h>
45#include <linux/msi.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_cmnd.h>
48#include <linux/libata.h>
49#include <linux/ahci-remap.h>
50#include <linux/io-64-nonatomic-lo-hi.h>
51#include "ahci.h"
52
53#define DRV_NAME "ahci"
54#define DRV_VERSION "3.0"
55
56enum {
57 AHCI_PCI_BAR_STA2X11 = 0,
58 AHCI_PCI_BAR_CAVIUM = 0,
59 AHCI_PCI_BAR_ENMOTUS = 2,
60 AHCI_PCI_BAR_CAVIUM_GEN5 = 4,
61 AHCI_PCI_BAR_STANDARD = 5,
62};
63
64enum board_ids {
65
66 board_ahci,
67 board_ahci_ign_iferr,
68 board_ahci_mobile,
69 board_ahci_nomsi,
70 board_ahci_noncq,
71 board_ahci_nosntf,
72 board_ahci_yes_fbs,
73
74
75 board_ahci_avn,
76 board_ahci_mcp65,
77 board_ahci_mcp77,
78 board_ahci_mcp89,
79 board_ahci_mv,
80 board_ahci_sb600,
81 board_ahci_sb700,
82 board_ahci_vt8251,
83
84
85 board_ahci_mcp_linux = board_ahci_mcp65,
86 board_ahci_mcp67 = board_ahci_mcp65,
87 board_ahci_mcp73 = board_ahci_mcp65,
88 board_ahci_mcp79 = board_ahci_mcp77,
89};
90
91static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
92static void ahci_remove_one(struct pci_dev *dev);
93static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
94 unsigned long deadline);
95static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
96 unsigned long deadline);
97static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
98static bool is_mcp89_apple(struct pci_dev *pdev);
99static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
100 unsigned long deadline);
101#ifdef CONFIG_PM
102static int ahci_pci_device_runtime_suspend(struct device *dev);
103static int ahci_pci_device_runtime_resume(struct device *dev);
104#ifdef CONFIG_PM_SLEEP
105static int ahci_pci_device_suspend(struct device *dev);
106static int ahci_pci_device_resume(struct device *dev);
107#endif
108#endif
109
110static struct scsi_host_template ahci_sht = {
111 AHCI_SHT("ahci"),
112};
113
114static struct ata_port_operations ahci_vt8251_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_vt8251_hardreset,
117};
118
119static struct ata_port_operations ahci_p5wdh_ops = {
120 .inherits = &ahci_ops,
121 .hardreset = ahci_p5wdh_hardreset,
122};
123
124static struct ata_port_operations ahci_avn_ops = {
125 .inherits = &ahci_ops,
126 .hardreset = ahci_avn_hardreset,
127};
128
129static const struct ata_port_info ahci_port_info[] = {
130
131 [board_ahci] = {
132 .flags = AHCI_FLAG_COMMON,
133 .pio_mask = ATA_PIO4,
134 .udma_mask = ATA_UDMA6,
135 .port_ops = &ahci_ops,
136 },
137 [board_ahci_ign_iferr] = {
138 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
144 [board_ahci_mobile] = {
145 AHCI_HFLAGS (AHCI_HFLAG_IS_MOBILE),
146 .flags = AHCI_FLAG_COMMON,
147 .pio_mask = ATA_PIO4,
148 .udma_mask = ATA_UDMA6,
149 .port_ops = &ahci_ops,
150 },
151 [board_ahci_nomsi] = {
152 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_noncq] = {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_nosntf] = {
166 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
167 .flags = AHCI_FLAG_COMMON,
168 .pio_mask = ATA_PIO4,
169 .udma_mask = ATA_UDMA6,
170 .port_ops = &ahci_ops,
171 },
172 [board_ahci_yes_fbs] = {
173 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
174 .flags = AHCI_FLAG_COMMON,
175 .pio_mask = ATA_PIO4,
176 .udma_mask = ATA_UDMA6,
177 .port_ops = &ahci_ops,
178 },
179
180 [board_ahci_avn] = {
181 .flags = AHCI_FLAG_COMMON,
182 .pio_mask = ATA_PIO4,
183 .udma_mask = ATA_UDMA6,
184 .port_ops = &ahci_avn_ops,
185 },
186 [board_ahci_mcp65] = {
187 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
188 AHCI_HFLAG_YES_NCQ),
189 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_ops,
193 },
194 [board_ahci_mcp77] = {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_ops,
200 },
201 [board_ahci_mcp89] = {
202 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
203 .flags = AHCI_FLAG_COMMON,
204 .pio_mask = ATA_PIO4,
205 .udma_mask = ATA_UDMA6,
206 .port_ops = &ahci_ops,
207 },
208 [board_ahci_mv] = {
209 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
210 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
211 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
212 .pio_mask = ATA_PIO4,
213 .udma_mask = ATA_UDMA6,
214 .port_ops = &ahci_ops,
215 },
216 [board_ahci_sb600] = {
217 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
218 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
219 AHCI_HFLAG_32BIT_ONLY),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
224 },
225 [board_ahci_sb700] = {
226 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
227 .flags = AHCI_FLAG_COMMON,
228 .pio_mask = ATA_PIO4,
229 .udma_mask = ATA_UDMA6,
230 .port_ops = &ahci_pmp_retry_srst_ops,
231 },
232 [board_ahci_vt8251] = {
233 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
234 .flags = AHCI_FLAG_COMMON,
235 .pio_mask = ATA_PIO4,
236 .udma_mask = ATA_UDMA6,
237 .port_ops = &ahci_vt8251_ops,
238 },
239};
240
241static const struct pci_device_id ahci_pci_tbl[] = {
242
243 { PCI_VDEVICE(INTEL, 0x2652), board_ahci },
244 { PCI_VDEVICE(INTEL, 0x2653), board_ahci },
245 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci },
246 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci },
247 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci },
248 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr },
249 { PCI_VDEVICE(INTEL, 0x2681), board_ahci },
250 { PCI_VDEVICE(INTEL, 0x2682), board_ahci },
251 { PCI_VDEVICE(INTEL, 0x2683), board_ahci },
252 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci },
253 { PCI_VDEVICE(INTEL, 0x2821), board_ahci },
254 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf },
255 { PCI_VDEVICE(INTEL, 0x2824), board_ahci },
256 { PCI_VDEVICE(INTEL, 0x2829), board_ahci },
257 { PCI_VDEVICE(INTEL, 0x282a), board_ahci },
258 { PCI_VDEVICE(INTEL, 0x2922), board_ahci },
259 { PCI_VDEVICE(INTEL, 0x2923), board_ahci },
260 { PCI_VDEVICE(INTEL, 0x2924), board_ahci },
261 { PCI_VDEVICE(INTEL, 0x2925), board_ahci },
262 { PCI_VDEVICE(INTEL, 0x2927), board_ahci },
263 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_mobile },
264 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_mobile },
265 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_mobile },
266 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_mobile },
267 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_mobile },
268 { PCI_VDEVICE(INTEL, 0x294d), board_ahci },
269 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_mobile },
270 { PCI_VDEVICE(INTEL, 0x502a), board_ahci },
271 { PCI_VDEVICE(INTEL, 0x502b), board_ahci },
272 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci },
273 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci },
274 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci },
275 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci },
276 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci },
277 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci },
278 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci },
279 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_mobile },
280 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci },
281 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_mobile },
282 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci },
283 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci },
284 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci },
285 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci },
286 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci },
287 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci },
288 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci },
289 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci },
290 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci },
291 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci },
292 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci },
293 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci },
294 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci },
295 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci },
296 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci },
297 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci },
298 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci },
299 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci },
300 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci },
301 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci },
302 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci },
303 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci },
304 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_mobile },
305 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci },
306 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_mobile },
307 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci },
308 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci },
309 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci },
310 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci },
311 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci },
312 { PCI_VDEVICE(INTEL, 0x2826), board_ahci },
313 { PCI_VDEVICE(INTEL, 0x2323), board_ahci },
314 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci },
315 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_mobile },
316 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci },
317 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci },
318 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci },
319 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_mobile },
320 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci },
321 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci },
322 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_mobile },
323 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci },
324 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_mobile },
325 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci },
326 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_mobile },
327 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci },
328 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_mobile },
329 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_mobile },
330 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_mobile },
331 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_mobile },
332 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_mobile },
333 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_mobile },
334 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_mobile },
335 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_mobile },
336 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_mobile },
337 { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_mobile },
338 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci },
339 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci },
340 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci },
341 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci },
342 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci },
343 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci },
344 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci },
345 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci },
346 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn },
347 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn },
348 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn },
349 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn },
350 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn },
351 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn },
352 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn },
353 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn },
354 { PCI_VDEVICE(INTEL, 0x2823), board_ahci },
355 { PCI_VDEVICE(INTEL, 0x2827), board_ahci },
356 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci },
357 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci },
358 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci },
359 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci },
360 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci },
361 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci },
362 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci },
363 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci },
364 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci },
365 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_mobile },
366 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_mobile },
367 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_mobile },
368 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_mobile },
369 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci },
370 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_mobile },
371 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci },
372 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_mobile },
373 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci },
374 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_mobile },
375 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci },
376 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_mobile },
377 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_mobile },
378 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_mobile },
379 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_mobile },
380 { PCI_VDEVICE(INTEL, 0xa102), board_ahci },
381 { PCI_VDEVICE(INTEL, 0xa103), board_ahci_mobile },
382 { PCI_VDEVICE(INTEL, 0xa105), board_ahci },
383 { PCI_VDEVICE(INTEL, 0xa106), board_ahci },
384 { PCI_VDEVICE(INTEL, 0xa107), board_ahci_mobile },
385 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci },
386 { PCI_VDEVICE(INTEL, 0x2822), board_ahci },
387 { PCI_VDEVICE(INTEL, 0x2823), board_ahci },
388 { PCI_VDEVICE(INTEL, 0x2826), board_ahci },
389 { PCI_VDEVICE(INTEL, 0x2827), board_ahci },
390 { PCI_VDEVICE(INTEL, 0xa182), board_ahci },
391 { PCI_VDEVICE(INTEL, 0xa186), board_ahci },
392 { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci },
393 { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci },
394 { PCI_VDEVICE(INTEL, 0xa202), board_ahci },
395 { PCI_VDEVICE(INTEL, 0xa206), board_ahci },
396 { PCI_VDEVICE(INTEL, 0xa252), board_ahci },
397 { PCI_VDEVICE(INTEL, 0xa256), board_ahci },
398 { PCI_VDEVICE(INTEL, 0xa356), board_ahci },
399 { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_mobile },
400 { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_mobile },
401 { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_mobile },
402 { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_mobile },
403
404
405 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
406 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
407
408 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
409 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
410
411
412
413 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 },
414 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 },
415 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 },
416 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 },
417 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 },
418 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 },
419 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 },
420
421
422 { PCI_VDEVICE(AMD, 0x7800), board_ahci },
423 { PCI_VDEVICE(AMD, 0x7900), board_ahci },
424
425 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
426 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
427
428
429 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 },
430 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 },
431
432
433 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },
434 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },
435 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },
436 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },
437 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },
438 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },
439 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },
440 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },
441 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },
442 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },
443 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },
444 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },
445 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },
446 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },
447 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },
448 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },
449 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },
450 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },
451 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },
452 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },
453 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },
454 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },
455 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },
456 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },
457 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },
458 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },
459 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },
460 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },
461 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },
462 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },
463 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },
464 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },
465 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },
466 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },
467 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },
468 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },
469 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },
470 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },
471 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },
472 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },
473 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },
474 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },
475 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },
476 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },
477 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },
478 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },
479 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },
480 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },
481 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },
482 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },
483 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },
484 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },
485 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },
486 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },
487 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },
488 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },
489 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },
490 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },
491 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },
492 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },
493 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },
494 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },
495 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },
496 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },
497 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },
498 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },
499 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },
500 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },
501 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },
502 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },
503 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },
504 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },
505 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },
506 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },
507 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },
508 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },
509 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },
510 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },
511 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },
512 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },
513 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },
514 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },
515 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },
516 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },
517
518
519 { PCI_VDEVICE(SI, 0x1184), board_ahci },
520 { PCI_VDEVICE(SI, 0x1185), board_ahci },
521 { PCI_VDEVICE(SI, 0x0186), board_ahci },
522
523
524 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },
525
526
527 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },
528 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
530 .class = PCI_CLASS_STORAGE_SATA_AHCI,
531 .class_mask = 0xffffff,
532 .driver_data = board_ahci_yes_fbs },
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
534 .driver_data = board_ahci_yes_fbs },
535 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
536 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
537 .driver_data = board_ahci_yes_fbs },
538 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
539 .driver_data = board_ahci_yes_fbs },
540 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
541 .driver_data = board_ahci_yes_fbs },
542 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
543 .driver_data = board_ahci_yes_fbs },
544 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
545 .driver_data = board_ahci_yes_fbs },
546 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
547 .driver_data = board_ahci_yes_fbs },
548 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2),
549 .driver_data = board_ahci_yes_fbs },
550 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
551 .driver_data = board_ahci_yes_fbs },
552 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
553 .driver_data = board_ahci_yes_fbs },
554 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
555 .driver_data = board_ahci_yes_fbs },
556 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645),
557 .driver_data = board_ahci_yes_fbs },
558
559
560 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },
561 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci },
562
563
564 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },
565 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },
566 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },
567 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },
568 { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci },
569 { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci },
570
571
572
573
574
575 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
576 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
577
578
579 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
580
581
582 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
583 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
584
585 { }
586};
587
588static const struct dev_pm_ops ahci_pci_pm_ops = {
589 SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
590 SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
591 ahci_pci_device_runtime_resume, NULL)
592};
593
594static struct pci_driver ahci_pci_driver = {
595 .name = DRV_NAME,
596 .id_table = ahci_pci_tbl,
597 .probe = ahci_init_one,
598 .remove = ahci_remove_one,
599 .driver = {
600 .pm = &ahci_pci_pm_ops,
601 },
602};
603
604#if IS_ENABLED(CONFIG_PATA_MARVELL)
605static int marvell_enable;
606#else
607static int marvell_enable = 1;
608#endif
609module_param(marvell_enable, int, 0644);
610MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
611
612static int mobile_lpm_policy = CONFIG_SATA_MOBILE_LPM_POLICY;
613module_param(mobile_lpm_policy, int, 0644);
614MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
615
616static void ahci_pci_save_initial_config(struct pci_dev *pdev,
617 struct ahci_host_priv *hpriv)
618{
619 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
620 dev_info(&pdev->dev, "JMB361 has only one port\n");
621 hpriv->force_port_map = 1;
622 }
623
624
625
626
627
628
629 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
630 if (pdev->device == 0x6121)
631 hpriv->mask_port_map = 0x3;
632 else
633 hpriv->mask_port_map = 0xf;
634 dev_info(&pdev->dev,
635 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
636 }
637
638 ahci_save_initial_config(&pdev->dev, hpriv);
639}
640
641static int ahci_pci_reset_controller(struct ata_host *host)
642{
643 struct pci_dev *pdev = to_pci_dev(host->dev);
644 int rc;
645
646 rc = ahci_reset_controller(host);
647 if (rc)
648 return rc;
649
650 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
651 struct ahci_host_priv *hpriv = host->private_data;
652 u16 tmp16;
653
654
655 pci_read_config_word(pdev, 0x92, &tmp16);
656 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
657 tmp16 |= hpriv->port_map;
658 pci_write_config_word(pdev, 0x92, tmp16);
659 }
660 }
661
662 return 0;
663}
664
665static void ahci_pci_init_controller(struct ata_host *host)
666{
667 struct ahci_host_priv *hpriv = host->private_data;
668 struct pci_dev *pdev = to_pci_dev(host->dev);
669 void __iomem *port_mmio;
670 u32 tmp;
671 int mv;
672
673 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
674 if (pdev->device == 0x6121)
675 mv = 2;
676 else
677 mv = 4;
678 port_mmio = __ahci_port_base(host, mv);
679
680 writel(0, port_mmio + PORT_IRQ_MASK);
681
682
683 tmp = readl(port_mmio + PORT_IRQ_STAT);
684 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
685 if (tmp)
686 writel(tmp, port_mmio + PORT_IRQ_STAT);
687 }
688
689 ahci_init_controller(host);
690}
691
692static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
693 unsigned long deadline)
694{
695 struct ata_port *ap = link->ap;
696 struct ahci_host_priv *hpriv = ap->host->private_data;
697 bool online;
698 int rc;
699
700 DPRINTK("ENTER\n");
701
702 hpriv->stop_engine(ap);
703
704 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
705 deadline, &online, NULL);
706
707 hpriv->start_engine(ap);
708
709 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
710
711
712
713
714 return online ? -EAGAIN : rc;
715}
716
717static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
718 unsigned long deadline)
719{
720 struct ata_port *ap = link->ap;
721 struct ahci_port_priv *pp = ap->private_data;
722 struct ahci_host_priv *hpriv = ap->host->private_data;
723 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
724 struct ata_taskfile tf;
725 bool online;
726 int rc;
727
728 hpriv->stop_engine(ap);
729
730
731 ata_tf_init(link->device, &tf);
732 tf.command = ATA_BUSY;
733 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
734
735 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
736 deadline, &online, NULL);
737
738 hpriv->start_engine(ap);
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753 if (online) {
754 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
755 ahci_check_ready);
756 if (rc)
757 ahci_kick_engine(ap);
758 }
759 return rc;
760}
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
778 unsigned long deadline)
779{
780 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
781 struct ata_port *ap = link->ap;
782 struct ahci_port_priv *pp = ap->private_data;
783 struct ahci_host_priv *hpriv = ap->host->private_data;
784 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
785 unsigned long tmo = deadline - jiffies;
786 struct ata_taskfile tf;
787 bool online;
788 int rc, i;
789
790 DPRINTK("ENTER\n");
791
792 hpriv->stop_engine(ap);
793
794 for (i = 0; i < 2; i++) {
795 u16 val;
796 u32 sstatus;
797 int port = ap->port_no;
798 struct ata_host *host = ap->host;
799 struct pci_dev *pdev = to_pci_dev(host->dev);
800
801
802 ata_tf_init(link->device, &tf);
803 tf.command = ATA_BUSY;
804 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
805
806 rc = sata_link_hardreset(link, timing, deadline, &online,
807 ahci_check_ready);
808
809 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
810 (sstatus & 0xf) != 1)
811 break;
812
813 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
814 port);
815
816 pci_read_config_word(pdev, 0x92, &val);
817 val &= ~(1 << port);
818 pci_write_config_word(pdev, 0x92, val);
819 ata_msleep(ap, 1000);
820 val |= 1 << port;
821 pci_write_config_word(pdev, 0x92, val);
822 deadline += tmo;
823 }
824
825 hpriv->start_engine(ap);
826
827 if (online)
828 *class = ahci_dev_classify(ap);
829
830 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
831 return rc;
832}
833
834
835#ifdef CONFIG_PM
836static void ahci_pci_disable_interrupts(struct ata_host *host)
837{
838 struct ahci_host_priv *hpriv = host->private_data;
839 void __iomem *mmio = hpriv->mmio;
840 u32 ctl;
841
842
843
844
845
846 ctl = readl(mmio + HOST_CTL);
847 ctl &= ~HOST_IRQ_EN;
848 writel(ctl, mmio + HOST_CTL);
849 readl(mmio + HOST_CTL);
850}
851
852static int ahci_pci_device_runtime_suspend(struct device *dev)
853{
854 struct pci_dev *pdev = to_pci_dev(dev);
855 struct ata_host *host = pci_get_drvdata(pdev);
856
857 ahci_pci_disable_interrupts(host);
858 return 0;
859}
860
861static int ahci_pci_device_runtime_resume(struct device *dev)
862{
863 struct pci_dev *pdev = to_pci_dev(dev);
864 struct ata_host *host = pci_get_drvdata(pdev);
865 int rc;
866
867 rc = ahci_pci_reset_controller(host);
868 if (rc)
869 return rc;
870 ahci_pci_init_controller(host);
871 return 0;
872}
873
874#ifdef CONFIG_PM_SLEEP
875static int ahci_pci_device_suspend(struct device *dev)
876{
877 struct pci_dev *pdev = to_pci_dev(dev);
878 struct ata_host *host = pci_get_drvdata(pdev);
879 struct ahci_host_priv *hpriv = host->private_data;
880
881 if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
882 dev_err(&pdev->dev,
883 "BIOS update required for suspend/resume\n");
884 return -EIO;
885 }
886
887 ahci_pci_disable_interrupts(host);
888 return ata_host_suspend(host, PMSG_SUSPEND);
889}
890
891static int ahci_pci_device_resume(struct device *dev)
892{
893 struct pci_dev *pdev = to_pci_dev(dev);
894 struct ata_host *host = pci_get_drvdata(pdev);
895 int rc;
896
897
898 if (is_mcp89_apple(pdev))
899 ahci_mcp89_apple_enable(pdev);
900
901 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
902 rc = ahci_pci_reset_controller(host);
903 if (rc)
904 return rc;
905
906 ahci_pci_init_controller(host);
907 }
908
909 ata_host_resume(host);
910
911 return 0;
912}
913#endif
914
915#endif
916
917static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
918{
919 int rc;
920
921
922
923
924
925 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
926 return 0;
927
928 if (using_dac &&
929 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
930 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
931 if (rc) {
932 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
933 if (rc) {
934 dev_err(&pdev->dev,
935 "64-bit DMA enable failed\n");
936 return rc;
937 }
938 }
939 } else {
940 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
941 if (rc) {
942 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
943 return rc;
944 }
945 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
946 if (rc) {
947 dev_err(&pdev->dev,
948 "32-bit consistent DMA enable failed\n");
949 return rc;
950 }
951 }
952 return 0;
953}
954
955static void ahci_pci_print_info(struct ata_host *host)
956{
957 struct pci_dev *pdev = to_pci_dev(host->dev);
958 u16 cc;
959 const char *scc_s;
960
961 pci_read_config_word(pdev, 0x0a, &cc);
962 if (cc == PCI_CLASS_STORAGE_IDE)
963 scc_s = "IDE";
964 else if (cc == PCI_CLASS_STORAGE_SATA)
965 scc_s = "SATA";
966 else if (cc == PCI_CLASS_STORAGE_RAID)
967 scc_s = "RAID";
968 else
969 scc_s = "unknown";
970
971 ahci_print_info(host, scc_s);
972}
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992static void ahci_p5wdh_workaround(struct ata_host *host)
993{
994 static const struct dmi_system_id sysids[] = {
995 {
996 .ident = "P5W DH Deluxe",
997 .matches = {
998 DMI_MATCH(DMI_SYS_VENDOR,
999 "ASUSTEK COMPUTER INC"),
1000 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
1001 },
1002 },
1003 { }
1004 };
1005 struct pci_dev *pdev = to_pci_dev(host->dev);
1006
1007 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
1008 dmi_check_system(sysids)) {
1009 struct ata_port *ap = host->ports[1];
1010
1011 dev_info(&pdev->dev,
1012 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1013
1014 ap->ops = &ahci_p5wdh_ops;
1015 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1016 }
1017}
1018
1019
1020
1021
1022
1023static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1024{
1025 u32 val;
1026
1027 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1028
1029 pci_read_config_dword(pdev, 0xf8, &val);
1030 val |= 1 << 0x1b;
1031
1032
1033 pci_write_config_dword(pdev, 0xf8, val);
1034
1035 pci_read_config_dword(pdev, 0x54c, &val);
1036 val |= 1 << 0xc;
1037 pci_write_config_dword(pdev, 0x54c, val);
1038
1039 pci_read_config_dword(pdev, 0x4a4, &val);
1040 val &= 0xff;
1041 val |= 0x01060100;
1042 pci_write_config_dword(pdev, 0x4a4, val);
1043
1044 pci_read_config_dword(pdev, 0x54c, &val);
1045 val &= ~(1 << 0xc);
1046 pci_write_config_dword(pdev, 0x54c, val);
1047
1048 pci_read_config_dword(pdev, 0xf8, &val);
1049 val &= ~(1 << 0x1b);
1050 pci_write_config_dword(pdev, 0xf8, val);
1051}
1052
1053static bool is_mcp89_apple(struct pci_dev *pdev)
1054{
1055 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1056 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1057 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1058 pdev->subsystem_device == 0xcb89;
1059}
1060
1061
1062static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1063{
1064 static const struct dmi_system_id sysids[] = {
1065
1066
1067
1068
1069
1070
1071
1072 {
1073 .ident = "ASUS M2A-VM",
1074 .matches = {
1075 DMI_MATCH(DMI_BOARD_VENDOR,
1076 "ASUSTeK Computer INC."),
1077 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1078 },
1079 .driver_data = "20071026",
1080 },
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097 {
1098 .ident = "MSI K9A2 Platinum",
1099 .matches = {
1100 DMI_MATCH(DMI_BOARD_VENDOR,
1101 "MICRO-STAR INTER"),
1102 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1103 },
1104 },
1105
1106
1107
1108
1109
1110
1111
1112
1113 {
1114 .ident = "MSI K9AGM2",
1115 .matches = {
1116 DMI_MATCH(DMI_BOARD_VENDOR,
1117 "MICRO-STAR INTER"),
1118 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1119 },
1120 },
1121
1122
1123
1124
1125 {
1126 .ident = "ASUS M3A",
1127 .matches = {
1128 DMI_MATCH(DMI_BOARD_VENDOR,
1129 "ASUSTeK Computer INC."),
1130 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1131 },
1132 },
1133 { }
1134 };
1135 const struct dmi_system_id *match;
1136 int year, month, date;
1137 char buf[9];
1138
1139 match = dmi_first_match(sysids);
1140 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1141 !match)
1142 return false;
1143
1144 if (!match->driver_data)
1145 goto enable_64bit;
1146
1147 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1148 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1149
1150 if (strcmp(buf, match->driver_data) >= 0)
1151 goto enable_64bit;
1152 else {
1153 dev_warn(&pdev->dev,
1154 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1155 match->ident);
1156 return false;
1157 }
1158
1159enable_64bit:
1160 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1161 return true;
1162}
1163
1164static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1165{
1166 static const struct dmi_system_id broken_systems[] = {
1167 {
1168 .ident = "HP Compaq nx6310",
1169 .matches = {
1170 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1171 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1172 },
1173
1174 .driver_data = (void *)0x1FUL,
1175 },
1176 {
1177 .ident = "HP Compaq 6720s",
1178 .matches = {
1179 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1180 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1181 },
1182
1183 .driver_data = (void *)0x1FUL,
1184 },
1185
1186 { }
1187 };
1188 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1189
1190 if (dmi) {
1191 unsigned long slot = (unsigned long)dmi->driver_data;
1192
1193 return slot == PCI_SLOT(pdev->devfn);
1194 }
1195
1196 return false;
1197}
1198
1199static bool ahci_broken_suspend(struct pci_dev *pdev)
1200{
1201 static const struct dmi_system_id sysids[] = {
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215 {
1216 .ident = "dv4",
1217 .matches = {
1218 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1219 DMI_MATCH(DMI_PRODUCT_NAME,
1220 "HP Pavilion dv4 Notebook PC"),
1221 },
1222 .driver_data = "20090105",
1223 },
1224 {
1225 .ident = "dv5",
1226 .matches = {
1227 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1228 DMI_MATCH(DMI_PRODUCT_NAME,
1229 "HP Pavilion dv5 Notebook PC"),
1230 },
1231 .driver_data = "20090506",
1232 },
1233 {
1234 .ident = "dv6",
1235 .matches = {
1236 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1237 DMI_MATCH(DMI_PRODUCT_NAME,
1238 "HP Pavilion dv6 Notebook PC"),
1239 },
1240 .driver_data = "20090423",
1241 },
1242 {
1243 .ident = "HDX18",
1244 .matches = {
1245 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1246 DMI_MATCH(DMI_PRODUCT_NAME,
1247 "HP HDX18 Notebook PC"),
1248 },
1249 .driver_data = "20090430",
1250 },
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260 {
1261 .ident = "G725",
1262 .matches = {
1263 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1264 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1265 },
1266 .driver_data = "20091216",
1267 },
1268 { }
1269 };
1270 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1271 int year, month, date;
1272 char buf[9];
1273
1274 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1275 return false;
1276
1277 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1278 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1279
1280 return strcmp(buf, dmi->driver_data) < 0;
1281}
1282
1283static bool ahci_broken_online(struct pci_dev *pdev)
1284{
1285#define ENCODE_BUSDEVFN(bus, slot, func) \
1286 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1287 static const struct dmi_system_id sysids[] = {
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301 {
1302 .ident = "EP45-DQ6",
1303 .matches = {
1304 DMI_MATCH(DMI_BOARD_VENDOR,
1305 "Gigabyte Technology Co., Ltd."),
1306 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1307 },
1308 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1309 },
1310 {
1311 .ident = "EP45-DS5",
1312 .matches = {
1313 DMI_MATCH(DMI_BOARD_VENDOR,
1314 "Gigabyte Technology Co., Ltd."),
1315 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1316 },
1317 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1318 },
1319 { }
1320 };
1321#undef ENCODE_BUSDEVFN
1322 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1323 unsigned int val;
1324
1325 if (!dmi)
1326 return false;
1327
1328 val = (unsigned long)dmi->driver_data;
1329
1330 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1331}
1332
1333static bool ahci_broken_devslp(struct pci_dev *pdev)
1334{
1335
1336 static const struct pci_device_id ids[] = {
1337 { PCI_VDEVICE(INTEL, 0x0f23)},
1338 {}
1339 };
1340
1341 return pci_match_id(ids, pdev);
1342}
1343
1344#ifdef CONFIG_ATA_ACPI
1345static void ahci_gtf_filter_workaround(struct ata_host *host)
1346{
1347 static const struct dmi_system_id sysids[] = {
1348
1349
1350
1351
1352
1353
1354
1355
1356 {
1357 .ident = "Aspire 3810T",
1358 .matches = {
1359 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1360 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1361 },
1362 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1363 },
1364 { }
1365 };
1366 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1367 unsigned int filter;
1368 int i;
1369
1370 if (!dmi)
1371 return;
1372
1373 filter = (unsigned long)dmi->driver_data;
1374 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1375 filter, dmi->ident);
1376
1377 for (i = 0; i < host->n_ports; i++) {
1378 struct ata_port *ap = host->ports[i];
1379 struct ata_link *link;
1380 struct ata_device *dev;
1381
1382 ata_for_each_link(link, ap, EDGE)
1383 ata_for_each_dev(dev, link, ALL)
1384 dev->gtf_filter |= filter;
1385 }
1386}
1387#else
1388static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1389{}
1390#endif
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1404 struct pci_dev *pdev)
1405{
1406 static const struct dmi_system_id sysids[] = {
1407 {
1408 .ident = "Acer Switch Alpha 12",
1409 .matches = {
1410 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1411 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1412 },
1413 },
1414 { }
1415 };
1416
1417 if (dmi_check_system(sysids)) {
1418 dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1419 if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1420 hpriv->port_map = 0x7;
1421 hpriv->cap = 0xC734FF02;
1422 }
1423 }
1424}
1425
1426#ifdef CONFIG_ARM64
1427
1428
1429
1430
1431
1432static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1433{
1434 struct ata_host *host = dev_instance;
1435 struct ahci_host_priv *hpriv;
1436 unsigned int rc = 0;
1437 void __iomem *mmio;
1438 u32 irq_stat, irq_masked;
1439 unsigned int handled = 1;
1440
1441 VPRINTK("ENTER\n");
1442 hpriv = host->private_data;
1443 mmio = hpriv->mmio;
1444 irq_stat = readl(mmio + HOST_IRQ_STAT);
1445 if (!irq_stat)
1446 return IRQ_NONE;
1447
1448 do {
1449 irq_masked = irq_stat & hpriv->port_map;
1450 spin_lock(&host->lock);
1451 rc = ahci_handle_port_intr(host, irq_masked);
1452 if (!rc)
1453 handled = 0;
1454 writel(irq_stat, mmio + HOST_IRQ_STAT);
1455 irq_stat = readl(mmio + HOST_IRQ_STAT);
1456 spin_unlock(&host->lock);
1457 } while (irq_stat);
1458 VPRINTK("EXIT\n");
1459
1460 return IRQ_RETVAL(handled);
1461}
1462#endif
1463
1464static void ahci_remap_check(struct pci_dev *pdev, int bar,
1465 struct ahci_host_priv *hpriv)
1466{
1467 int i, count = 0;
1468 u32 cap;
1469
1470
1471
1472
1473 if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1474 pci_resource_len(pdev, bar) < SZ_512K ||
1475 bar != AHCI_PCI_BAR_STANDARD ||
1476 !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1477 return;
1478
1479 cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1480 for (i = 0; i < AHCI_MAX_REMAP; i++) {
1481 if ((cap & (1 << i)) == 0)
1482 continue;
1483 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1484 != PCI_CLASS_STORAGE_EXPRESS)
1485 continue;
1486
1487
1488 count++;
1489 }
1490
1491 if (!count)
1492 return;
1493
1494 dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1495 dev_warn(&pdev->dev,
1496 "Switch your BIOS from RAID to AHCI mode to use them.\n");
1497
1498
1499
1500
1501
1502 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1503}
1504
1505static int ahci_get_irq_vector(struct ata_host *host, int port)
1506{
1507 return pci_irq_vector(to_pci_dev(host->dev), port);
1508}
1509
1510static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1511 struct ahci_host_priv *hpriv)
1512{
1513 int nvec;
1514
1515 if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1516 return -ENODEV;
1517
1518
1519
1520
1521
1522
1523 if (n_ports > 1) {
1524 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1525 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1526 if (nvec > 0) {
1527 if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1528 hpriv->get_irq_vector = ahci_get_irq_vector;
1529 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1530 return nvec;
1531 }
1532
1533
1534
1535
1536
1537 printk(KERN_INFO
1538 "ahci: MRSM is on, fallback to single MSI\n");
1539 pci_free_irq_vectors(pdev);
1540 }
1541 }
1542
1543
1544
1545
1546
1547 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1548 if (nvec == 1)
1549 return nvec;
1550 return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1551}
1552
1553static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1554{
1555 unsigned int board_id = ent->driver_data;
1556 struct ata_port_info pi = ahci_port_info[board_id];
1557 const struct ata_port_info *ppi[] = { &pi, NULL };
1558 struct device *dev = &pdev->dev;
1559 struct ahci_host_priv *hpriv;
1560 struct ata_host *host;
1561 int n_ports, i, rc;
1562 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1563
1564 VPRINTK("ENTER\n");
1565
1566 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1567
1568 ata_print_version_once(&pdev->dev, DRV_VERSION);
1569
1570
1571
1572
1573 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1574 return -ENODEV;
1575
1576
1577 if (is_mcp89_apple(pdev))
1578 ahci_mcp89_apple_enable(pdev);
1579
1580
1581
1582
1583
1584 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1585 dev_info(&pdev->dev,
1586 "PDC42819 can only drive SATA devices with this driver\n");
1587
1588
1589 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1590 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1591 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1592 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1593 else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1594 if (pdev->device == 0xa01c)
1595 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1596 if (pdev->device == 0xa084)
1597 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1598 }
1599
1600
1601 rc = pcim_enable_device(pdev);
1602 if (rc)
1603 return rc;
1604
1605 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1606 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1607 u8 map;
1608
1609
1610
1611
1612
1613 pci_read_config_byte(pdev, ICH_MAP, &map);
1614 if (map & 0x3) {
1615 dev_info(&pdev->dev,
1616 "controller is in combined mode, can't enable AHCI mode\n");
1617 return -ENODEV;
1618 }
1619 }
1620
1621
1622
1623
1624 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1625 if (rc == -EBUSY)
1626 pcim_pin_device(pdev);
1627 if (rc)
1628 return rc;
1629
1630 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1631 if (!hpriv)
1632 return -ENOMEM;
1633 hpriv->flags |= (unsigned long)pi.private_data;
1634
1635
1636 if (board_id == board_ahci_mcp65 &&
1637 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1638 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1639
1640
1641 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1642 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1643
1644
1645 if (ahci_sb600_enable_64bit(pdev))
1646 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1647
1648 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1649
1650
1651 ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1652
1653
1654 if (ahci_broken_devslp(pdev))
1655 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1656
1657#ifdef CONFIG_ARM64
1658 if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1659 hpriv->irq_handler = ahci_thunderx_irq_handler;
1660#endif
1661
1662
1663 ahci_pci_save_initial_config(pdev, hpriv);
1664
1665
1666 if (hpriv->cap & HOST_CAP_NCQ) {
1667 pi.flags |= ATA_FLAG_NCQ;
1668
1669
1670
1671
1672
1673
1674 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1675 pi.flags |= ATA_FLAG_FPDMA_AA;
1676
1677
1678
1679
1680
1681
1682
1683 pi.flags |= ATA_FLAG_FPDMA_AUX;
1684 }
1685
1686 if (hpriv->cap & HOST_CAP_PMP)
1687 pi.flags |= ATA_FLAG_PMP;
1688
1689 ahci_set_em_messages(hpriv, &pi);
1690
1691 if (ahci_broken_system_poweroff(pdev)) {
1692 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1693 dev_info(&pdev->dev,
1694 "quirky BIOS, skipping spindown on poweroff\n");
1695 }
1696
1697 if (ahci_broken_suspend(pdev)) {
1698 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1699 dev_warn(&pdev->dev,
1700 "BIOS update required for suspend/resume\n");
1701 }
1702
1703 if (ahci_broken_online(pdev)) {
1704 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1705 dev_info(&pdev->dev,
1706 "online status unreliable, applying workaround\n");
1707 }
1708
1709
1710
1711 acer_sa5_271_workaround(hpriv, pdev);
1712
1713
1714
1715
1716
1717
1718 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1719
1720 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1721 if (!host)
1722 return -ENOMEM;
1723 host->private_data = hpriv;
1724
1725 if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1726
1727 pci_intx(pdev, 1);
1728 }
1729 hpriv->irq = pci_irq_vector(pdev, 0);
1730
1731 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1732 host->flags |= ATA_HOST_PARALLEL_SCAN;
1733 else
1734 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1735
1736 if (pi.flags & ATA_FLAG_EM)
1737 ahci_reset_em(host);
1738
1739 for (i = 0; i < host->n_ports; i++) {
1740 struct ata_port *ap = host->ports[i];
1741
1742 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1743 ata_port_pbar_desc(ap, ahci_pci_bar,
1744 0x100 + ap->port_no * 0x80, "port");
1745
1746
1747 if (ap->flags & ATA_FLAG_EM)
1748 ap->em_message_type = hpriv->em_msg_type;
1749
1750 if ((hpriv->flags & AHCI_HFLAG_IS_MOBILE) &&
1751 mobile_lpm_policy >= ATA_LPM_UNKNOWN &&
1752 mobile_lpm_policy <= ATA_LPM_MIN_POWER)
1753 ap->target_lpm_policy = mobile_lpm_policy;
1754
1755
1756 if (!(hpriv->port_map & (1 << i)))
1757 ap->ops = &ata_dummy_port_ops;
1758 }
1759
1760
1761 ahci_p5wdh_workaround(host);
1762
1763
1764 ahci_gtf_filter_workaround(host);
1765
1766
1767 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1768 if (rc)
1769 return rc;
1770
1771 rc = ahci_pci_reset_controller(host);
1772 if (rc)
1773 return rc;
1774
1775 ahci_pci_init_controller(host);
1776 ahci_pci_print_info(host);
1777
1778 pci_set_master(pdev);
1779
1780 rc = ahci_host_activate(host, &ahci_sht);
1781 if (rc)
1782 return rc;
1783
1784 pm_runtime_put_noidle(&pdev->dev);
1785 return 0;
1786}
1787
1788static void ahci_remove_one(struct pci_dev *pdev)
1789{
1790 pm_runtime_get_noresume(&pdev->dev);
1791 ata_pci_remove_one(pdev);
1792}
1793
1794module_pci_driver(ahci_pci_driver);
1795
1796MODULE_AUTHOR("Jeff Garzik");
1797MODULE_DESCRIPTION("AHCI SATA low-level driver");
1798MODULE_LICENSE("GPL");
1799MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1800MODULE_VERSION(DRV_VERSION);
1801