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8#include <linux/clk-provider.h>
9#include <linux/clk.h>
10#include <linux/clkdev.h>
11#include <linux/init.h>
12#include <linux/mfd/da8xx-cfgchip.h>
13#include <linux/mfd/syscon.h>
14#include <linux/of_device.h>
15#include <linux/of.h>
16#include <linux/platform_data/clk-da8xx-cfgchip.h>
17#include <linux/platform_device.h>
18#include <linux/regmap.h>
19#include <linux/slab.h>
20
21
22
23#define DA8XX_GATE_CLOCK_IS_DIV4P5 BIT(1)
24
25struct da8xx_cfgchip_gate_clk_info {
26 const char *name;
27 u32 cfgchip;
28 u32 bit;
29 u32 flags;
30};
31
32struct da8xx_cfgchip_gate_clk {
33 struct clk_hw hw;
34 struct regmap *regmap;
35 u32 reg;
36 u32 mask;
37};
38
39#define to_da8xx_cfgchip_gate_clk(_hw) \
40 container_of((_hw), struct da8xx_cfgchip_gate_clk, hw)
41
42static int da8xx_cfgchip_gate_clk_enable(struct clk_hw *hw)
43{
44 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
45
46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask);
47}
48
49static void da8xx_cfgchip_gate_clk_disable(struct clk_hw *hw)
50{
51 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
52
53 regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0);
54}
55
56static int da8xx_cfgchip_gate_clk_is_enabled(struct clk_hw *hw)
57{
58 struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
59 unsigned int val;
60
61 regmap_read(clk->regmap, clk->reg, &val);
62
63 return !!(val & clk->mask);
64}
65
66static unsigned long da8xx_cfgchip_div4p5_recalc_rate(struct clk_hw *hw,
67 unsigned long parent_rate)
68{
69
70 return parent_rate * 2 / 9;
71}
72
73static const struct clk_ops da8xx_cfgchip_gate_clk_ops = {
74 .enable = da8xx_cfgchip_gate_clk_enable,
75 .disable = da8xx_cfgchip_gate_clk_disable,
76 .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
77};
78
79static const struct clk_ops da8xx_cfgchip_div4p5_clk_ops = {
80 .enable = da8xx_cfgchip_gate_clk_enable,
81 .disable = da8xx_cfgchip_gate_clk_disable,
82 .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
83 .recalc_rate = da8xx_cfgchip_div4p5_recalc_rate,
84};
85
86static struct da8xx_cfgchip_gate_clk * __init
87da8xx_cfgchip_gate_clk_register(struct device *dev,
88 const struct da8xx_cfgchip_gate_clk_info *info,
89 struct regmap *regmap)
90{
91 struct clk *parent;
92 const char *parent_name;
93 struct da8xx_cfgchip_gate_clk *gate;
94 struct clk_init_data init;
95 int ret;
96
97 parent = devm_clk_get(dev, NULL);
98 if (IS_ERR(parent))
99 return ERR_CAST(parent);
100
101 parent_name = __clk_get_name(parent);
102
103 gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
104 if (!gate)
105 return ERR_PTR(-ENOMEM);
106
107 init.name = info->name;
108 if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5)
109 init.ops = &da8xx_cfgchip_div4p5_clk_ops;
110 else
111 init.ops = &da8xx_cfgchip_gate_clk_ops;
112 init.parent_names = &parent_name;
113 init.num_parents = 1;
114 init.flags = 0;
115
116 gate->hw.init = &init;
117 gate->regmap = regmap;
118 gate->reg = info->cfgchip;
119 gate->mask = info->bit;
120
121 ret = devm_clk_hw_register(dev, &gate->hw);
122 if (ret < 0)
123 return ERR_PTR(ret);
124
125 return gate;
126}
127
128static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = {
129 .name = "ehrpwm_tbclk",
130 .cfgchip = CFGCHIP(1),
131 .bit = CFGCHIP1_TBCLKSYNC,
132};
133
134static int __init da8xx_cfgchip_register_tbclk(struct device *dev,
135 struct regmap *regmap)
136{
137 struct da8xx_cfgchip_gate_clk *gate;
138
139 gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info,
140 regmap);
141 if (IS_ERR(gate))
142 return PTR_ERR(gate);
143
144 clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0");
145 clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1");
146
147 return 0;
148}
149
150static const struct da8xx_cfgchip_gate_clk_info da8xx_div4p5ena_info __initconst = {
151 .name = "div4.5",
152 .cfgchip = CFGCHIP(3),
153 .bit = CFGCHIP3_DIV45PENA,
154 .flags = DA8XX_GATE_CLOCK_IS_DIV4P5,
155};
156
157static int __init da8xx_cfgchip_register_div4p5(struct device *dev,
158 struct regmap *regmap)
159{
160 struct da8xx_cfgchip_gate_clk *gate;
161
162 gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap);
163 if (IS_ERR(gate))
164 return PTR_ERR(gate);
165
166 return 0;
167}
168
169static int __init
170of_da8xx_cfgchip_gate_clk_init(struct device *dev,
171 const struct da8xx_cfgchip_gate_clk_info *info,
172 struct regmap *regmap)
173{
174 struct da8xx_cfgchip_gate_clk *gate;
175
176 gate = da8xx_cfgchip_gate_clk_register(dev, info, regmap);
177 if (IS_ERR(gate))
178 return PTR_ERR(gate);
179
180 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, gate);
181}
182
183static int __init of_da8xx_tbclksync_init(struct device *dev,
184 struct regmap *regmap)
185{
186 return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_tbclksync_info, regmap);
187}
188
189static int __init of_da8xx_div4p5ena_init(struct device *dev,
190 struct regmap *regmap)
191{
192 return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_div4p5ena_info, regmap);
193}
194
195
196
197struct da8xx_cfgchip_mux_clk_info {
198 const char *name;
199 const char *parent0;
200 const char *parent1;
201 u32 cfgchip;
202 u32 bit;
203};
204
205struct da8xx_cfgchip_mux_clk {
206 struct clk_hw hw;
207 struct regmap *regmap;
208 u32 reg;
209 u32 mask;
210};
211
212#define to_da8xx_cfgchip_mux_clk(_hw) \
213 container_of((_hw), struct da8xx_cfgchip_mux_clk, hw)
214
215static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index)
216{
217 struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
218 unsigned int val = index ? clk->mask : 0;
219
220 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val);
221}
222
223static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw)
224{
225 struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
226 unsigned int val;
227
228 regmap_read(clk->regmap, clk->reg, &val);
229
230 return (val & clk->mask) ? 1 : 0;
231}
232
233static const struct clk_ops da8xx_cfgchip_mux_clk_ops = {
234 .set_parent = da8xx_cfgchip_mux_clk_set_parent,
235 .get_parent = da8xx_cfgchip_mux_clk_get_parent,
236};
237
238static struct da8xx_cfgchip_mux_clk * __init
239da8xx_cfgchip_mux_clk_register(struct device *dev,
240 const struct da8xx_cfgchip_mux_clk_info *info,
241 struct regmap *regmap)
242{
243 const char * const parent_names[] = { info->parent0, info->parent1 };
244 struct da8xx_cfgchip_mux_clk *mux;
245 struct clk_init_data init;
246 int ret;
247
248 mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
249 if (!mux)
250 return ERR_PTR(-ENOMEM);
251
252 init.name = info->name;
253 init.ops = &da8xx_cfgchip_mux_clk_ops;
254 init.parent_names = parent_names;
255 init.num_parents = 2;
256 init.flags = 0;
257
258 mux->hw.init = &init;
259 mux->regmap = regmap;
260 mux->reg = info->cfgchip;
261 mux->mask = info->bit;
262
263 ret = devm_clk_hw_register(dev, &mux->hw);
264 if (ret < 0)
265 return ERR_PTR(ret);
266
267 return mux;
268}
269
270static const struct da8xx_cfgchip_mux_clk_info da850_async1_info __initconst = {
271 .name = "async1",
272 .parent0 = "pll0_sysclk3",
273 .parent1 = "div4.5",
274 .cfgchip = CFGCHIP(3),
275 .bit = CFGCHIP3_EMA_CLKSRC,
276};
277
278static int __init da8xx_cfgchip_register_async1(struct device *dev,
279 struct regmap *regmap)
280{
281 struct da8xx_cfgchip_mux_clk *mux;
282
283 mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap);
284 if (IS_ERR(mux))
285 return PTR_ERR(mux);
286
287 clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0");
288
289 return 0;
290}
291
292static const struct da8xx_cfgchip_mux_clk_info da850_async3_info __initconst = {
293 .name = "async3",
294 .parent0 = "pll0_sysclk2",
295 .parent1 = "pll1_sysclk2",
296 .cfgchip = CFGCHIP(3),
297 .bit = CFGCHIP3_ASYNC3_CLKSRC,
298};
299
300static int __init da850_cfgchip_register_async3(struct device *dev,
301 struct regmap *regmap)
302{
303 struct da8xx_cfgchip_mux_clk *mux;
304 struct clk_hw *parent;
305
306 mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap);
307 if (IS_ERR(mux))
308 return PTR_ERR(mux);
309
310 clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1");
311
312
313 parent = clk_hw_get_parent_by_index(&mux->hw, 1);
314 if (parent)
315 clk_set_parent(mux->hw.clk, parent->clk);
316 else
317 dev_warn(dev, "Failed to find async3 parent clock\n");
318
319 return 0;
320}
321
322static int __init
323of_da8xx_cfgchip_init_mux_clock(struct device *dev,
324 const struct da8xx_cfgchip_mux_clk_info *info,
325 struct regmap *regmap)
326{
327 struct da8xx_cfgchip_mux_clk *mux;
328
329 mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap);
330 if (IS_ERR(mux))
331 return PTR_ERR(mux);
332
333 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw);
334}
335
336static int __init of_da850_async1_init(struct device *dev, struct regmap *regmap)
337{
338 return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async1_info, regmap);
339}
340
341static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap)
342{
343 return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap);
344}
345
346
347
348struct da8xx_usb0_clk48 {
349 struct clk_hw hw;
350 struct clk *fck;
351 struct regmap *regmap;
352};
353
354#define to_da8xx_usb0_clk48(_hw) \
355 container_of((_hw), struct da8xx_usb0_clk48, hw)
356
357static int da8xx_usb0_clk48_prepare(struct clk_hw *hw)
358{
359 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
360
361
362
363
364
365 return clk_prepare(usb0->fck);
366}
367
368static void da8xx_usb0_clk48_unprepare(struct clk_hw *hw)
369{
370 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
371
372 clk_unprepare(usb0->fck);
373}
374
375static int da8xx_usb0_clk48_enable(struct clk_hw *hw)
376{
377 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
378 unsigned int mask, val;
379 int ret;
380
381
382
383
384 clk_enable(usb0->fck);
385
386
387
388
389 mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON;
390 val = CFGCHIP2_PHY_PLLON;
391
392 regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
393 ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val,
394 val & CFGCHIP2_PHYCLKGD, 0, 500000);
395
396 clk_disable(usb0->fck);
397
398 return ret;
399}
400
401static void da8xx_usb0_clk48_disable(struct clk_hw *hw)
402{
403 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
404 unsigned int val;
405
406 val = CFGCHIP2_PHYPWRDN;
407 regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val);
408}
409
410static int da8xx_usb0_clk48_is_enabled(struct clk_hw *hw)
411{
412 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
413 unsigned int val;
414
415 regmap_read(usb0->regmap, CFGCHIP(2), &val);
416
417 return !!(val & CFGCHIP2_PHYCLKGD);
418}
419
420static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw,
421 unsigned long parent_rate)
422{
423 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
424 unsigned int mask, val;
425
426
427 mask = CFGCHIP2_REFFREQ_MASK;
428 switch (parent_rate) {
429 case 12000000:
430 val = CFGCHIP2_REFFREQ_12MHZ;
431 break;
432 case 13000000:
433 val = CFGCHIP2_REFFREQ_13MHZ;
434 break;
435 case 19200000:
436 val = CFGCHIP2_REFFREQ_19_2MHZ;
437 break;
438 case 20000000:
439 val = CFGCHIP2_REFFREQ_20MHZ;
440 break;
441 case 24000000:
442 val = CFGCHIP2_REFFREQ_24MHZ;
443 break;
444 case 26000000:
445 val = CFGCHIP2_REFFREQ_26MHZ;
446 break;
447 case 38400000:
448 val = CFGCHIP2_REFFREQ_38_4MHZ;
449 break;
450 case 40000000:
451 val = CFGCHIP2_REFFREQ_40MHZ;
452 break;
453 case 48000000:
454 val = CFGCHIP2_REFFREQ_48MHZ;
455 break;
456 default:
457 return 0;
458 }
459
460 regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
461
462
463 return 48000000;
464}
465
466static long da8xx_usb0_clk48_round_rate(struct clk_hw *hw, unsigned long rate,
467 unsigned long *parent_rate)
468{
469 return 48000000;
470}
471
472static int da8xx_usb0_clk48_set_parent(struct clk_hw *hw, u8 index)
473{
474 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
475
476 return regmap_write_bits(usb0->regmap, CFGCHIP(2),
477 CFGCHIP2_USB2PHYCLKMUX,
478 index ? CFGCHIP2_USB2PHYCLKMUX : 0);
479}
480
481static u8 da8xx_usb0_clk48_get_parent(struct clk_hw *hw)
482{
483 struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
484 unsigned int val;
485
486 regmap_read(usb0->regmap, CFGCHIP(2), &val);
487
488 return (val & CFGCHIP2_USB2PHYCLKMUX) ? 1 : 0;
489}
490
491static const struct clk_ops da8xx_usb0_clk48_ops = {
492 .prepare = da8xx_usb0_clk48_prepare,
493 .unprepare = da8xx_usb0_clk48_unprepare,
494 .enable = da8xx_usb0_clk48_enable,
495 .disable = da8xx_usb0_clk48_disable,
496 .is_enabled = da8xx_usb0_clk48_is_enabled,
497 .recalc_rate = da8xx_usb0_clk48_recalc_rate,
498 .round_rate = da8xx_usb0_clk48_round_rate,
499 .set_parent = da8xx_usb0_clk48_set_parent,
500 .get_parent = da8xx_usb0_clk48_get_parent,
501};
502
503static struct da8xx_usb0_clk48 *
504da8xx_cfgchip_register_usb0_clk48(struct device *dev,
505 struct regmap *regmap)
506{
507 const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" };
508 struct clk *fck_clk;
509 struct da8xx_usb0_clk48 *usb0;
510 struct clk_init_data init;
511 int ret;
512
513 fck_clk = devm_clk_get(dev, "fck");
514 if (IS_ERR(fck_clk)) {
515 if (PTR_ERR(fck_clk) != -EPROBE_DEFER)
516 dev_err(dev, "Missing fck clock\n");
517 return ERR_CAST(fck_clk);
518 }
519
520 usb0 = devm_kzalloc(dev, sizeof(*usb0), GFP_KERNEL);
521 if (!usb0)
522 return ERR_PTR(-ENOMEM);
523
524 init.name = "usb0_clk48";
525 init.ops = &da8xx_usb0_clk48_ops;
526 init.parent_names = parent_names;
527 init.num_parents = 2;
528
529 usb0->hw.init = &init;
530 usb0->fck = fck_clk;
531 usb0->regmap = regmap;
532
533 ret = devm_clk_hw_register(dev, &usb0->hw);
534 if (ret < 0)
535 return ERR_PTR(ret);
536
537 return usb0;
538}
539
540
541
542struct da8xx_usb1_clk48 {
543 struct clk_hw hw;
544 struct regmap *regmap;
545};
546
547#define to_da8xx_usb1_clk48(_hw) \
548 container_of((_hw), struct da8xx_usb1_clk48, hw)
549
550static int da8xx_usb1_clk48_set_parent(struct clk_hw *hw, u8 index)
551{
552 struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
553
554 return regmap_write_bits(usb1->regmap, CFGCHIP(2),
555 CFGCHIP2_USB1PHYCLKMUX,
556 index ? CFGCHIP2_USB1PHYCLKMUX : 0);
557}
558
559static u8 da8xx_usb1_clk48_get_parent(struct clk_hw *hw)
560{
561 struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
562 unsigned int val;
563
564 regmap_read(usb1->regmap, CFGCHIP(2), &val);
565
566 return (val & CFGCHIP2_USB1PHYCLKMUX) ? 1 : 0;
567}
568
569static const struct clk_ops da8xx_usb1_clk48_ops = {
570 .set_parent = da8xx_usb1_clk48_set_parent,
571 .get_parent = da8xx_usb1_clk48_get_parent,
572};
573
574
575
576
577
578static struct da8xx_usb1_clk48 *
579da8xx_cfgchip_register_usb1_clk48(struct device *dev,
580 struct regmap *regmap)
581{
582 const char * const parent_names[] = { "usb0_clk48", "usb_refclkin" };
583 struct da8xx_usb1_clk48 *usb1;
584 struct clk_init_data init;
585 int ret;
586
587 usb1 = devm_kzalloc(dev, sizeof(*usb1), GFP_KERNEL);
588 if (!usb1)
589 return ERR_PTR(-ENOMEM);
590
591 init.name = "usb1_clk48";
592 init.ops = &da8xx_usb1_clk48_ops;
593 init.parent_names = parent_names;
594 init.num_parents = 2;
595
596 usb1->hw.init = &init;
597 usb1->regmap = regmap;
598
599 ret = devm_clk_hw_register(dev, &usb1->hw);
600 if (ret < 0)
601 return ERR_PTR(ret);
602
603 return usb1;
604}
605
606static int da8xx_cfgchip_register_usb_phy_clk(struct device *dev,
607 struct regmap *regmap)
608{
609 struct da8xx_usb0_clk48 *usb0;
610 struct da8xx_usb1_clk48 *usb1;
611 struct clk_hw *parent;
612
613 usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
614 if (IS_ERR(usb0))
615 return PTR_ERR(usb0);
616
617
618
619
620
621 parent = clk_hw_get_parent_by_index(&usb0->hw, 1);
622 if (parent)
623 clk_set_parent(usb0->hw.clk, parent->clk);
624 else
625 dev_warn(dev, "Failed to find usb0 parent clock\n");
626
627 usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
628 if (IS_ERR(usb1))
629 return PTR_ERR(usb1);
630
631
632
633
634
635 parent = clk_hw_get_parent_by_index(&usb1->hw, 0);
636 if (parent)
637 clk_set_parent(usb1->hw.clk, parent->clk);
638 else
639 dev_warn(dev, "Failed to find usb1 parent clock\n");
640
641 clk_hw_register_clkdev(&usb0->hw, "usb0_clk48", "da8xx-usb-phy");
642 clk_hw_register_clkdev(&usb1->hw, "usb1_clk48", "da8xx-usb-phy");
643
644 return 0;
645}
646
647static int of_da8xx_usb_phy_clk_init(struct device *dev, struct regmap *regmap)
648{
649 struct clk_hw_onecell_data *clk_data;
650 struct da8xx_usb0_clk48 *usb0;
651 struct da8xx_usb1_clk48 *usb1;
652
653 clk_data = devm_kzalloc(dev, sizeof(*clk_data) + 2 *
654 sizeof(*clk_data->hws), GFP_KERNEL);
655 if (!clk_data)
656 return -ENOMEM;
657
658 clk_data->num = 2;
659
660 usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
661 if (IS_ERR(usb0)) {
662 if (PTR_ERR(usb0) == -EPROBE_DEFER)
663 return -EPROBE_DEFER;
664
665 dev_warn(dev, "Failed to register usb0_clk48 (%ld)\n",
666 PTR_ERR(usb0));
667
668 clk_data->hws[0] = ERR_PTR(-ENOENT);
669 } else {
670 clk_data->hws[0] = &usb0->hw;
671 }
672
673 usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
674 if (IS_ERR(usb1)) {
675 if (PTR_ERR(usb0) == -EPROBE_DEFER)
676 return -EPROBE_DEFER;
677
678 dev_warn(dev, "Failed to register usb1_clk48 (%ld)\n",
679 PTR_ERR(usb1));
680
681 clk_data->hws[1] = ERR_PTR(-ENOENT);
682 } else {
683 clk_data->hws[1] = &usb1->hw;
684 }
685
686 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
687}
688
689
690
691static const struct of_device_id da8xx_cfgchip_of_match[] = {
692 {
693 .compatible = "ti,da830-tbclksync",
694 .data = of_da8xx_tbclksync_init,
695 },
696 {
697 .compatible = "ti,da830-div4p5ena",
698 .data = of_da8xx_div4p5ena_init,
699 },
700 {
701 .compatible = "ti,da850-async1-clksrc",
702 .data = of_da850_async1_init,
703 },
704 {
705 .compatible = "ti,da850-async3-clksrc",
706 .data = of_da850_async3_init,
707 },
708 {
709 .compatible = "ti,da830-usb-phy-clocks",
710 .data = of_da8xx_usb_phy_clk_init,
711 },
712 { }
713};
714
715static const struct platform_device_id da8xx_cfgchip_id_table[] = {
716 {
717 .name = "da830-tbclksync",
718 .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_tbclk,
719 },
720 {
721 .name = "da830-div4p5ena",
722 .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_div4p5,
723 },
724 {
725 .name = "da850-async1-clksrc",
726 .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_async1,
727 },
728 {
729 .name = "da850-async3-clksrc",
730 .driver_data = (kernel_ulong_t)da850_cfgchip_register_async3,
731 },
732 {
733 .name = "da830-usb-phy-clks",
734 .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_usb_phy_clk,
735 },
736 { }
737};
738
739typedef int (*da8xx_cfgchip_init)(struct device *dev, struct regmap *regmap);
740
741static int da8xx_cfgchip_probe(struct platform_device *pdev)
742{
743 struct device *dev = &pdev->dev;
744 struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data;
745 const struct of_device_id *of_id;
746 da8xx_cfgchip_init clk_init = NULL;
747 struct regmap *regmap = NULL;
748
749 of_id = of_match_device(da8xx_cfgchip_of_match, dev);
750 if (of_id) {
751 struct device_node *parent;
752
753 clk_init = of_id->data;
754 parent = of_get_parent(dev->of_node);
755 regmap = syscon_node_to_regmap(parent);
756 of_node_put(parent);
757 } else if (pdev->id_entry && pdata) {
758 clk_init = (void *)pdev->id_entry->driver_data;
759 regmap = pdata->cfgchip;
760 }
761
762 if (!clk_init) {
763 dev_err(dev, "unable to find driver data\n");
764 return -EINVAL;
765 }
766
767 if (IS_ERR_OR_NULL(regmap)) {
768 dev_err(dev, "no regmap for CFGCHIP syscon\n");
769 return regmap ? PTR_ERR(regmap) : -ENOENT;
770 }
771
772 return clk_init(dev, regmap);
773}
774
775static struct platform_driver da8xx_cfgchip_driver = {
776 .probe = da8xx_cfgchip_probe,
777 .driver = {
778 .name = "da8xx-cfgchip-clk",
779 .of_match_table = da8xx_cfgchip_of_match,
780 },
781 .id_table = da8xx_cfgchip_id_table,
782};
783
784static int __init da8xx_cfgchip_driver_init(void)
785{
786 return platform_driver_register(&da8xx_cfgchip_driver);
787}
788
789
790postcore_initcall(da8xx_cfgchip_driver_init);
791
