1
2
3
4
5
6
7
8
9
10
11
12
13
14
15#include <linux/clk-provider.h>
16#include <linux/err.h>
17#include <linux/export.h>
18#include <linux/init.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/mutex.h>
22#include <linux/mfd/qcom_rpm.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/platform_device.h>
26
27#include <dt-bindings/mfd/qcom-rpm.h>
28#include <dt-bindings/clock/qcom,rpmcc.h>
29
30#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
31#define QCOM_RPM_SCALING_ENABLE_ID 0x2
32#define QCOM_RPM_XO_MODE_ON 0x2
33
34#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
35 static struct clk_rpm _platform##_##_active; \
36 static struct clk_rpm _platform##_##_name = { \
37 .rpm_clk_id = (r_id), \
38 .peer = &_platform##_##_active, \
39 .rate = INT_MAX, \
40 .hw.init = &(struct clk_init_data){ \
41 .ops = &clk_rpm_ops, \
42 .name = #_name, \
43 .parent_names = (const char *[]){ "pxo_board" }, \
44 .num_parents = 1, \
45 }, \
46 }; \
47 static struct clk_rpm _platform##_##_active = { \
48 .rpm_clk_id = (r_id), \
49 .peer = &_platform##_##_name, \
50 .active_only = true, \
51 .rate = INT_MAX, \
52 .hw.init = &(struct clk_init_data){ \
53 .ops = &clk_rpm_ops, \
54 .name = #_active, \
55 .parent_names = (const char *[]){ "pxo_board" }, \
56 .num_parents = 1, \
57 }, \
58 }
59
60#define DEFINE_CLK_RPM_XO_BUFFER(_platform, _name, _active, offset) \
61 static struct clk_rpm _platform##_##_name = { \
62 .rpm_clk_id = QCOM_RPM_CXO_BUFFERS, \
63 .xo_offset = (offset), \
64 .hw.init = &(struct clk_init_data){ \
65 .ops = &clk_rpm_xo_ops, \
66 .name = #_name, \
67 .parent_names = (const char *[]){ "cxo_board" }, \
68 .num_parents = 1, \
69 }, \
70 }
71
72#define DEFINE_CLK_RPM_FIXED(_platform, _name, _active, r_id, r) \
73 static struct clk_rpm _platform##_##_name = { \
74 .rpm_clk_id = (r_id), \
75 .rate = (r), \
76 .hw.init = &(struct clk_init_data){ \
77 .ops = &clk_rpm_fixed_ops, \
78 .name = #_name, \
79 .parent_names = (const char *[]){ "pxo" }, \
80 .num_parents = 1, \
81 }, \
82 }
83
84#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
85 static struct clk_rpm _platform##_##_active; \
86 static struct clk_rpm _platform##_##_name = { \
87 .rpm_clk_id = (r_id), \
88 .active_only = true, \
89 .peer = &_platform##_##_active, \
90 .rate = (r), \
91 .branch = true, \
92 .hw.init = &(struct clk_init_data){ \
93 .ops = &clk_rpm_branch_ops, \
94 .name = #_name, \
95 .parent_names = (const char *[]){ "pxo_board" }, \
96 .num_parents = 1, \
97 }, \
98 }; \
99 static struct clk_rpm _platform##_##_active = { \
100 .rpm_clk_id = (r_id), \
101 .peer = &_platform##_##_name, \
102 .rate = (r), \
103 .branch = true, \
104 .hw.init = &(struct clk_init_data){ \
105 .ops = &clk_rpm_branch_ops, \
106 .name = #_active, \
107 .parent_names = (const char *[]){ "pxo_board" }, \
108 .num_parents = 1, \
109 }, \
110 }
111
112#define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \
113 static struct clk_rpm _platform##_##_active; \
114 static struct clk_rpm _platform##_##_name = { \
115 .rpm_clk_id = (r_id), \
116 .peer = &_platform##_##_active, \
117 .rate = (r), \
118 .branch = true, \
119 .hw.init = &(struct clk_init_data){ \
120 .ops = &clk_rpm_branch_ops, \
121 .name = #_name, \
122 .parent_names = (const char *[]){ "cxo_board" }, \
123 .num_parents = 1, \
124 }, \
125 }; \
126 static struct clk_rpm _platform##_##_active = { \
127 .rpm_clk_id = (r_id), \
128 .active_only = true, \
129 .peer = &_platform##_##_name, \
130 .rate = (r), \
131 .branch = true, \
132 .hw.init = &(struct clk_init_data){ \
133 .ops = &clk_rpm_branch_ops, \
134 .name = #_active, \
135 .parent_names = (const char *[]){ "cxo_board" }, \
136 .num_parents = 1, \
137 }, \
138 }
139
140#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
141
142struct rpm_cc;
143
144struct clk_rpm {
145 const int rpm_clk_id;
146 const int xo_offset;
147 const bool active_only;
148 unsigned long rate;
149 bool enabled;
150 bool branch;
151 struct clk_rpm *peer;
152 struct clk_hw hw;
153 struct qcom_rpm *rpm;
154 struct rpm_cc *rpm_cc;
155};
156
157struct rpm_cc {
158 struct qcom_rpm *rpm;
159 struct clk_rpm **clks;
160 size_t num_clks;
161 u32 xo_buffer_value;
162 struct mutex xo_lock;
163};
164
165struct rpm_clk_desc {
166 struct clk_rpm **clks;
167 size_t num_clks;
168};
169
170static DEFINE_MUTEX(rpm_clk_lock);
171
172static int clk_rpm_handoff(struct clk_rpm *r)
173{
174 int ret;
175 u32 value = INT_MAX;
176
177
178
179
180
181 if (r->rpm_clk_id == QCOM_RPM_PLL_4 ||
182 r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)
183 return 0;
184
185 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
186 r->rpm_clk_id, &value, 1);
187 if (ret)
188 return ret;
189 ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
190 r->rpm_clk_id, &value, 1);
191 if (ret)
192 return ret;
193
194 return 0;
195}
196
197static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
198{
199 u32 value = DIV_ROUND_UP(rate, 1000);
200
201 return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
202 r->rpm_clk_id, &value, 1);
203}
204
205static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
206{
207 u32 value = DIV_ROUND_UP(rate, 1000);
208
209 return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
210 r->rpm_clk_id, &value, 1);
211}
212
213static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
214 unsigned long *active, unsigned long *sleep)
215{
216 *active = rate;
217
218
219
220
221
222 if (r->active_only)
223 *sleep = 0;
224 else
225 *sleep = *active;
226}
227
228static int clk_rpm_prepare(struct clk_hw *hw)
229{
230 struct clk_rpm *r = to_clk_rpm(hw);
231 struct clk_rpm *peer = r->peer;
232 unsigned long this_rate = 0, this_sleep_rate = 0;
233 unsigned long peer_rate = 0, peer_sleep_rate = 0;
234 unsigned long active_rate, sleep_rate;
235 int ret = 0;
236
237 mutex_lock(&rpm_clk_lock);
238
239
240 if (!r->rate)
241 goto out;
242
243 to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
244
245
246 if (peer->enabled)
247 to_active_sleep(peer, peer->rate,
248 &peer_rate, &peer_sleep_rate);
249
250 active_rate = max(this_rate, peer_rate);
251
252 if (r->branch)
253 active_rate = !!active_rate;
254
255 ret = clk_rpm_set_rate_active(r, active_rate);
256 if (ret)
257 goto out;
258
259 sleep_rate = max(this_sleep_rate, peer_sleep_rate);
260 if (r->branch)
261 sleep_rate = !!sleep_rate;
262
263 ret = clk_rpm_set_rate_sleep(r, sleep_rate);
264 if (ret)
265
266 ret = clk_rpm_set_rate_active(r, peer_rate);
267
268out:
269 if (!ret)
270 r->enabled = true;
271
272 mutex_unlock(&rpm_clk_lock);
273
274 return ret;
275}
276
277static void clk_rpm_unprepare(struct clk_hw *hw)
278{
279 struct clk_rpm *r = to_clk_rpm(hw);
280 struct clk_rpm *peer = r->peer;
281 unsigned long peer_rate = 0, peer_sleep_rate = 0;
282 unsigned long active_rate, sleep_rate;
283 int ret;
284
285 mutex_lock(&rpm_clk_lock);
286
287 if (!r->rate)
288 goto out;
289
290
291 if (peer->enabled)
292 to_active_sleep(peer, peer->rate, &peer_rate,
293 &peer_sleep_rate);
294
295 active_rate = r->branch ? !!peer_rate : peer_rate;
296 ret = clk_rpm_set_rate_active(r, active_rate);
297 if (ret)
298 goto out;
299
300 sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
301 ret = clk_rpm_set_rate_sleep(r, sleep_rate);
302 if (ret)
303 goto out;
304
305 r->enabled = false;
306
307out:
308 mutex_unlock(&rpm_clk_lock);
309}
310
311static int clk_rpm_xo_prepare(struct clk_hw *hw)
312{
313 struct clk_rpm *r = to_clk_rpm(hw);
314 struct rpm_cc *rcc = r->rpm_cc;
315 int ret, clk_id = r->rpm_clk_id;
316 u32 value;
317
318 mutex_lock(&rcc->xo_lock);
319
320 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset);
321 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
322 if (!ret) {
323 r->enabled = true;
324 rcc->xo_buffer_value = value;
325 }
326
327 mutex_unlock(&rcc->xo_lock);
328
329 return ret;
330}
331
332static void clk_rpm_xo_unprepare(struct clk_hw *hw)
333{
334 struct clk_rpm *r = to_clk_rpm(hw);
335 struct rpm_cc *rcc = r->rpm_cc;
336 int ret, clk_id = r->rpm_clk_id;
337 u32 value;
338
339 mutex_lock(&rcc->xo_lock);
340
341 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);
342 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
343 if (!ret) {
344 r->enabled = false;
345 rcc->xo_buffer_value = value;
346 }
347
348 mutex_unlock(&rcc->xo_lock);
349}
350
351static int clk_rpm_fixed_prepare(struct clk_hw *hw)
352{
353 struct clk_rpm *r = to_clk_rpm(hw);
354 u32 value = 1;
355 int ret;
356
357 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
358 r->rpm_clk_id, &value, 1);
359 if (!ret)
360 r->enabled = true;
361
362 return ret;
363}
364
365static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
366{
367 struct clk_rpm *r = to_clk_rpm(hw);
368 u32 value = 0;
369 int ret;
370
371 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
372 r->rpm_clk_id, &value, 1);
373 if (!ret)
374 r->enabled = false;
375}
376
377static int clk_rpm_set_rate(struct clk_hw *hw,
378 unsigned long rate, unsigned long parent_rate)
379{
380 struct clk_rpm *r = to_clk_rpm(hw);
381 struct clk_rpm *peer = r->peer;
382 unsigned long active_rate, sleep_rate;
383 unsigned long this_rate = 0, this_sleep_rate = 0;
384 unsigned long peer_rate = 0, peer_sleep_rate = 0;
385 int ret = 0;
386
387 mutex_lock(&rpm_clk_lock);
388
389 if (!r->enabled)
390 goto out;
391
392 to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
393
394
395 if (peer->enabled)
396 to_active_sleep(peer, peer->rate,
397 &peer_rate, &peer_sleep_rate);
398
399 active_rate = max(this_rate, peer_rate);
400 ret = clk_rpm_set_rate_active(r, active_rate);
401 if (ret)
402 goto out;
403
404 sleep_rate = max(this_sleep_rate, peer_sleep_rate);
405 ret = clk_rpm_set_rate_sleep(r, sleep_rate);
406 if (ret)
407 goto out;
408
409 r->rate = rate;
410
411out:
412 mutex_unlock(&rpm_clk_lock);
413
414 return ret;
415}
416
417static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
418 unsigned long *parent_rate)
419{
420
421
422
423
424
425 return rate;
426}
427
428static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
429 unsigned long parent_rate)
430{
431 struct clk_rpm *r = to_clk_rpm(hw);
432
433
434
435
436
437
438 return r->rate;
439}
440
441static const struct clk_ops clk_rpm_xo_ops = {
442 .prepare = clk_rpm_xo_prepare,
443 .unprepare = clk_rpm_xo_unprepare,
444};
445
446static const struct clk_ops clk_rpm_fixed_ops = {
447 .prepare = clk_rpm_fixed_prepare,
448 .unprepare = clk_rpm_fixed_unprepare,
449 .round_rate = clk_rpm_round_rate,
450 .recalc_rate = clk_rpm_recalc_rate,
451};
452
453static const struct clk_ops clk_rpm_ops = {
454 .prepare = clk_rpm_prepare,
455 .unprepare = clk_rpm_unprepare,
456 .set_rate = clk_rpm_set_rate,
457 .round_rate = clk_rpm_round_rate,
458 .recalc_rate = clk_rpm_recalc_rate,
459};
460
461static const struct clk_ops clk_rpm_branch_ops = {
462 .prepare = clk_rpm_prepare,
463 .unprepare = clk_rpm_unprepare,
464 .round_rate = clk_rpm_round_rate,
465 .recalc_rate = clk_rpm_recalc_rate,
466};
467
468
469DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
470DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
471DEFINE_CLK_RPM(msm8660, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
472DEFINE_CLK_RPM(msm8660, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
473DEFINE_CLK_RPM(msm8660, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
474DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
475DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
476DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK);
477DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
478DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000);
479
480static struct clk_rpm *msm8660_clks[] = {
481 [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk,
482 [RPM_APPS_FABRIC_A_CLK] = &msm8660_afab_a_clk,
483 [RPM_SYS_FABRIC_CLK] = &msm8660_sfab_clk,
484 [RPM_SYS_FABRIC_A_CLK] = &msm8660_sfab_a_clk,
485 [RPM_MM_FABRIC_CLK] = &msm8660_mmfab_clk,
486 [RPM_MM_FABRIC_A_CLK] = &msm8660_mmfab_a_clk,
487 [RPM_DAYTONA_FABRIC_CLK] = &msm8660_daytona_clk,
488 [RPM_DAYTONA_FABRIC_A_CLK] = &msm8660_daytona_a_clk,
489 [RPM_SFPB_CLK] = &msm8660_sfpb_clk,
490 [RPM_SFPB_A_CLK] = &msm8660_sfpb_a_clk,
491 [RPM_CFPB_CLK] = &msm8660_cfpb_clk,
492 [RPM_CFPB_A_CLK] = &msm8660_cfpb_a_clk,
493 [RPM_MMFPB_CLK] = &msm8660_mmfpb_clk,
494 [RPM_MMFPB_A_CLK] = &msm8660_mmfpb_a_clk,
495 [RPM_SMI_CLK] = &msm8660_smi_clk,
496 [RPM_SMI_A_CLK] = &msm8660_smi_a_clk,
497 [RPM_EBI1_CLK] = &msm8660_ebi1_clk,
498 [RPM_EBI1_A_CLK] = &msm8660_ebi1_a_clk,
499 [RPM_PLL4_CLK] = &msm8660_pll4_clk,
500};
501
502static const struct rpm_clk_desc rpm_clk_msm8660 = {
503 .clks = msm8660_clks,
504 .num_clks = ARRAY_SIZE(msm8660_clks),
505};
506
507
508DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
509DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
510DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
511DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
512DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
513DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
514DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
515DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
516DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
517DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d0_clk, xo_d0_a_clk, 0);
518DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_d1_clk, xo_d1_a_clk, 8);
519DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a0_clk, xo_a0_a_clk, 16);
520DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a1_clk, xo_a1_a_clk, 24);
521DEFINE_CLK_RPM_XO_BUFFER(apq8064, xo_a2_clk, xo_a2_a_clk, 28);
522
523static struct clk_rpm *apq8064_clks[] = {
524 [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
525 [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
526 [RPM_CFPB_CLK] = &apq8064_cfpb_clk,
527 [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk,
528 [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk,
529 [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk,
530 [RPM_EBI1_CLK] = &apq8064_ebi1_clk,
531 [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk,
532 [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk,
533 [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk,
534 [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk,
535 [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk,
536 [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk,
537 [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk,
538 [RPM_SFPB_CLK] = &apq8064_sfpb_clk,
539 [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk,
540 [RPM_QDSS_CLK] = &apq8064_qdss_clk,
541 [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
542 [RPM_XO_D0] = &apq8064_xo_d0_clk,
543 [RPM_XO_D1] = &apq8064_xo_d1_clk,
544 [RPM_XO_A0] = &apq8064_xo_a0_clk,
545 [RPM_XO_A1] = &apq8064_xo_a1_clk,
546 [RPM_XO_A2] = &apq8064_xo_a2_clk,
547};
548
549static const struct rpm_clk_desc rpm_clk_apq8064 = {
550 .clks = apq8064_clks,
551 .num_clks = ARRAY_SIZE(apq8064_clks),
552};
553
554static const struct of_device_id rpm_clk_match_table[] = {
555 { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
556 { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
557 { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
558 { }
559};
560MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
561
562static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,
563 void *data)
564{
565 struct rpm_cc *rcc = data;
566 unsigned int idx = clkspec->args[0];
567
568 if (idx >= rcc->num_clks) {
569 pr_err("%s: invalid index %u\n", __func__, idx);
570 return ERR_PTR(-EINVAL);
571 }
572
573 return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
574}
575
576static int rpm_clk_probe(struct platform_device *pdev)
577{
578 struct rpm_cc *rcc;
579 int ret;
580 size_t num_clks, i;
581 struct qcom_rpm *rpm;
582 struct clk_rpm **rpm_clks;
583 const struct rpm_clk_desc *desc;
584
585 rpm = dev_get_drvdata(pdev->dev.parent);
586 if (!rpm) {
587 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
588 return -ENODEV;
589 }
590
591 desc = of_device_get_match_data(&pdev->dev);
592 if (!desc)
593 return -EINVAL;
594
595 rpm_clks = desc->clks;
596 num_clks = desc->num_clks;
597
598 rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
599 if (!rcc)
600 return -ENOMEM;
601
602 rcc->clks = rpm_clks;
603 rcc->num_clks = num_clks;
604 mutex_init(&rcc->xo_lock);
605
606 for (i = 0; i < num_clks; i++) {
607 if (!rpm_clks[i])
608 continue;
609
610 rpm_clks[i]->rpm = rpm;
611 rpm_clks[i]->rpm_cc = rcc;
612
613 ret = clk_rpm_handoff(rpm_clks[i]);
614 if (ret)
615 goto err;
616 }
617
618 for (i = 0; i < num_clks; i++) {
619 if (!rpm_clks[i])
620 continue;
621
622 ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
623 if (ret)
624 goto err;
625 }
626
627 ret = of_clk_add_hw_provider(pdev->dev.of_node, qcom_rpm_clk_hw_get,
628 rcc);
629 if (ret)
630 goto err;
631
632 return 0;
633err:
634 dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
635 return ret;
636}
637
638static int rpm_clk_remove(struct platform_device *pdev)
639{
640 of_clk_del_provider(pdev->dev.of_node);
641 return 0;
642}
643
644static struct platform_driver rpm_clk_driver = {
645 .driver = {
646 .name = "qcom-clk-rpm",
647 .of_match_table = rpm_clk_match_table,
648 },
649 .probe = rpm_clk_probe,
650 .remove = rpm_clk_remove,
651};
652
653static int __init rpm_clk_init(void)
654{
655 return platform_driver_register(&rpm_clk_driver);
656}
657core_initcall(rpm_clk_init);
658
659static void __exit rpm_clk_exit(void)
660{
661 platform_driver_unregister(&rpm_clk_driver);
662}
663module_exit(rpm_clk_exit);
664
665MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
666MODULE_LICENSE("GPL v2");
667MODULE_ALIAS("platform:qcom-clk-rpm");
668
