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11#include <linux/clkdev.h>
12#include <linux/slab.h>
13#include <linux/clk.h>
14#include <linux/clk-provider.h>
15#include <linux/platform_device.h>
16#include <linux/module.h>
17#include "clk.h"
18
19
20#include <mach/hardware.h>
21#include <mach/regs-gpio.h>
22
23#define MUX_DCLK0 0
24#define MUX_DCLK1 1
25#define DIV_DCLK0 2
26#define DIV_DCLK1 3
27#define GATE_DCLK0 4
28#define GATE_DCLK1 5
29#define MUX_CLKOUT0 6
30#define MUX_CLKOUT1 7
31#define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1)
32
33enum supported_socs {
34 S3C2410,
35 S3C2412,
36 S3C2440,
37 S3C2443,
38};
39
40struct s3c24xx_dclk_drv_data {
41 const char **clkout0_parent_names;
42 int clkout0_num_parents;
43 const char **clkout1_parent_names;
44 int clkout1_num_parents;
45 const char **mux_parent_names;
46 int mux_num_parents;
47};
48
49
50
51
52
53struct s3c24xx_clkout {
54 struct clk_hw hw;
55 u32 mask;
56 u8 shift;
57};
58
59#define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
60
61static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
62{
63 struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
64 int num_parents = clk_hw_get_num_parents(hw);
65 u32 val;
66
67 val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift;
68 val >>= clkout->shift;
69 val &= clkout->mask;
70
71 if (val >= num_parents)
72 return -EINVAL;
73
74 return val;
75}
76
77static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
78{
79 struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
80
81 s3c2410_modify_misccr((clkout->mask << clkout->shift),
82 (index << clkout->shift));
83
84 return 0;
85}
86
87static const struct clk_ops s3c24xx_clkout_ops = {
88 .get_parent = s3c24xx_clkout_get_parent,
89 .set_parent = s3c24xx_clkout_set_parent,
90 .determine_rate = __clk_mux_determine_rate,
91};
92
93static struct clk_hw *s3c24xx_register_clkout(struct device *dev,
94 const char *name, const char **parent_names, u8 num_parents,
95 u8 shift, u32 mask)
96{
97 struct s3c24xx_clkout *clkout;
98 struct clk_init_data init;
99 int ret;
100
101
102 clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
103 if (!clkout)
104 return ERR_PTR(-ENOMEM);
105
106 init.name = name;
107 init.ops = &s3c24xx_clkout_ops;
108 init.flags = CLK_IS_BASIC;
109 init.parent_names = parent_names;
110 init.num_parents = num_parents;
111
112 clkout->shift = shift;
113 clkout->mask = mask;
114 clkout->hw.init = &init;
115
116 ret = clk_hw_register(dev, &clkout->hw);
117 if (ret)
118 return ERR_PTR(ret);
119
120 return &clkout->hw;
121}
122
123
124
125
126
127struct s3c24xx_dclk {
128 struct device *dev;
129 void __iomem *base;
130 struct notifier_block dclk0_div_change_nb;
131 struct notifier_block dclk1_div_change_nb;
132 spinlock_t dclk_lock;
133 unsigned long reg_save;
134
135 struct clk_hw_onecell_data clk_data;
136};
137
138#define to_s3c24xx_dclk0(x) \
139 container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
140
141#define to_s3c24xx_dclk1(x) \
142 container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
143
144static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
145static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
146 "gate_dclk0" };
147static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
148 "gate_dclk1" };
149
150static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
151 "hclk", "pclk", "gate_dclk0" };
152static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
153 "gate_dclk1" };
154
155static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
156 "gate_dclk0" };
157static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
158 "hclk", "pclk", "gate_dclk1" };
159
160static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
161static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
162 "gate_dclk0" };
163static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
164 "hclk", "pclk", "gate_dclk1" };
165
166#define DCLKCON_DCLK_DIV_MASK 0xf
167#define DCLKCON_DCLK0_DIV_SHIFT 4
168#define DCLKCON_DCLK0_CMP_SHIFT 8
169#define DCLKCON_DCLK1_DIV_SHIFT 20
170#define DCLKCON_DCLK1_CMP_SHIFT 24
171
172static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
173 int div_shift, int cmp_shift)
174{
175 unsigned long flags = 0;
176 u32 dclk_con, div, cmp;
177
178 spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
179
180 dclk_con = readl_relaxed(s3c24xx_dclk->base);
181
182 div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
183 cmp = ((div + 1) / 2) - 1;
184
185 dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
186 dclk_con |= (cmp << cmp_shift);
187
188 writel_relaxed(dclk_con, s3c24xx_dclk->base);
189
190 spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
191}
192
193static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
194 unsigned long event, void *data)
195{
196 struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
197
198 if (event == POST_RATE_CHANGE) {
199 s3c24xx_dclk_update_cmp(s3c24xx_dclk,
200 DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
201 }
202
203 return NOTIFY_DONE;
204}
205
206static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
207 unsigned long event, void *data)
208{
209 struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
210
211 if (event == POST_RATE_CHANGE) {
212 s3c24xx_dclk_update_cmp(s3c24xx_dclk,
213 DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
214 }
215
216 return NOTIFY_DONE;
217}
218
219#ifdef CONFIG_PM_SLEEP
220static int s3c24xx_dclk_suspend(struct device *dev)
221{
222 struct platform_device *pdev = to_platform_device(dev);
223 struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
224
225 s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
226 return 0;
227}
228
229static int s3c24xx_dclk_resume(struct device *dev)
230{
231 struct platform_device *pdev = to_platform_device(dev);
232 struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
233
234 writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
235 return 0;
236}
237#endif
238
239static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
240 s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
241
242static int s3c24xx_dclk_probe(struct platform_device *pdev)
243{
244 struct s3c24xx_dclk *s3c24xx_dclk;
245 struct resource *mem;
246 struct s3c24xx_dclk_drv_data *dclk_variant;
247 struct clk_hw **clk_table;
248 int ret, i;
249
250 s3c24xx_dclk = devm_kzalloc(&pdev->dev, sizeof(*s3c24xx_dclk) +
251 sizeof(*s3c24xx_dclk->clk_data.hws) * DCLK_MAX_CLKS,
252 GFP_KERNEL);
253 if (!s3c24xx_dclk)
254 return -ENOMEM;
255
256 clk_table = s3c24xx_dclk->clk_data.hws;
257
258 s3c24xx_dclk->dev = &pdev->dev;
259 s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS;
260 platform_set_drvdata(pdev, s3c24xx_dclk);
261 spin_lock_init(&s3c24xx_dclk->dclk_lock);
262
263 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
264 s3c24xx_dclk->base = devm_ioremap_resource(&pdev->dev, mem);
265 if (IS_ERR(s3c24xx_dclk->base))
266 return PTR_ERR(s3c24xx_dclk->base);
267
268 dclk_variant = (struct s3c24xx_dclk_drv_data *)
269 platform_get_device_id(pdev)->driver_data;
270
271
272 clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0",
273 dclk_variant->mux_parent_names,
274 dclk_variant->mux_num_parents, 0,
275 s3c24xx_dclk->base, 1, 1, 0,
276 &s3c24xx_dclk->dclk_lock);
277 clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1",
278 dclk_variant->mux_parent_names,
279 dclk_variant->mux_num_parents, 0,
280 s3c24xx_dclk->base, 17, 1, 0,
281 &s3c24xx_dclk->dclk_lock);
282
283 clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0",
284 "mux_dclk0", 0, s3c24xx_dclk->base,
285 4, 4, 0, &s3c24xx_dclk->dclk_lock);
286 clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1",
287 "mux_dclk1", 0, s3c24xx_dclk->base,
288 20, 4, 0, &s3c24xx_dclk->dclk_lock);
289
290 clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0",
291 "div_dclk0", CLK_SET_RATE_PARENT,
292 s3c24xx_dclk->base, 0, 0,
293 &s3c24xx_dclk->dclk_lock);
294 clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1",
295 "div_dclk1", CLK_SET_RATE_PARENT,
296 s3c24xx_dclk->base, 16, 0,
297 &s3c24xx_dclk->dclk_lock);
298
299 clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
300 "clkout0", dclk_variant->clkout0_parent_names,
301 dclk_variant->clkout0_num_parents, 4, 7);
302 clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
303 "clkout1", dclk_variant->clkout1_parent_names,
304 dclk_variant->clkout1_num_parents, 8, 7);
305
306 for (i = 0; i < DCLK_MAX_CLKS; i++)
307 if (IS_ERR(clk_table[i])) {
308 dev_err(&pdev->dev, "clock %d failed to register\n", i);
309 ret = PTR_ERR(clk_table[i]);
310 goto err_clk_register;
311 }
312
313 ret = clk_hw_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
314 if (!ret)
315 ret = clk_hw_register_clkdev(clk_table[MUX_DCLK1], "dclk1",
316 NULL);
317 if (!ret)
318 ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0],
319 "clkout0", NULL);
320 if (!ret)
321 ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT1],
322 "clkout1", NULL);
323 if (ret) {
324 dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
325 goto err_clk_register;
326 }
327
328 s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
329 s3c24xx_dclk0_div_notify;
330
331 s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
332 s3c24xx_dclk1_div_notify;
333
334 ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk,
335 &s3c24xx_dclk->dclk0_div_change_nb);
336 if (ret)
337 goto err_clk_register;
338
339 ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk,
340 &s3c24xx_dclk->dclk1_div_change_nb);
341 if (ret)
342 goto err_dclk_notify;
343
344 return 0;
345
346err_dclk_notify:
347 clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
348 &s3c24xx_dclk->dclk0_div_change_nb);
349err_clk_register:
350 for (i = 0; i < DCLK_MAX_CLKS; i++)
351 if (clk_table[i] && !IS_ERR(clk_table[i]))
352 clk_hw_unregister(clk_table[i]);
353
354 return ret;
355}
356
357static int s3c24xx_dclk_remove(struct platform_device *pdev)
358{
359 struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
360 struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws;
361 int i;
362
363 clk_notifier_unregister(clk_table[DIV_DCLK1]->clk,
364 &s3c24xx_dclk->dclk1_div_change_nb);
365 clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
366 &s3c24xx_dclk->dclk0_div_change_nb);
367
368 for (i = 0; i < DCLK_MAX_CLKS; i++)
369 clk_hw_unregister(clk_table[i]);
370
371 return 0;
372}
373
374static struct s3c24xx_dclk_drv_data dclk_variants[] = {
375 [S3C2410] = {
376 .clkout0_parent_names = clkout0_s3c2410_p,
377 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
378 .clkout1_parent_names = clkout1_s3c2410_p,
379 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
380 .mux_parent_names = dclk_s3c2410_p,
381 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
382 },
383 [S3C2412] = {
384 .clkout0_parent_names = clkout0_s3c2412_p,
385 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
386 .clkout1_parent_names = clkout1_s3c2412_p,
387 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
388 .mux_parent_names = dclk_s3c2410_p,
389 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
390 },
391 [S3C2440] = {
392 .clkout0_parent_names = clkout0_s3c2440_p,
393 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
394 .clkout1_parent_names = clkout1_s3c2440_p,
395 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
396 .mux_parent_names = dclk_s3c2410_p,
397 .mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
398 },
399 [S3C2443] = {
400 .clkout0_parent_names = clkout0_s3c2443_p,
401 .clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
402 .clkout1_parent_names = clkout1_s3c2443_p,
403 .clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
404 .mux_parent_names = dclk_s3c2443_p,
405 .mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
406 },
407};
408
409static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
410 {
411 .name = "s3c2410-dclk",
412 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2410],
413 }, {
414 .name = "s3c2412-dclk",
415 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2412],
416 }, {
417 .name = "s3c2440-dclk",
418 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2440],
419 }, {
420 .name = "s3c2443-dclk",
421 .driver_data = (kernel_ulong_t)&dclk_variants[S3C2443],
422 },
423 { }
424};
425
426MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
427
428static struct platform_driver s3c24xx_dclk_driver = {
429 .driver = {
430 .name = "s3c24xx-dclk",
431 .pm = &s3c24xx_dclk_pm_ops,
432 .suppress_bind_attrs = true,
433 },
434 .probe = s3c24xx_dclk_probe,
435 .remove = s3c24xx_dclk_remove,
436 .id_table = s3c24xx_dclk_driver_ids,
437};
438module_platform_driver(s3c24xx_dclk_driver);
439
440MODULE_LICENSE("GPL v2");
441MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
442MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");
443
