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16#include <linux/slab.h>
17#include <linux/clk-provider.h>
18#include <linux/io.h>
19#include <linux/mfd/syscon.h>
20#include <linux/of.h>
21#include <linux/regmap.h>
22
23#include "clk.h"
24
25#define streq(a, b) (strcmp((a), (b)) == 0)
26
27#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw)
28
29
30#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28
31
32static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk,
33 unsigned long parent_rate)
34{
35 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
36 u32 div = 1, val;
37
38 if (socfpgaclk->fixed_div)
39 div = socfpgaclk->fixed_div;
40 else if (socfpgaclk->div_reg) {
41 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
42 val &= GENMASK(socfpgaclk->width - 1, 0);
43 div = (1 << val);
44 }
45
46 return parent_rate / div;
47}
48
49static int socfpga_clk_prepare(struct clk_hw *hwclk)
50{
51 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
52 int i;
53 u32 hs_timing;
54 u32 clk_phase[2];
55
56 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) {
57 for (i = 0; i < ARRAY_SIZE(clk_phase); i++) {
58 switch (socfpgaclk->clk_phase[i]) {
59 case 0:
60 clk_phase[i] = 0;
61 break;
62 case 45:
63 clk_phase[i] = 1;
64 break;
65 case 90:
66 clk_phase[i] = 2;
67 break;
68 case 135:
69 clk_phase[i] = 3;
70 break;
71 case 180:
72 clk_phase[i] = 4;
73 break;
74 case 225:
75 clk_phase[i] = 5;
76 break;
77 case 270:
78 clk_phase[i] = 6;
79 break;
80 case 315:
81 clk_phase[i] = 7;
82 break;
83 default:
84 clk_phase[i] = 0;
85 break;
86 }
87 }
88
89 hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]);
90 if (!IS_ERR(socfpgaclk->sys_mgr_base_addr))
91 regmap_write(socfpgaclk->sys_mgr_base_addr,
92 SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing);
93 else
94 pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n",
95 __func__);
96 }
97 return 0;
98}
99
100static struct clk_ops gateclk_ops = {
101 .prepare = socfpga_clk_prepare,
102 .recalc_rate = socfpga_gate_clk_recalc_rate,
103};
104
105static void __init __socfpga_gate_init(struct device_node *node,
106 const struct clk_ops *ops)
107{
108 u32 clk_gate[2];
109 u32 div_reg[3];
110 u32 clk_phase[2];
111 u32 fixed_div;
112 struct clk *clk;
113 struct socfpga_gate_clk *socfpga_clk;
114 const char *clk_name = node->name;
115 const char *parent_name[SOCFPGA_MAX_PARENTS];
116 struct clk_init_data init;
117 int rc;
118
119 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
120 if (WARN_ON(!socfpga_clk))
121 return;
122
123 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
124 if (rc)
125 clk_gate[0] = 0;
126
127 if (clk_gate[0]) {
128 socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0];
129 socfpga_clk->hw.bit_idx = clk_gate[1];
130
131 gateclk_ops.enable = clk_gate_ops.enable;
132 gateclk_ops.disable = clk_gate_ops.disable;
133 }
134
135 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
136 if (rc)
137 socfpga_clk->fixed_div = 0;
138 else
139 socfpga_clk->fixed_div = fixed_div;
140
141 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
142 if (!rc) {
143 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0];
144 socfpga_clk->shift = div_reg[1];
145 socfpga_clk->width = div_reg[2];
146 } else {
147 socfpga_clk->div_reg = NULL;
148 }
149
150 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2);
151 if (!rc) {
152 socfpga_clk->clk_phase[0] = clk_phase[0];
153 socfpga_clk->clk_phase[1] = clk_phase[1];
154
155 socfpga_clk->sys_mgr_base_addr =
156 syscon_regmap_lookup_by_compatible("altr,sys-mgr");
157 if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) {
158 pr_err("%s: failed to find altr,sys-mgr regmap!\n",
159 __func__);
160 return;
161 }
162 }
163
164 of_property_read_string(node, "clock-output-names", &clk_name);
165
166 init.name = clk_name;
167 init.ops = ops;
168 init.flags = 0;
169
170 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
171 init.parent_names = parent_name;
172 socfpga_clk->hw.hw.init = &init;
173
174 clk = clk_register(NULL, &socfpga_clk->hw.hw);
175 if (WARN_ON(IS_ERR(clk))) {
176 kfree(socfpga_clk);
177 return;
178 }
179 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
180 if (WARN_ON(rc))
181 return;
182}
183
184void __init socfpga_a10_gate_init(struct device_node *node)
185{
186 __socfpga_gate_init(node, &gateclk_ops);
187}
188
