LXR linux/drivers/clk/socfpga/clk-periph.c

   1/*
   2 *  Copyright 2011-2012 Calxeda, Inc.
   3 *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * Based from clk-highbank.c
  16 *
  17 */
  18#include <linux/slab.h>
  19#include <linux/clk-provider.h>
  20#include <linux/io.h>
  21#include <linux/of.h>
  22
  23#include "clk.h"
  24
  25#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
  26
  27static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
  28                                             unsigned long parent_rate)
  29{
  30        struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
  31        u32 div, val;
  32
  33        if (socfpgaclk->fixed_div) {
  34                div = socfpgaclk->fixed_div;
  35        } else {
  36                if (socfpgaclk->div_reg) {
  37                        val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
  38                        val &= GENMASK(socfpgaclk->width - 1, 0);
  39                        parent_rate /= (val + 1);
  40                }
  41                div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
  42        }
  43
  44        return parent_rate / div;
  45}
  46
  47static u8 clk_periclk_get_parent(struct clk_hw *hwclk)
  48{
  49        u32 clk_src;
  50
  51        clk_src = readl(clk_mgr_base_addr + CLKMGR_DBCTRL);
  52        return clk_src & 0x1;
  53}
  54
  55static const struct clk_ops periclk_ops = {
  56        .recalc_rate = clk_periclk_recalc_rate,
  57        .get_parent = clk_periclk_get_parent,
  58};
  59
  60static __init void __socfpga_periph_init(struct device_node *node,
  61        const struct clk_ops *ops)
  62{
  63        u32 reg;
  64        struct clk *clk;
  65        struct socfpga_periph_clk *periph_clk;
  66        const char *clk_name = node->name;
  67        const char *parent_name[SOCFPGA_MAX_PARENTS];
  68        struct clk_init_data init;
  69        int rc;
  70        u32 fixed_div;
  71        u32 div_reg[3];
  72
  73        of_property_read_u32(node, "reg", &reg);
  74
  75        periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
  76        if (WARN_ON(!periph_clk))
  77                return;
  78
  79        periph_clk->hw.reg = clk_mgr_base_addr + reg;
  80
  81        rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
  82        if (!rc) {
  83                periph_clk->div_reg = clk_mgr_base_addr + div_reg[0];
  84                periph_clk->shift = div_reg[1];
  85                periph_clk->width = div_reg[2];
  86        } else {
  87                periph_clk->div_reg = NULL;
  88        }
  89
  90        rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
  91        if (rc)
  92                periph_clk->fixed_div = 0;
  93        else
  94                periph_clk->fixed_div = fixed_div;
  95
  96        of_property_read_string(node, "clock-output-names", &clk_name);
  97
  98        init.name = clk_name;
  99        init.ops = ops;
 100        init.flags = 0;
 101
 102        init.num_parents = of_clk_parent_fill(node, parent_name,
 103                                              SOCFPGA_MAX_PARENTS);
 104        init.parent_names = parent_name;
 105
 106        periph_clk->hw.hw.init = &init;
 107
 108        clk = clk_register(NULL, &periph_clk->hw.hw);
 109        if (WARN_ON(IS_ERR(clk))) {
 110                kfree(periph_clk);
 111                return;
 112        }
 113        rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 114}
 115
 116void __init socfpga_periph_init(struct device_node *node)
 117{
 118        __socfpga_periph_init(node, &periclk_ops);
 119}
 120