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19#include <linux/clk-provider.h>
20#include <linux/clk.h>
21#include <linux/clkdev.h>
22#include <linux/delay.h>
23#include <linux/module.h>
24#include <linux/of_address.h>
25#include <linux/of_platform.h>
26#include <linux/platform_device.h>
27#include <linux/sort.h>
28#include <linux/string.h>
29
30#include <soc/tegra/fuse.h>
31#include <soc/tegra/emc.h>
32
33#include "clk.h"
34
35#define CLK_SOURCE_EMC 0x19c
36
37#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
38#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
39#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
40 CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
41
42#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
43#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
44#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
45 CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
46
47static const char * const emc_parent_clk_names[] = {
48 "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
49 "pll_c2", "pll_c3", "pll_c_ud"
50};
51
52
53
54
55
56
57
58
59#define EMC_SRC_PLL_M 0
60#define EMC_SRC_PLL_C 1
61#define EMC_SRC_PLL_P 2
62#define EMC_SRC_CLK_M 3
63#define EMC_SRC_PLL_C2 4
64#define EMC_SRC_PLL_C3 5
65
66static const char emc_parent_clk_sources[] = {
67 EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
68 EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
69};
70
71struct emc_timing {
72 unsigned long rate, parent_rate;
73 u8 parent_index;
74 struct clk *parent;
75 u32 ram_code;
76};
77
78struct tegra_clk_emc {
79 struct clk_hw hw;
80 void __iomem *clk_regs;
81 struct clk *prev_parent;
82 bool changing_timing;
83
84 struct device_node *emc_node;
85 struct tegra_emc *emc;
86
87 int num_timings;
88 struct emc_timing *timings;
89 spinlock_t *lock;
90};
91
92
93
94static unsigned long emc_recalc_rate(struct clk_hw *hw,
95 unsigned long parent_rate)
96{
97 struct tegra_clk_emc *tegra;
98 u32 val, div;
99
100 tegra = container_of(hw, struct tegra_clk_emc, hw);
101
102
103
104
105
106 parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
107
108 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
109 div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
110
111 return parent_rate / (div + 2) * 2;
112}
113
114
115
116
117
118
119static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
120{
121 struct tegra_clk_emc *tegra;
122 u8 ram_code = tegra_read_ram_code();
123 struct emc_timing *timing = NULL;
124 int i;
125
126 tegra = container_of(hw, struct tegra_clk_emc, hw);
127
128 for (i = 0; i < tegra->num_timings; i++) {
129 if (tegra->timings[i].ram_code != ram_code)
130 continue;
131
132 timing = tegra->timings + i;
133
134 if (timing->rate > req->max_rate) {
135 i = min(i, 1);
136 req->rate = tegra->timings[i - 1].rate;
137 return 0;
138 }
139
140 if (timing->rate < req->min_rate)
141 continue;
142
143 if (timing->rate >= req->rate) {
144 req->rate = timing->rate;
145 return 0;
146 }
147 }
148
149 if (timing) {
150 req->rate = timing->rate;
151 return 0;
152 }
153
154 req->rate = clk_hw_get_rate(hw);
155 return 0;
156}
157
158static u8 emc_get_parent(struct clk_hw *hw)
159{
160 struct tegra_clk_emc *tegra;
161 u32 val;
162
163 tegra = container_of(hw, struct tegra_clk_emc, hw);
164
165 val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
166
167 return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
168 & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
169}
170
171static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
172{
173 struct platform_device *pdev;
174
175 if (tegra->emc)
176 return tegra->emc;
177
178 if (!tegra->emc_node)
179 return NULL;
180
181 pdev = of_find_device_by_node(tegra->emc_node);
182 if (!pdev) {
183 pr_err("%s: could not get external memory controller\n",
184 __func__);
185 return NULL;
186 }
187
188 of_node_put(tegra->emc_node);
189 tegra->emc_node = NULL;
190
191 tegra->emc = platform_get_drvdata(pdev);
192 if (!tegra->emc) {
193 pr_err("%s: cannot find EMC driver\n", __func__);
194 return NULL;
195 }
196
197 return tegra->emc;
198}
199
200static int emc_set_timing(struct tegra_clk_emc *tegra,
201 struct emc_timing *timing)
202{
203 int err;
204 u8 div;
205 u32 car_value;
206 unsigned long flags = 0;
207 struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
208
209 if (!emc)
210 return -ENOENT;
211
212 pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
213 timing->parent_rate, __clk_get_name(timing->parent));
214
215 if (emc_get_parent(&tegra->hw) == timing->parent_index &&
216 clk_get_rate(timing->parent) != timing->parent_rate) {
217 BUG();
218 return -EINVAL;
219 }
220
221 tegra->changing_timing = true;
222
223 err = clk_set_rate(timing->parent, timing->parent_rate);
224 if (err) {
225 pr_err("cannot change parent %s rate to %ld: %d\n",
226 __clk_get_name(timing->parent), timing->parent_rate,
227 err);
228
229 return err;
230 }
231
232 err = clk_prepare_enable(timing->parent);
233 if (err) {
234 pr_err("cannot enable parent clock: %d\n", err);
235 return err;
236 }
237
238 div = timing->parent_rate / (timing->rate / 2) - 2;
239
240 err = tegra_emc_prepare_timing_change(emc, timing->rate);
241 if (err)
242 return err;
243
244 spin_lock_irqsave(tegra->lock, flags);
245
246 car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
247
248 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
249 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
250
251 car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
252 car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
253
254 writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
255
256 spin_unlock_irqrestore(tegra->lock, flags);
257
258 tegra_emc_complete_timing_change(emc, timing->rate);
259
260 clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
261 clk_disable_unprepare(tegra->prev_parent);
262
263 tegra->prev_parent = timing->parent;
264 tegra->changing_timing = false;
265
266 return 0;
267}
268
269
270
271
272
273
274
275static struct emc_timing *get_backup_timing(struct tegra_clk_emc *tegra,
276 int timing_index)
277{
278 int i;
279 u32 ram_code = tegra_read_ram_code();
280 struct emc_timing *timing;
281
282 for (i = timing_index+1; i < tegra->num_timings; i++) {
283 timing = tegra->timings + i;
284 if (timing->ram_code != ram_code)
285 continue;
286
287 if (emc_parent_clk_sources[timing->parent_index] !=
288 emc_parent_clk_sources[
289 tegra->timings[timing_index].parent_index])
290 return timing;
291 }
292
293 for (i = timing_index-1; i >= 0; --i) {
294 timing = tegra->timings + i;
295 if (timing->ram_code != ram_code)
296 continue;
297
298 if (emc_parent_clk_sources[timing->parent_index] !=
299 emc_parent_clk_sources[
300 tegra->timings[timing_index].parent_index])
301 return timing;
302 }
303
304 return NULL;
305}
306
307static int emc_set_rate(struct clk_hw *hw, unsigned long rate,
308 unsigned long parent_rate)
309{
310 struct tegra_clk_emc *tegra;
311 struct emc_timing *timing = NULL;
312 int i, err;
313 u32 ram_code = tegra_read_ram_code();
314
315 tegra = container_of(hw, struct tegra_clk_emc, hw);
316
317 if (clk_hw_get_rate(hw) == rate)
318 return 0;
319
320
321
322
323
324
325 if (tegra->changing_timing)
326 return 0;
327
328 for (i = 0; i < tegra->num_timings; i++) {
329 if (tegra->timings[i].rate == rate &&
330 tegra->timings[i].ram_code == ram_code) {
331 timing = tegra->timings + i;
332 break;
333 }
334 }
335
336 if (!timing) {
337 pr_err("cannot switch to rate %ld without emc table\n", rate);
338 return -EINVAL;
339 }
340
341 if (emc_parent_clk_sources[emc_get_parent(hw)] ==
342 emc_parent_clk_sources[timing->parent_index] &&
343 clk_get_rate(timing->parent) != timing->parent_rate) {
344
345
346
347
348
349 struct emc_timing *backup_timing;
350
351 backup_timing = get_backup_timing(tegra, i);
352 if (!backup_timing) {
353 pr_err("cannot find backup timing\n");
354 return -EINVAL;
355 }
356
357 pr_debug("using %ld as backup rate when going to %ld\n",
358 backup_timing->rate, rate);
359
360 err = emc_set_timing(tegra, backup_timing);
361 if (err) {
362 pr_err("cannot set backup timing: %d\n", err);
363 return err;
364 }
365 }
366
367 return emc_set_timing(tegra, timing);
368}
369
370
371
372static int load_one_timing_from_dt(struct tegra_clk_emc *tegra,
373 struct emc_timing *timing,
374 struct device_node *node)
375{
376 int err, i;
377 u32 tmp;
378
379 err = of_property_read_u32(node, "clock-frequency", &tmp);
380 if (err) {
381 pr_err("timing %pOF: failed to read rate\n", node);
382 return err;
383 }
384
385 timing->rate = tmp;
386
387 err = of_property_read_u32(node, "nvidia,parent-clock-frequency", &tmp);
388 if (err) {
389 pr_err("timing %pOF: failed to read parent rate\n", node);
390 return err;
391 }
392
393 timing->parent_rate = tmp;
394
395 timing->parent = of_clk_get_by_name(node, "emc-parent");
396 if (IS_ERR(timing->parent)) {
397 pr_err("timing %pOF: failed to get parent clock\n", node);
398 return PTR_ERR(timing->parent);
399 }
400
401 timing->parent_index = 0xff;
402 for (i = 0; i < ARRAY_SIZE(emc_parent_clk_names); i++) {
403 if (!strcmp(emc_parent_clk_names[i],
404 __clk_get_name(timing->parent))) {
405 timing->parent_index = i;
406 break;
407 }
408 }
409 if (timing->parent_index == 0xff) {
410 pr_err("timing %pOF: %s is not a valid parent\n",
411 node, __clk_get_name(timing->parent));
412 clk_put(timing->parent);
413 return -EINVAL;
414 }
415
416 return 0;
417}
418
419static int cmp_timings(const void *_a, const void *_b)
420{
421 const struct emc_timing *a = _a;
422 const struct emc_timing *b = _b;
423
424 if (a->rate < b->rate)
425 return -1;
426 else if (a->rate == b->rate)
427 return 0;
428 else
429 return 1;
430}
431
432static int load_timings_from_dt(struct tegra_clk_emc *tegra,
433 struct device_node *node,
434 u32 ram_code)
435{
436 struct device_node *child;
437 int child_count = of_get_child_count(node);
438 int i = 0, err;
439
440 tegra->timings = kcalloc(child_count, sizeof(struct emc_timing),
441 GFP_KERNEL);
442 if (!tegra->timings)
443 return -ENOMEM;
444
445 tegra->num_timings = child_count;
446
447 for_each_child_of_node(node, child) {
448 struct emc_timing *timing = tegra->timings + (i++);
449
450 err = load_one_timing_from_dt(tegra, timing, child);
451 if (err) {
452 of_node_put(child);
453 return err;
454 }
455
456 timing->ram_code = ram_code;
457 }
458
459 sort(tegra->timings, tegra->num_timings, sizeof(struct emc_timing),
460 cmp_timings, NULL);
461
462 return 0;
463}
464
465static const struct clk_ops tegra_clk_emc_ops = {
466 .recalc_rate = emc_recalc_rate,
467 .determine_rate = emc_determine_rate,
468 .set_rate = emc_set_rate,
469 .get_parent = emc_get_parent,
470};
471
472struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
473 spinlock_t *lock)
474{
475 struct tegra_clk_emc *tegra;
476 struct clk_init_data init;
477 struct device_node *node;
478 u32 node_ram_code;
479 struct clk *clk;
480 int err;
481
482 tegra = kcalloc(1, sizeof(*tegra), GFP_KERNEL);
483 if (!tegra)
484 return ERR_PTR(-ENOMEM);
485
486 tegra->clk_regs = base;
487 tegra->lock = lock;
488
489 tegra->num_timings = 0;
490
491 for_each_child_of_node(np, node) {
492 err = of_property_read_u32(node, "nvidia,ram-code",
493 &node_ram_code);
494 if (err)
495 continue;
496
497
498
499
500
501 err = load_timings_from_dt(tegra, node, node_ram_code);
502 of_node_put(node);
503 if (err)
504 return ERR_PTR(err);
505 break;
506 }
507
508 if (tegra->num_timings == 0)
509 pr_warn("%s: no memory timings registered\n", __func__);
510
511 tegra->emc_node = of_parse_phandle(np,
512 "nvidia,external-memory-controller", 0);
513 if (!tegra->emc_node)
514 pr_warn("%s: couldn't find node for EMC driver\n", __func__);
515
516 init.name = "emc";
517 init.ops = &tegra_clk_emc_ops;
518 init.flags = CLK_IS_CRITICAL;
519 init.parent_names = emc_parent_clk_names;
520 init.num_parents = ARRAY_SIZE(emc_parent_clk_names);
521
522 tegra->hw.init = &init;
523
524 clk = clk_register(NULL, &tegra->hw);
525 if (IS_ERR(clk))
526 return clk;
527
528 tegra->prev_parent = clk_hw_get_parent_by_index(
529 &tegra->hw, emc_get_parent(&tegra->hw))->clk;
530 tegra->changing_timing = false;
531
532
533 clk_register_clkdev(clk, "emc", "tegra-clk-debug");
534
535 clk_prepare_enable(clk);
536
537 return clk;
538};
539