1
2
3
4
5
6
7
8
9
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/clk-provider.h>
13#include <linux/mfd/dbx500-prcmu.h>
14#include "clk.h"
15
16#define PRCC_NUM_PERIPH_CLUSTERS 6
17#define PRCC_PERIPHS_PER_CLUSTER 32
18
19static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
20static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
21static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22
23#define PRCC_SHOW(clk, base, bit) \
24 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
25#define PRCC_PCLK_STORE(clk, base, bit) \
26 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
27#define PRCC_KCLK_STORE(clk, base, bit) \
28 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
29
30static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec,
31 void *data)
32{
33 struct clk **clk_data = data;
34 unsigned int base, bit;
35
36 if (clkspec->args_count != 2)
37 return ERR_PTR(-EINVAL);
38
39 base = clkspec->args[0];
40 bit = clkspec->args[1];
41
42 if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
43 pr_err("%s: invalid PRCC base %d\n", __func__, base);
44 return ERR_PTR(-EINVAL);
45 }
46
47 return PRCC_SHOW(clk_data, base, bit);
48}
49
50
51enum clkrst_index {
52 CLKRST1_INDEX = 0,
53 CLKRST2_INDEX,
54 CLKRST3_INDEX,
55 CLKRST5_INDEX,
56 CLKRST6_INDEX,
57 CLKRST_MAX,
58};
59
60static void u8500_clk_init(struct device_node *np)
61{
62 struct prcmu_fw_version *fw_version;
63 struct device_node *child = NULL;
64 const char *sgaclk_parent = NULL;
65 struct clk *clk, *rtc_clk, *twd_clk;
66 u32 bases[CLKRST_MAX];
67 int i;
68
69 for (i = 0; i < ARRAY_SIZE(bases); i++) {
70 struct resource r;
71
72 if (of_address_to_resource(np, i, &r))
73
74 pr_err("failed to get CLKRST %d base address\n",
75 i + 1);
76 bases[i] = r.start;
77 }
78
79
80 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
81 CLK_IGNORE_UNUSED);
82 prcmu_clk[PRCMU_PLLSOC0] = clk;
83
84 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
85 CLK_IGNORE_UNUSED);
86 prcmu_clk[PRCMU_PLLSOC1] = clk;
87
88 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
89 CLK_IGNORE_UNUSED);
90 prcmu_clk[PRCMU_PLLDDR] = clk;
91
92
93
94 rtc_clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
95 CLK_IGNORE_UNUSED,
96 32768);
97
98
99 fw_version = prcmu_get_fw_version();
100 if (fw_version != NULL) {
101 switch (fw_version->project) {
102 case PRCMU_FW_PROJECT_U8500_C2:
103 case PRCMU_FW_PROJECT_U8520:
104 case PRCMU_FW_PROJECT_U8420:
105 sgaclk_parent = "soc0_pll";
106 break;
107 default:
108 break;
109 }
110 }
111
112 if (sgaclk_parent)
113 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
114 PRCMU_SGACLK, 0);
115 else
116 clk = clk_reg_prcmu_gate("sgclk", NULL, PRCMU_SGACLK, 0);
117 prcmu_clk[PRCMU_SGACLK] = clk;
118
119 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, 0);
120 prcmu_clk[PRCMU_UARTCLK] = clk;
121
122 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, 0);
123 prcmu_clk[PRCMU_MSP02CLK] = clk;
124
125 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, 0);
126 prcmu_clk[PRCMU_MSP1CLK] = clk;
127
128 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, 0);
129 prcmu_clk[PRCMU_I2CCLK] = clk;
130
131 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, 0);
132 prcmu_clk[PRCMU_SLIMCLK] = clk;
133
134 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, 0);
135 prcmu_clk[PRCMU_PER1CLK] = clk;
136
137 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, 0);
138 prcmu_clk[PRCMU_PER2CLK] = clk;
139
140 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, 0);
141 prcmu_clk[PRCMU_PER3CLK] = clk;
142
143 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, 0);
144 prcmu_clk[PRCMU_PER5CLK] = clk;
145
146 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, 0);
147 prcmu_clk[PRCMU_PER6CLK] = clk;
148
149 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, 0);
150 prcmu_clk[PRCMU_PER7CLK] = clk;
151
152 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
153 CLK_SET_RATE_GATE);
154 prcmu_clk[PRCMU_LCDCLK] = clk;
155
156 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, 0);
157 prcmu_clk[PRCMU_BMLCLK] = clk;
158
159 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
160 CLK_SET_RATE_GATE);
161 prcmu_clk[PRCMU_HSITXCLK] = clk;
162
163 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
164 CLK_SET_RATE_GATE);
165 prcmu_clk[PRCMU_HSIRXCLK] = clk;
166
167 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
168 CLK_SET_RATE_GATE);
169 prcmu_clk[PRCMU_HDMICLK] = clk;
170
171 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, 0);
172 prcmu_clk[PRCMU_APEATCLK] = clk;
173
174 clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0,
175 CLK_SET_RATE_GATE);
176 prcmu_clk[PRCMU_APETRACECLK] = clk;
177
178 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, 0);
179 prcmu_clk[PRCMU_MCDECLK] = clk;
180
181 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, 0);
182 prcmu_clk[PRCMU_IPI2CCLK] = clk;
183
184 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, 0);
185 prcmu_clk[PRCMU_DSIALTCLK] = clk;
186
187 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, 0);
188 prcmu_clk[PRCMU_DMACLK] = clk;
189
190 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, 0);
191 prcmu_clk[PRCMU_B2R2CLK] = clk;
192
193 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
194 CLK_SET_RATE_GATE);
195 prcmu_clk[PRCMU_TVCLK] = clk;
196
197 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, 0);
198 prcmu_clk[PRCMU_SSPCLK] = clk;
199
200 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, 0);
201 prcmu_clk[PRCMU_RNGCLK] = clk;
202
203 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, 0);
204 prcmu_clk[PRCMU_UICCCLK] = clk;
205
206 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, 0);
207 prcmu_clk[PRCMU_TIMCLK] = clk;
208
209 clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, 0);
210 prcmu_clk[PRCMU_SYSCLK] = clk;
211
212 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
213 100000000, CLK_SET_RATE_GATE);
214 prcmu_clk[PRCMU_SDMMCCLK] = clk;
215
216 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
217 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
218 prcmu_clk[PRCMU_PLLDSI] = clk;
219
220 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
221 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
222 prcmu_clk[PRCMU_DSI0CLK] = clk;
223
224 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
225 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
226 prcmu_clk[PRCMU_DSI1CLK] = clk;
227
228 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
229 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
230 prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
231
232 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
233 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
234 prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
235
236 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
237 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
238 prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
239
240 clk = clk_reg_prcmu_scalable_rate("armss", NULL,
241 PRCMU_ARMSS, 0, CLK_IGNORE_UNUSED);
242 prcmu_clk[PRCMU_ARMSS] = clk;
243
244 twd_clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
245 CLK_IGNORE_UNUSED, 1, 2);
246
247
248
249
250
251
252
253
254 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX],
255 BIT(0), 0);
256 PRCC_PCLK_STORE(clk, 1, 0);
257
258 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX],
259 BIT(1), 0);
260 PRCC_PCLK_STORE(clk, 1, 1);
261
262 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX],
263 BIT(2), 0);
264 PRCC_PCLK_STORE(clk, 1, 2);
265
266 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX],
267 BIT(3), 0);
268 PRCC_PCLK_STORE(clk, 1, 3);
269
270 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX],
271 BIT(4), 0);
272 PRCC_PCLK_STORE(clk, 1, 4);
273
274 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX],
275 BIT(5), 0);
276 PRCC_PCLK_STORE(clk, 1, 5);
277
278 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX],
279 BIT(6), 0);
280 PRCC_PCLK_STORE(clk, 1, 6);
281
282 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX],
283 BIT(7), 0);
284 PRCC_PCLK_STORE(clk, 1, 7);
285
286 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX],
287 BIT(8), 0);
288 PRCC_PCLK_STORE(clk, 1, 8);
289
290 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX],
291 BIT(9), 0);
292 PRCC_PCLK_STORE(clk, 1, 9);
293
294 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX],
295 BIT(10), 0);
296 PRCC_PCLK_STORE(clk, 1, 10);
297
298 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX],
299 BIT(11), 0);
300 PRCC_PCLK_STORE(clk, 1, 11);
301
302 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX],
303 BIT(0), 0);
304 PRCC_PCLK_STORE(clk, 2, 0);
305
306 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX],
307 BIT(1), 0);
308 PRCC_PCLK_STORE(clk, 2, 1);
309
310 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX],
311 BIT(2), 0);
312 PRCC_PCLK_STORE(clk, 2, 2);
313
314 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX],
315 BIT(3), 0);
316 PRCC_PCLK_STORE(clk, 2, 3);
317
318 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX],
319 BIT(4), 0);
320 PRCC_PCLK_STORE(clk, 2, 4);
321
322 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX],
323 BIT(5), 0);
324 PRCC_PCLK_STORE(clk, 2, 5);
325
326 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX],
327 BIT(6), 0);
328 PRCC_PCLK_STORE(clk, 2, 6);
329
330 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX],
331 BIT(7), 0);
332 PRCC_PCLK_STORE(clk, 2, 7);
333
334 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX],
335 BIT(8), 0);
336 PRCC_PCLK_STORE(clk, 2, 8);
337
338 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX],
339 BIT(9), 0);
340 PRCC_PCLK_STORE(clk, 2, 9);
341
342 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX],
343 BIT(10), 0);
344 PRCC_PCLK_STORE(clk, 2, 10);
345
346 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX],
347 BIT(11), 0);
348 PRCC_PCLK_STORE(clk, 2, 11);
349
350 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX],
351 BIT(12), 0);
352 PRCC_PCLK_STORE(clk, 2, 12);
353
354 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX],
355 BIT(0), 0);
356 PRCC_PCLK_STORE(clk, 3, 0);
357
358 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX],
359 BIT(1), 0);
360 PRCC_PCLK_STORE(clk, 3, 1);
361
362 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX],
363 BIT(2), 0);
364 PRCC_PCLK_STORE(clk, 3, 2);
365
366 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX],
367 BIT(3), 0);
368 PRCC_PCLK_STORE(clk, 3, 3);
369
370 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX],
371 BIT(4), 0);
372 PRCC_PCLK_STORE(clk, 3, 4);
373
374 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX],
375 BIT(5), 0);
376 PRCC_PCLK_STORE(clk, 3, 5);
377
378 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX],
379 BIT(6), 0);
380 PRCC_PCLK_STORE(clk, 3, 6);
381
382 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX],
383 BIT(7), 0);
384 PRCC_PCLK_STORE(clk, 3, 7);
385
386 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX],
387 BIT(8), 0);
388 PRCC_PCLK_STORE(clk, 3, 8);
389
390 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX],
391 BIT(0), 0);
392 PRCC_PCLK_STORE(clk, 5, 0);
393
394 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX],
395 BIT(1), 0);
396 PRCC_PCLK_STORE(clk, 5, 1);
397
398 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX],
399 BIT(0), 0);
400 PRCC_PCLK_STORE(clk, 6, 0);
401
402 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX],
403 BIT(1), 0);
404 PRCC_PCLK_STORE(clk, 6, 1);
405
406 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX],
407 BIT(2), 0);
408 PRCC_PCLK_STORE(clk, 6, 2);
409
410 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX],
411 BIT(3), 0);
412 PRCC_PCLK_STORE(clk, 6, 3);
413
414 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX],
415 BIT(4), 0);
416 PRCC_PCLK_STORE(clk, 6, 4);
417
418 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX],
419 BIT(5), 0);
420 PRCC_PCLK_STORE(clk, 6, 5);
421
422 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX],
423 BIT(6), 0);
424 PRCC_PCLK_STORE(clk, 6, 6);
425
426 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX],
427 BIT(7), 0);
428 PRCC_PCLK_STORE(clk, 6, 7);
429
430
431
432
433
434
435
436
437
438
439 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
440 bases[CLKRST1_INDEX], BIT(0), CLK_SET_RATE_GATE);
441 PRCC_KCLK_STORE(clk, 1, 0);
442
443 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
444 bases[CLKRST1_INDEX], BIT(1), CLK_SET_RATE_GATE);
445 PRCC_KCLK_STORE(clk, 1, 1);
446
447 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
448 bases[CLKRST1_INDEX], BIT(2), CLK_SET_RATE_GATE);
449 PRCC_KCLK_STORE(clk, 1, 2);
450
451 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
452 bases[CLKRST1_INDEX], BIT(3), CLK_SET_RATE_GATE);
453 PRCC_KCLK_STORE(clk, 1, 3);
454
455 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
456 bases[CLKRST1_INDEX], BIT(4), CLK_SET_RATE_GATE);
457 PRCC_KCLK_STORE(clk, 1, 4);
458
459 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
460 bases[CLKRST1_INDEX], BIT(5), CLK_SET_RATE_GATE);
461 PRCC_KCLK_STORE(clk, 1, 5);
462
463 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
464 bases[CLKRST1_INDEX], BIT(6), CLK_SET_RATE_GATE);
465 PRCC_KCLK_STORE(clk, 1, 6);
466
467 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
468 bases[CLKRST1_INDEX], BIT(8), CLK_SET_RATE_GATE);
469 PRCC_KCLK_STORE(clk, 1, 8);
470
471 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
472 bases[CLKRST1_INDEX], BIT(9), CLK_SET_RATE_GATE);
473 PRCC_KCLK_STORE(clk, 1, 9);
474
475 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
476 bases[CLKRST1_INDEX], BIT(10), CLK_SET_RATE_GATE);
477 PRCC_KCLK_STORE(clk, 1, 10);
478
479
480 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
481 bases[CLKRST2_INDEX], BIT(0), CLK_SET_RATE_GATE);
482 PRCC_KCLK_STORE(clk, 2, 0);
483
484 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
485 bases[CLKRST2_INDEX], BIT(2), CLK_SET_RATE_GATE);
486 PRCC_KCLK_STORE(clk, 2, 2);
487
488 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
489 bases[CLKRST2_INDEX], BIT(3), CLK_SET_RATE_GATE);
490 PRCC_KCLK_STORE(clk, 2, 3);
491
492 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
493 bases[CLKRST2_INDEX], BIT(4), CLK_SET_RATE_GATE);
494 PRCC_KCLK_STORE(clk, 2, 4);
495
496 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
497 bases[CLKRST2_INDEX], BIT(5), CLK_SET_RATE_GATE);
498 PRCC_KCLK_STORE(clk, 2, 5);
499
500
501 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
502 bases[CLKRST2_INDEX], BIT(6),
503 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
504 PRCC_KCLK_STORE(clk, 2, 6);
505
506 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
507 bases[CLKRST2_INDEX], BIT(7),
508 CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
509 PRCC_KCLK_STORE(clk, 2, 7);
510
511
512 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
513 bases[CLKRST3_INDEX], BIT(1), CLK_SET_RATE_GATE);
514 PRCC_KCLK_STORE(clk, 3, 1);
515
516 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
517 bases[CLKRST3_INDEX], BIT(2), CLK_SET_RATE_GATE);
518 PRCC_KCLK_STORE(clk, 3, 2);
519
520 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
521 bases[CLKRST3_INDEX], BIT(3), CLK_SET_RATE_GATE);
522 PRCC_KCLK_STORE(clk, 3, 3);
523
524 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
525 bases[CLKRST3_INDEX], BIT(4), CLK_SET_RATE_GATE);
526 PRCC_KCLK_STORE(clk, 3, 4);
527
528 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
529 bases[CLKRST3_INDEX], BIT(5), CLK_SET_RATE_GATE);
530 PRCC_KCLK_STORE(clk, 3, 5);
531
532 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
533 bases[CLKRST3_INDEX], BIT(6), CLK_SET_RATE_GATE);
534 PRCC_KCLK_STORE(clk, 3, 6);
535
536 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
537 bases[CLKRST3_INDEX], BIT(7), CLK_SET_RATE_GATE);
538 PRCC_KCLK_STORE(clk, 3, 7);
539
540
541 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
542 bases[CLKRST6_INDEX], BIT(0), CLK_SET_RATE_GATE);
543 PRCC_KCLK_STORE(clk, 6, 0);
544
545 for_each_child_of_node(np, child) {
546 static struct clk_onecell_data clk_data;
547
548 if (!of_node_cmp(child->name, "prcmu-clock")) {
549 clk_data.clks = prcmu_clk;
550 clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
551 of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
552 }
553 if (!of_node_cmp(child->name, "prcc-periph-clock"))
554 of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
555
556 if (!of_node_cmp(child->name, "prcc-kernel-clock"))
557 of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
558
559 if (!of_node_cmp(child->name, "rtc32k-clock"))
560 of_clk_add_provider(child, of_clk_src_simple_get, rtc_clk);
561
562 if (!of_node_cmp(child->name, "smp-twd-clock"))
563 of_clk_add_provider(child, of_clk_src_simple_get, twd_clk);
564 }
565}
566CLK_OF_DECLARE(u8500_clks, "stericsson,u8500-clks", u8500_clk_init);
567
