1
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5
6
7#include <linux/device.h>
8#include <linux/of_address.h>
9#include <linux/of_irq.h>
10#include <linux/sys_soc.h>
11
12#include "compat.h"
13#include "regs.h"
14#include "intern.h"
15#include "jr.h"
16#include "desc_constr.h"
17#include "ctrl.h"
18
19bool caam_little_end;
20EXPORT_SYMBOL(caam_little_end);
21bool caam_dpaa2;
22EXPORT_SYMBOL(caam_dpaa2);
23bool caam_imx;
24EXPORT_SYMBOL(caam_imx);
25
26#ifdef CONFIG_CAAM_QI
27#include "qi.h"
28#endif
29
30
31
32
33
34static inline struct clk *caam_drv_identify_clk(struct device *dev,
35 char *clk_name)
36{
37 return caam_imx ? devm_clk_get(dev, clk_name) : NULL;
38}
39
40
41
42
43
44static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
45{
46 u32 *jump_cmd, op_flags;
47
48 init_job_desc(desc, 0);
49
50 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
51 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
52
53
54 append_operation(desc, op_flags);
55
56 if (!handle && do_sk) {
57
58
59
60
61
62 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
63 set_jump_tgt_here(desc, jump_cmd);
64
65
66
67
68
69 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
70
71
72 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
73 OP_ALG_AAI_RNG4_SK);
74 }
75
76 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
77}
78
79
80static void build_deinstantiation_desc(u32 *desc, int handle)
81{
82 init_job_desc(desc, 0);
83
84
85 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
86 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
87
88 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
89}
90
91
92
93
94
95
96
97
98
99
100
101static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
102 u32 *status)
103{
104 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
105 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
106 struct caam_deco __iomem *deco = ctrlpriv->deco;
107 unsigned int timeout = 100000;
108 u32 deco_dbg_reg, flags;
109 int i;
110
111
112 if (ctrlpriv->virt_en == 1) {
113 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
114
115 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
116 --timeout)
117 cpu_relax();
118
119 timeout = 100000;
120 }
121
122 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
123
124 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
125 --timeout)
126 cpu_relax();
127
128 if (!timeout) {
129 dev_err(ctrldev, "failed to acquire DECO 0\n");
130 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
131 return -ENODEV;
132 }
133
134 for (i = 0; i < desc_len(desc); i++)
135 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
136
137 flags = DECO_JQCR_WHL;
138
139
140
141
142 if (desc_len(desc) >= 4)
143 flags |= DECO_JQCR_FOUR;
144
145
146 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
147
148 timeout = 10000000;
149 do {
150 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
151
152
153
154
155 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
156 DESC_DBG_DECO_STAT_HOST_ERR)
157 break;
158 cpu_relax();
159 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
160
161 *status = rd_reg32(&deco->op_status_hi) &
162 DECO_OP_STATUS_HI_ERR_MASK;
163
164 if (ctrlpriv->virt_en == 1)
165 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
166
167
168 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
169
170 if (!timeout)
171 return -EAGAIN;
172
173 return 0;
174}
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
196 int gen_sk)
197{
198 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
199 struct caam_ctrl __iomem *ctrl;
200 u32 *desc, status = 0, rdsta_val;
201 int ret = 0, sh_idx;
202
203 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
204 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
205 if (!desc)
206 return -ENOMEM;
207
208 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
209
210
211
212
213 if ((1 << sh_idx) & state_handle_mask)
214 continue;
215
216
217 build_instantiation_desc(desc, sh_idx, gen_sk);
218
219
220 ret = run_descriptor_deco0(ctrldev, desc, &status);
221
222
223
224
225
226
227
228
229
230
231 if (ret)
232 break;
233
234 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
235 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
236 !(rdsta_val & (1 << sh_idx))) {
237 ret = -EAGAIN;
238 break;
239 }
240
241 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
242
243 memset(desc, 0x00, CAAM_CMD_SZ * 7);
244 }
245
246 kfree(desc);
247
248 return ret;
249}
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
265{
266 u32 *desc, status;
267 int sh_idx, ret = 0;
268
269 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
270 if (!desc)
271 return -ENOMEM;
272
273 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
274
275
276
277
278
279 if ((1 << sh_idx) & state_handle_mask) {
280
281
282
283
284 build_deinstantiation_desc(desc, sh_idx);
285
286
287 ret = run_descriptor_deco0(ctrldev, desc, &status);
288
289 if (ret ||
290 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
291 dev_err(ctrldev,
292 "Failed to deinstantiate RNG4 SH%d\n",
293 sh_idx);
294 break;
295 }
296 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
297 }
298 }
299
300 kfree(desc);
301
302 return ret;
303}
304
305static int caam_remove(struct platform_device *pdev)
306{
307 struct device *ctrldev;
308 struct caam_drv_private *ctrlpriv;
309 struct caam_ctrl __iomem *ctrl;
310
311 ctrldev = &pdev->dev;
312 ctrlpriv = dev_get_drvdata(ctrldev);
313 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
314
315
316 of_platform_depopulate(ctrldev);
317
318#ifdef CONFIG_CAAM_QI
319 if (ctrlpriv->qidev)
320 caam_qi_shutdown(ctrlpriv->qidev);
321#endif
322
323
324
325
326
327 if (!caam_dpaa2 && ctrlpriv->rng4_sh_init)
328 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
329
330
331#ifdef CONFIG_DEBUG_FS
332 debugfs_remove_recursive(ctrlpriv->dfs_root);
333#endif
334
335
336 iounmap(ctrl);
337
338
339 clk_disable_unprepare(ctrlpriv->caam_ipg);
340 if (ctrlpriv->caam_mem)
341 clk_disable_unprepare(ctrlpriv->caam_mem);
342 clk_disable_unprepare(ctrlpriv->caam_aclk);
343 if (ctrlpriv->caam_emi_slow)
344 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
345 return 0;
346}
347
348
349
350
351
352
353
354static void kick_trng(struct platform_device *pdev, int ent_delay)
355{
356 struct device *ctrldev = &pdev->dev;
357 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
358 struct caam_ctrl __iomem *ctrl;
359 struct rng4tst __iomem *r4tst;
360 u32 val;
361
362 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
363 r4tst = &ctrl->r4tst[0];
364
365
366 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
367
368
369
370
371
372
373
374
375
376 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
377 >> RTSDCTL_ENT_DLY_SHIFT;
378 if (ent_delay <= val)
379 goto start_rng;
380
381 val = rd_reg32(&r4tst->rtsdctl);
382 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
383 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
384 wr_reg32(&r4tst->rtsdctl, val);
385
386 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
387
388 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
389
390 val = rd_reg32(&r4tst->rtmctl);
391start_rng:
392
393
394
395
396 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
397}
398
399
400
401
402
403int caam_get_era(void)
404{
405 struct device_node *caam_node;
406 int ret;
407 u32 prop;
408
409 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
410 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
411 of_node_put(caam_node);
412
413 return ret ? -ENOTSUPP : prop;
414}
415EXPORT_SYMBOL(caam_get_era);
416
417static const struct of_device_id caam_match[] = {
418 {
419 .compatible = "fsl,sec-v4.0",
420 },
421 {
422 .compatible = "fsl,sec4.0",
423 },
424 {},
425};
426MODULE_DEVICE_TABLE(of, caam_match);
427
428
429static int caam_probe(struct platform_device *pdev)
430{
431 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
432 u64 caam_id;
433 static const struct soc_device_attribute imx_soc[] = {
434 {.family = "Freescale i.MX"},
435 {},
436 };
437 struct device *dev;
438 struct device_node *nprop, *np;
439 struct caam_ctrl __iomem *ctrl;
440 struct caam_drv_private *ctrlpriv;
441 struct clk *clk;
442#ifdef CONFIG_DEBUG_FS
443 struct caam_perfmon *perfmon;
444#endif
445 u32 scfgr, comp_params;
446 u32 cha_vid_ls;
447 int pg_size;
448 int BLOCK_OFFSET = 0;
449
450 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
451 if (!ctrlpriv)
452 return -ENOMEM;
453
454 dev = &pdev->dev;
455 dev_set_drvdata(dev, ctrlpriv);
456 nprop = pdev->dev.of_node;
457
458 caam_imx = (bool)soc_device_match(imx_soc);
459
460
461 clk = caam_drv_identify_clk(&pdev->dev, "ipg");
462 if (IS_ERR(clk)) {
463 ret = PTR_ERR(clk);
464 dev_err(&pdev->dev,
465 "can't identify CAAM ipg clk: %d\n", ret);
466 return ret;
467 }
468 ctrlpriv->caam_ipg = clk;
469
470 if (!of_machine_is_compatible("fsl,imx7d") &&
471 !of_machine_is_compatible("fsl,imx7s")) {
472 clk = caam_drv_identify_clk(&pdev->dev, "mem");
473 if (IS_ERR(clk)) {
474 ret = PTR_ERR(clk);
475 dev_err(&pdev->dev,
476 "can't identify CAAM mem clk: %d\n", ret);
477 return ret;
478 }
479 ctrlpriv->caam_mem = clk;
480 }
481
482 clk = caam_drv_identify_clk(&pdev->dev, "aclk");
483 if (IS_ERR(clk)) {
484 ret = PTR_ERR(clk);
485 dev_err(&pdev->dev,
486 "can't identify CAAM aclk clk: %d\n", ret);
487 return ret;
488 }
489 ctrlpriv->caam_aclk = clk;
490
491 if (!of_machine_is_compatible("fsl,imx6ul") &&
492 !of_machine_is_compatible("fsl,imx7d") &&
493 !of_machine_is_compatible("fsl,imx7s")) {
494 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
495 if (IS_ERR(clk)) {
496 ret = PTR_ERR(clk);
497 dev_err(&pdev->dev,
498 "can't identify CAAM emi_slow clk: %d\n", ret);
499 return ret;
500 }
501 ctrlpriv->caam_emi_slow = clk;
502 }
503
504 ret = clk_prepare_enable(ctrlpriv->caam_ipg);
505 if (ret < 0) {
506 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
507 return ret;
508 }
509
510 if (ctrlpriv->caam_mem) {
511 ret = clk_prepare_enable(ctrlpriv->caam_mem);
512 if (ret < 0) {
513 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
514 ret);
515 goto disable_caam_ipg;
516 }
517 }
518
519 ret = clk_prepare_enable(ctrlpriv->caam_aclk);
520 if (ret < 0) {
521 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
522 goto disable_caam_mem;
523 }
524
525 if (ctrlpriv->caam_emi_slow) {
526 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
527 if (ret < 0) {
528 dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
529 ret);
530 goto disable_caam_aclk;
531 }
532 }
533
534
535
536 ctrl = of_iomap(nprop, 0);
537 if (ctrl == NULL) {
538 dev_err(dev, "caam: of_iomap() failed\n");
539 ret = -ENOMEM;
540 goto disable_caam_emi_slow;
541 }
542
543 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
544 (CSTA_PLEND | CSTA_ALT_PLEND));
545
546
547 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
548 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
549
550
551
552
553 if (pg_size == 0)
554 BLOCK_OFFSET = PG_SIZE_4K;
555 else
556 BLOCK_OFFSET = PG_SIZE_64K;
557
558 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
559 ctrlpriv->assure = (struct caam_assurance __iomem __force *)
560 ((__force uint8_t *)ctrl +
561 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
562 );
563 ctrlpriv->deco = (struct caam_deco __iomem __force *)
564 ((__force uint8_t *)ctrl +
565 BLOCK_OFFSET * DECO_BLOCK_NUMBER
566 );
567
568
569 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
570
571
572
573
574
575
576
577 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
578 if (!caam_dpaa2)
579 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
580 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
581 MCFGR_WDENABLE | MCFGR_LARGE_BURST |
582 (sizeof(dma_addr_t) == sizeof(u64) ?
583 MCFGR_LONG_PTR : 0));
584
585
586
587
588
589 scfgr = rd_reg32(&ctrl->scfgr);
590
591 ctrlpriv->virt_en = 0;
592 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
593
594
595
596 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
597 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
598 (scfgr & SCFGR_VIRT_EN)))
599 ctrlpriv->virt_en = 1;
600 } else {
601
602 if (comp_params & CTPR_MS_VIRT_EN_POR)
603 ctrlpriv->virt_en = 1;
604 }
605
606 if (ctrlpriv->virt_en == 1)
607 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
608 JRSTART_JR1_START | JRSTART_JR2_START |
609 JRSTART_JR3_START);
610
611 if (sizeof(dma_addr_t) == sizeof(u64)) {
612 if (caam_dpaa2)
613 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
614 else if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
615 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
616 else
617 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
618 } else {
619 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
620 }
621 if (ret) {
622 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
623 goto iounmap_ctrl;
624 }
625
626 ctrlpriv->era = caam_get_era();
627
628 ret = of_platform_populate(nprop, caam_match, NULL, dev);
629 if (ret) {
630 dev_err(dev, "JR platform devices creation error\n");
631 goto iounmap_ctrl;
632 }
633
634#ifdef CONFIG_DEBUG_FS
635
636
637
638
639
640 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
641
642 ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
643 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
644#endif
645
646 ring = 0;
647 for_each_available_child_of_node(nprop, np)
648 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
649 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
650 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
651 ((__force uint8_t *)ctrl +
652 (ring + JR_BLOCK_NUMBER) *
653 BLOCK_OFFSET
654 );
655 ctrlpriv->total_jobrs++;
656 ring++;
657 }
658
659
660 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
661 if (ctrlpriv->qi_present && !caam_dpaa2) {
662 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
663 ((__force uint8_t *)ctrl +
664 BLOCK_OFFSET * QI_BLOCK_NUMBER
665 );
666
667 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
668
669
670#ifdef CONFIG_CAAM_QI
671 ret = caam_qi_init(pdev);
672 if (ret)
673 dev_err(dev, "caam qi i/f init failed: %d\n", ret);
674#endif
675 }
676
677
678 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
679 dev_err(dev, "no queues configured, terminating\n");
680 ret = -ENOMEM;
681 goto caam_remove;
682 }
683
684 cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
685
686
687
688
689
690
691 if (!caam_dpaa2 &&
692 (cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
693 ctrlpriv->rng4_sh_init =
694 rd_reg32(&ctrl->r4tst[0].rdsta);
695
696
697
698
699
700
701 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
702 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
703 do {
704 int inst_handles =
705 rd_reg32(&ctrl->r4tst[0].rdsta) &
706 RDSTA_IFMASK;
707
708
709
710
711
712
713
714
715 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
716 dev_info(dev,
717 "Entropy delay = %u\n",
718 ent_delay);
719 kick_trng(pdev, ent_delay);
720 ent_delay += 400;
721 }
722
723
724
725
726
727
728
729 ret = instantiate_rng(dev, inst_handles,
730 gen_sk);
731 if (ret == -EAGAIN)
732
733
734
735
736 cpu_relax();
737 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
738 if (ret) {
739 dev_err(dev, "failed to instantiate RNG");
740 goto caam_remove;
741 }
742
743
744
745
746 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
747
748
749 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
750 }
751
752
753
754 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
755 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
756
757
758 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
759 ctrlpriv->era);
760 dev_info(dev, "job rings = %d, qi = %d, dpaa2 = %s\n",
761 ctrlpriv->total_jobrs, ctrlpriv->qi_present,
762 caam_dpaa2 ? "yes" : "no");
763
764#ifdef CONFIG_DEBUG_FS
765 debugfs_create_file("rq_dequeued", S_IRUSR | S_IRGRP | S_IROTH,
766 ctrlpriv->ctl, &perfmon->req_dequeued,
767 &caam_fops_u64_ro);
768 debugfs_create_file("ob_rq_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
769 ctrlpriv->ctl, &perfmon->ob_enc_req,
770 &caam_fops_u64_ro);
771 debugfs_create_file("ib_rq_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
772 ctrlpriv->ctl, &perfmon->ib_dec_req,
773 &caam_fops_u64_ro);
774 debugfs_create_file("ob_bytes_encrypted", S_IRUSR | S_IRGRP | S_IROTH,
775 ctrlpriv->ctl, &perfmon->ob_enc_bytes,
776 &caam_fops_u64_ro);
777 debugfs_create_file("ob_bytes_protected", S_IRUSR | S_IRGRP | S_IROTH,
778 ctrlpriv->ctl, &perfmon->ob_prot_bytes,
779 &caam_fops_u64_ro);
780 debugfs_create_file("ib_bytes_decrypted", S_IRUSR | S_IRGRP | S_IROTH,
781 ctrlpriv->ctl, &perfmon->ib_dec_bytes,
782 &caam_fops_u64_ro);
783 debugfs_create_file("ib_bytes_validated", S_IRUSR | S_IRGRP | S_IROTH,
784 ctrlpriv->ctl, &perfmon->ib_valid_bytes,
785 &caam_fops_u64_ro);
786
787
788 debugfs_create_file("fault_addr", S_IRUSR | S_IRGRP | S_IROTH,
789 ctrlpriv->ctl, &perfmon->faultaddr,
790 &caam_fops_u32_ro);
791 debugfs_create_file("fault_detail", S_IRUSR | S_IRGRP | S_IROTH,
792 ctrlpriv->ctl, &perfmon->faultdetail,
793 &caam_fops_u32_ro);
794 debugfs_create_file("fault_status", S_IRUSR | S_IRGRP | S_IROTH,
795 ctrlpriv->ctl, &perfmon->status,
796 &caam_fops_u32_ro);
797
798
799 ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
800 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
801 ctrlpriv->ctl_kek = debugfs_create_blob("kek",
802 S_IRUSR |
803 S_IRGRP | S_IROTH,
804 ctrlpriv->ctl,
805 &ctrlpriv->ctl_kek_wrap);
806
807 ctrlpriv->ctl_tkek_wrap.data = (__force void *)&ctrlpriv->ctrl->tkek[0];
808 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
809 ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
810 S_IRUSR |
811 S_IRGRP | S_IROTH,
812 ctrlpriv->ctl,
813 &ctrlpriv->ctl_tkek_wrap);
814
815 ctrlpriv->ctl_tdsk_wrap.data = (__force void *)&ctrlpriv->ctrl->tdsk[0];
816 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
817 ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
818 S_IRUSR |
819 S_IRGRP | S_IROTH,
820 ctrlpriv->ctl,
821 &ctrlpriv->ctl_tdsk_wrap);
822#endif
823 return 0;
824
825caam_remove:
826 caam_remove(pdev);
827 return ret;
828
829iounmap_ctrl:
830 iounmap(ctrl);
831disable_caam_emi_slow:
832 if (ctrlpriv->caam_emi_slow)
833 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
834disable_caam_aclk:
835 clk_disable_unprepare(ctrlpriv->caam_aclk);
836disable_caam_mem:
837 if (ctrlpriv->caam_mem)
838 clk_disable_unprepare(ctrlpriv->caam_mem);
839disable_caam_ipg:
840 clk_disable_unprepare(ctrlpriv->caam_ipg);
841 return ret;
842}
843
844static struct platform_driver caam_driver = {
845 .driver = {
846 .name = "caam",
847 .of_match_table = caam_match,
848 },
849 .probe = caam_probe,
850 .remove = caam_remove,
851};
852
853module_platform_driver(caam_driver);
854
855MODULE_LICENSE("GPL");
856MODULE_DESCRIPTION("FSL CAAM request backend");
857MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
858