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13#ifndef __DMA_ST_FDMA_H
14#define __DMA_ST_FDMA_H
15
16#include <linux/dmaengine.h>
17#include <linux/dmapool.h>
18#include <linux/io.h>
19#include <linux/remoteproc/st_slim_rproc.h>
20#include "virt-dma.h"
21
22#define ST_FDMA_NR_DREQS 32
23#define FW_NAME_SIZE 30
24#define DRIVER_NAME "st-fdma"
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32
33struct st_fdma_generic_node {
34 u32 length;
35 u32 sstride;
36 u32 dstride;
37};
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52
53struct st_fdma_hw_node {
54 u32 next;
55 u32 control;
56 u32 nbytes;
57 u32 saddr;
58 u32 daddr;
59 union {
60 struct st_fdma_generic_node generic;
61 };
62} __aligned(32);
63
64
65
66
67#define FDMA_NODE_CTRL_REQ_MAP_MASK GENMASK(4, 0)
68#define FDMA_NODE_CTRL_REQ_MAP_FREE_RUN 0x0
69#define FDMA_NODE_CTRL_REQ_MAP_DREQ(n) ((n)&FDMA_NODE_CTRL_REQ_MAP_MASK)
70#define FDMA_NODE_CTRL_REQ_MAP_EXT FDMA_NODE_CTRL_REQ_MAP_MASK
71#define FDMA_NODE_CTRL_SRC_MASK GENMASK(6, 5)
72#define FDMA_NODE_CTRL_SRC_STATIC BIT(5)
73#define FDMA_NODE_CTRL_SRC_INCR BIT(6)
74#define FDMA_NODE_CTRL_DST_MASK GENMASK(8, 7)
75#define FDMA_NODE_CTRL_DST_STATIC BIT(7)
76#define FDMA_NODE_CTRL_DST_INCR BIT(8)
77#define FDMA_NODE_CTRL_SECURE BIT(15)
78#define FDMA_NODE_CTRL_PAUSE_EON BIT(30)
79#define FDMA_NODE_CTRL_INT_EON BIT(31)
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86
87struct st_fdma_sw_node {
88 dma_addr_t pdesc;
89 struct st_fdma_hw_node *desc;
90};
91
92#define NAME_SZ 10
93
94struct st_fdma_driverdata {
95 u32 id;
96 char name[NAME_SZ];
97};
98
99struct st_fdma_desc {
100 struct virt_dma_desc vdesc;
101 struct st_fdma_chan *fchan;
102 bool iscyclic;
103 unsigned int n_nodes;
104 struct st_fdma_sw_node node[];
105};
106
107enum st_fdma_type {
108 ST_FDMA_TYPE_FREE_RUN,
109 ST_FDMA_TYPE_PACED,
110};
111
112struct st_fdma_cfg {
113 struct device_node *of_node;
114 enum st_fdma_type type;
115 dma_addr_t dev_addr;
116 enum dma_transfer_direction dir;
117 int req_line;
118 long req_ctrl;
119};
120
121struct st_fdma_chan {
122 struct st_fdma_dev *fdev;
123 struct dma_pool *node_pool;
124 struct dma_slave_config scfg;
125 struct st_fdma_cfg cfg;
126
127 int dreq_line;
128
129 struct virt_dma_chan vchan;
130 struct st_fdma_desc *fdesc;
131 enum dma_status status;
132};
133
134struct st_fdma_dev {
135 struct device *dev;
136 const struct st_fdma_driverdata *drvdata;
137 struct dma_device dma_device;
138
139 struct st_slim_rproc *slim_rproc;
140
141 int irq;
142
143 struct st_fdma_chan *chans;
144
145 spinlock_t dreq_lock;
146 unsigned long dreq_mask;
147
148 u32 nr_channels;
149 char fw_name[FW_NAME_SIZE];
150};
151
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153
154#define FDMA_CMD_STA_OFST 0xFC0
155#define FDMA_CMD_SET_OFST 0xFC4
156#define FDMA_CMD_CLR_OFST 0xFC8
157#define FDMA_CMD_MASK_OFST 0xFCC
158#define FDMA_CMD_START(ch) (0x1 << (ch << 1))
159#define FDMA_CMD_PAUSE(ch) (0x2 << (ch << 1))
160#define FDMA_CMD_FLUSH(ch) (0x3 << (ch << 1))
161
162#define FDMA_INT_STA_OFST 0xFD0
163#define FDMA_INT_STA_CH 0x1
164#define FDMA_INT_STA_ERR 0x2
165
166#define FDMA_INT_SET_OFST 0xFD4
167#define FDMA_INT_CLR_OFST 0xFD8
168#define FDMA_INT_MASK_OFST 0xFDC
169
170#define fdma_read(fdev, name) \
171 readl((fdev)->slim_rproc->peri + name)
172
173#define fdma_write(fdev, val, name) \
174 writel((val), (fdev)->slim_rproc->peri + name)
175
176
177#define FDMA_CH_CMD_OFST 0x200
178#define FDMA_CH_CMD_STA_MASK GENMASK(1, 0)
179#define FDMA_CH_CMD_STA_IDLE (0x0)
180#define FDMA_CH_CMD_STA_START (0x1)
181#define FDMA_CH_CMD_STA_RUNNING (0x2)
182#define FDMA_CH_CMD_STA_PAUSED (0x3)
183#define FDMA_CH_CMD_ERR_MASK GENMASK(4, 2)
184#define FDMA_CH_CMD_ERR_INT (0x0 << 2)
185#define FDMA_CH_CMD_ERR_NAND (0x1 << 2)
186#define FDMA_CH_CMD_ERR_MCHI (0x2 << 2)
187#define FDMA_CH_CMD_DATA_MASK GENMASK(31, 5)
188#define fchan_read(fchan, name) \
189 readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
190 + (fchan)->vchan.chan.chan_id * 0x4 \
191 + name)
192
193#define fchan_write(fchan, val, name) \
194 writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
195 + (fchan)->vchan.chan.chan_id * 0x4 \
196 + name)
197
198
199#define FDMA_REQ_CTRL_OFST 0x240
200#define dreq_write(fchan, val, name) \
201 writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
202 + fchan->dreq_line * 0x04 \
203 + name)
204
205#define FDMA_NODE_SZ 128
206#define FDMA_PTRN_OFST 0x800
207#define FDMA_CNTN_OFST 0x808
208#define FDMA_SADDRN_OFST 0x80c
209#define FDMA_DADDRN_OFST 0x810
210#define fnode_read(fchan, name) \
211 readl((fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
212 + (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
213 + name)
214
215#define fnode_write(fchan, val, name) \
216 writel((val), (fchan)->fdev->slim_rproc->mem[ST_SLIM_DMEM].cpu_addr \
217 + (fchan)->vchan.chan.chan_id * FDMA_NODE_SZ \
218 + name)
219
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222
223#define FDMA_REQ_CTRL_NUM_OPS_MASK GENMASK(31, 24)
224#define FDMA_REQ_CTRL_NUM_OPS(n) (FDMA_REQ_CTRL_NUM_OPS_MASK & \
225 ((n) << 24))
226#define FDMA_REQ_CTRL_INITIATOR_MASK BIT(22)
227#define FDMA_REQ_CTRL_INIT0 (0x0 << 22)
228#define FDMA_REQ_CTRL_INIT1 (0x1 << 22)
229#define FDMA_REQ_CTRL_INC_ADDR_ON BIT(21)
230#define FDMA_REQ_CTRL_DATA_SWAP_ON BIT(17)
231#define FDMA_REQ_CTRL_WNR BIT(14)
232#define FDMA_REQ_CTRL_OPCODE_MASK GENMASK(7, 4)
233#define FDMA_REQ_CTRL_OPCODE_LD_ST1 (0x0 << 4)
234#define FDMA_REQ_CTRL_OPCODE_LD_ST2 (0x1 << 4)
235#define FDMA_REQ_CTRL_OPCODE_LD_ST4 (0x2 << 4)
236#define FDMA_REQ_CTRL_OPCODE_LD_ST8 (0x3 << 4)
237#define FDMA_REQ_CTRL_OPCODE_LD_ST16 (0x4 << 4)
238#define FDMA_REQ_CTRL_OPCODE_LD_ST32 (0x5 << 4)
239#define FDMA_REQ_CTRL_OPCODE_LD_ST64 (0x6 << 4)
240#define FDMA_REQ_CTRL_HOLDOFF_MASK GENMASK(2, 0)
241#define FDMA_REQ_CTRL_HOLDOFF(n) ((n) & FDMA_REQ_CTRL_HOLDOFF_MASK)
242
243
244#define FDMA_REQ_CTRL_CFG_MASK (FDMA_REQ_CTRL_HOLDOFF_MASK | \
245 FDMA_REQ_CTRL_DATA_SWAP_ON | \
246 FDMA_REQ_CTRL_INC_ADDR_ON | \
247 FDMA_REQ_CTRL_INITIATOR_MASK)
248
249#endif
250
