LXR linux/drivers/edac/amd8131

   1/*
   2 * amd8131_edac.c, AMD8131 hypertransport chip EDAC kernel module
   3 *
   4 * Copyright (c) 2008 Wind River Systems, Inc.
   5 *
   6 * Authors:     Cao Qingtao <qingtao.cao@windriver.com>
   7 *              Benjamin Walsh <benjamin.walsh@windriver.com>
   8 *              Hu Yongqi <yongqi.hu@windriver.com>
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License version 2 as
  12 * published by the Free Software Foundation.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17 * See the GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22 */
  23
  24#include <linux/module.h>
  25#include <linux/init.h>
  26#include <linux/interrupt.h>
  27#include <linux/io.h>
  28#include <linux/bitops.h>
  29#include <linux/edac.h>
  30#include <linux/pci_ids.h>
  31
  32#include "edac_module.h"
  33#include "amd8131_edac.h"
  34
  35#define AMD8131_EDAC_REVISION   " Ver: 1.0.0"
  36#define AMD8131_EDAC_MOD_STR    "amd8131_edac"
  37
  38/* Wrapper functions for accessing PCI configuration space */
  39static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
  40{
  41        int ret;
  42
  43        ret = pci_read_config_dword(dev, reg, val32);
  44        if (ret != 0)
  45                printk(KERN_ERR AMD8131_EDAC_MOD_STR
  46                        " PCI Access Read Error at 0x%x\n", reg);
  47}
  48
  49static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
  50{
  51        int ret;
  52
  53        ret = pci_write_config_dword(dev, reg, val32);
  54        if (ret != 0)
  55                printk(KERN_ERR AMD8131_EDAC_MOD_STR
  56                        " PCI Access Write Error at 0x%x\n", reg);
  57}
  58
  59static char * const bridge_str[] = {
  60        [NORTH_A] = "NORTH A",
  61        [NORTH_B] = "NORTH B",
  62        [SOUTH_A] = "SOUTH A",
  63        [SOUTH_B] = "SOUTH B",
  64        [NO_BRIDGE] = "NO BRIDGE",
  65};
  66
  67/* Support up to two AMD8131 chipsets on a platform */
  68static struct amd8131_dev_info amd8131_devices[] = {
  69        {
  70        .inst = NORTH_A,
  71        .devfn = DEVFN_PCIX_BRIDGE_NORTH_A,
  72        .ctl_name = "AMD8131_PCIX_NORTH_A",
  73        },
  74        {
  75        .inst = NORTH_B,
  76        .devfn = DEVFN_PCIX_BRIDGE_NORTH_B,
  77        .ctl_name = "AMD8131_PCIX_NORTH_B",
  78        },
  79        {
  80        .inst = SOUTH_A,
  81        .devfn = DEVFN_PCIX_BRIDGE_SOUTH_A,
  82        .ctl_name = "AMD8131_PCIX_SOUTH_A",
  83        },
  84        {
  85        .inst = SOUTH_B,
  86        .devfn = DEVFN_PCIX_BRIDGE_SOUTH_B,
  87        .ctl_name = "AMD8131_PCIX_SOUTH_B",
  88        },
  89        {.inst = NO_BRIDGE,},
  90};
  91
  92static void amd8131_pcix_init(struct amd8131_dev_info *dev_info)
  93{
  94        u32 val32;
  95        struct pci_dev *dev = dev_info->dev;
  96
  97        /* First clear error detection flags */
  98        edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
  99        if (val32 & MEM_LIMIT_MASK)
 100                edac_pci_write_dword(dev, REG_MEM_LIM, val32);
 101
 102        /* Clear Discard Timer Timedout flag */
 103        edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
 104        if (val32 & INT_CTLR_DTS)
 105                edac_pci_write_dword(dev, REG_INT_CTLR, val32);
 106
 107        /* Clear CRC Error flag on link side A */
 108        edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
 109        if (val32 & LNK_CTRL_CRCERR_A)
 110                edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
 111
 112        /* Clear CRC Error flag on link side B */
 113        edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
 114        if (val32 & LNK_CTRL_CRCERR_B)
 115                edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
 116
 117        /*
 118         * Then enable all error detections.
 119         *
 120         * Setup Discard Timer Sync Flood Enable,
 121         * System Error Enable and Parity Error Enable.
 122         */
 123        edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
 124        val32 |= INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE;
 125        edac_pci_write_dword(dev, REG_INT_CTLR, val32);
 126
 127        /* Enable overall SERR Error detection */
 128        edac_pci_read_dword(dev, REG_STS_CMD, &val32);
 129        val32 |= STS_CMD_SERREN;
 130        edac_pci_write_dword(dev, REG_STS_CMD, val32);
 131
 132        /* Setup CRC Flood Enable for link side A */
 133        edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
 134        val32 |= LNK_CTRL_CRCFEN;
 135        edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
 136
 137        /* Setup CRC Flood Enable for link side B */
 138        edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
 139        val32 |= LNK_CTRL_CRCFEN;
 140        edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
 141}
 142
 143static void amd8131_pcix_exit(struct amd8131_dev_info *dev_info)
 144{
 145        u32 val32;
 146        struct pci_dev *dev = dev_info->dev;
 147
 148        /* Disable SERR, PERR and DTSE Error detection */
 149        edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
 150        val32 &= ~(INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE);
 151        edac_pci_write_dword(dev, REG_INT_CTLR, val32);
 152
 153        /* Disable overall System Error detection */
 154        edac_pci_read_dword(dev, REG_STS_CMD, &val32);
 155        val32 &= ~STS_CMD_SERREN;
 156        edac_pci_write_dword(dev, REG_STS_CMD, val32);
 157
 158        /* Disable CRC Sync Flood on link side A */
 159        edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
 160        val32 &= ~LNK_CTRL_CRCFEN;
 161        edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
 162
 163        /* Disable CRC Sync Flood on link side B */
 164        edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
 165        val32 &= ~LNK_CTRL_CRCFEN;
 166        edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
 167}
 168
 169static void amd8131_pcix_check(struct edac_pci_ctl_info *edac_dev)
 170{
 171        struct amd8131_dev_info *dev_info = edac_dev->pvt_info;
 172        struct pci_dev *dev = dev_info->dev;
 173        u32 val32;
 174
 175        /* Check PCI-X Bridge Memory Base-Limit Register for errors */
 176        edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
 177        if (val32 & MEM_LIMIT_MASK) {
 178                printk(KERN_INFO "Error(s) in mem limit register "
 179                        "on %s bridge\n", dev_info->ctl_name);
 180                printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
 181                        "RTA: %d, STA: %d, MDPE: %d\n",
 182                        val32 & MEM_LIMIT_DPE,
 183                        val32 & MEM_LIMIT_RSE,
 184                        val32 & MEM_LIMIT_RMA,
 185                        val32 & MEM_LIMIT_RTA,
 186                        val32 & MEM_LIMIT_STA,
 187                        val32 & MEM_LIMIT_MDPE);
 188
 189                val32 |= MEM_LIMIT_MASK;
 190                edac_pci_write_dword(dev, REG_MEM_LIM, val32);
 191
 192                edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
 193        }
 194
 195        /* Check if Discard Timer timed out */
 196        edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
 197        if (val32 & INT_CTLR_DTS) {
 198                printk(KERN_INFO "Error(s) in interrupt and control register "
 199                        "on %s bridge\n", dev_info->ctl_name);
 200                printk(KERN_INFO "DTS: %d\n", val32 & INT_CTLR_DTS);
 201
 202                val32 |= INT_CTLR_DTS;
 203                edac_pci_write_dword(dev, REG_INT_CTLR, val32);
 204
 205                edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
 206        }
 207
 208        /* Check if CRC error happens on link side A */
 209        edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
 210        if (val32 & LNK_CTRL_CRCERR_A) {
 211                printk(KERN_INFO "Error(s) in link conf and control register "
 212                        "on %s bridge\n", dev_info->ctl_name);
 213                printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_A);
 214
 215                val32 |= LNK_CTRL_CRCERR_A;
 216                edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
 217
 218                edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
 219        }
 220
 221        /* Check if CRC error happens on link side B */
 222        edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
 223        if (val32 & LNK_CTRL_CRCERR_B) {
 224                printk(KERN_INFO "Error(s) in link conf and control register "
 225                        "on %s bridge\n", dev_info->ctl_name);
 226                printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_B);
 227
 228                val32 |= LNK_CTRL_CRCERR_B;
 229                edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
 230
 231                edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
 232        }
 233}
 234
 235static struct amd8131_info amd8131_chipset = {
 236        .err_dev = PCI_DEVICE_ID_AMD_8131_APIC,
 237        .devices = amd8131_devices,
 238        .init = amd8131_pcix_init,
 239        .exit = amd8131_pcix_exit,
 240        .check = amd8131_pcix_check,
 241};
 242
 243/*
 244 * There are 4 PCIX Bridges on ATCA-6101 that share the same PCI Device ID,
 245 * so amd8131_probe() would be called by kernel 4 times, with different
 246 * address of pci_dev for each of them each time.
 247 */
 248static int amd8131_probe(struct pci_dev *dev, const struct pci_device_id *id)
 249{
 250        struct amd8131_dev_info *dev_info;
 251
 252        for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
 253                dev_info++)
 254                if (dev_info->devfn == dev->devfn)
 255                        break;
 256
 257        if (dev_info->inst == NO_BRIDGE) /* should never happen */
 258                return -ENODEV;
 259
 260        /*
 261         * We can't call pci_get_device() as we are used to do because
 262         * there are 4 of them but pci_dev_get() instead.
 263         */
 264        dev_info->dev = pci_dev_get(dev);
 265
 266        if (pci_enable_device(dev_info->dev)) {
 267                pci_dev_put(dev_info->dev);
 268                printk(KERN_ERR "failed to enable:"
 269                        "vendor %x, device %x, devfn %x, name %s\n",
 270                        PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
 271                        dev_info->devfn, dev_info->ctl_name);
 272                return -ENODEV;
 273        }
 274
 275        /*
 276         * we do not allocate extra private structure for
 277         * edac_pci_ctl_info, but make use of existing
 278         * one instead.
 279         */
 280        dev_info->edac_idx = edac_pci_alloc_index();
 281        dev_info->edac_dev = edac_pci_alloc_ctl_info(0, dev_info->ctl_name);
 282        if (!dev_info->edac_dev)
 283                return -ENOMEM;
 284
 285        dev_info->edac_dev->pvt_info = dev_info;
 286        dev_info->edac_dev->dev = &dev_info->dev->dev;
 287        dev_info->edac_dev->mod_name = AMD8131_EDAC_MOD_STR;
 288        dev_info->edac_dev->ctl_name = dev_info->ctl_name;
 289        dev_info->edac_dev->dev_name = dev_name(&dev_info->dev->dev);
 290
 291        if (edac_op_state == EDAC_OPSTATE_POLL)
 292                dev_info->edac_dev->edac_check = amd8131_chipset.check;
 293
 294        if (amd8131_chipset.init)
 295                amd8131_chipset.init(dev_info);
 296
 297        if (edac_pci_add_device(dev_info->edac_dev, dev_info->edac_idx) > 0) {
 298                printk(KERN_ERR "failed edac_pci_add_device() for %s\n",
 299                        dev_info->ctl_name);
 300                edac_pci_free_ctl_info(dev_info->edac_dev);
 301                return -ENODEV;
 302        }
 303
 304        printk(KERN_INFO "added one device on AMD8131 "
 305                "vendor %x, device %x, devfn %x, name %s\n",
 306                PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
 307                dev_info->devfn, dev_info->ctl_name);
 308
 309        return 0;
 310}
 311
 312static void amd8131_remove(struct pci_dev *dev)
 313{
 314        struct amd8131_dev_info *dev_info;
 315
 316        for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
 317                dev_info++)
 318                if (dev_info->devfn == dev->devfn)
 319                        break;
 320
 321        if (dev_info->inst == NO_BRIDGE) /* should never happen */
 322                return;
 323
 324        if (dev_info->edac_dev) {
 325                edac_pci_del_device(dev_info->edac_dev->dev);
 326                edac_pci_free_ctl_info(dev_info->edac_dev);
 327        }
 328
 329        if (amd8131_chipset.exit)
 330                amd8131_chipset.exit(dev_info);
 331
 332        pci_dev_put(dev_info->dev);
 333}
 334
 335static const struct pci_device_id amd8131_edac_pci_tbl[] = {
 336        {
 337        PCI_VEND_DEV(AMD, 8131_BRIDGE),
 338        .subvendor = PCI_ANY_ID,
 339        .subdevice = PCI_ANY_ID,
 340        .class = 0,
 341        .class_mask = 0,
 342        .driver_data = 0,
 343        },
 344        {
 345        0,
 346        }                       /* table is NULL-terminated */
 347};
 348MODULE_DEVICE_TABLE(pci, amd8131_edac_pci_tbl);
 349
 350static struct pci_driver amd8131_edac_driver = {
 351        .name = AMD8131_EDAC_MOD_STR,
 352        .probe = amd8131_probe,
 353        .remove = amd8131_remove,
 354        .id_table = amd8131_edac_pci_tbl,
 355};
 356
 357static int __init amd8131_edac_init(void)
 358{
 359        printk(KERN_INFO "AMD8131 EDAC driver " AMD8131_EDAC_REVISION "\n");
 360        printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
 361
 362        /* Only POLL mode supported so far */
 363        edac_op_state = EDAC_OPSTATE_POLL;
 364
 365        return pci_register_driver(&amd8131_edac_driver);
 366}
 367
 368static void __exit amd8131_edac_exit(void)
 369{
 370        pci_unregister_driver(&amd8131_edac_driver);
 371}
 372
 373module_init(amd8131_edac_init);
 374module_exit(amd8131_edac_exit);
 375
 376MODULE_LICENSE("GPL");
 377MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
 378MODULE_DESCRIPTION("AMD8131 HyperTransport PCI-X Tunnel EDAC kernel module");
 379