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16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/ctype.h>
19#include <linux/edac.h>
20#include <linux/interrupt.h>
21#include <linux/platform_device.h>
22#include <linux/of_platform.h>
23#include <linux/uaccess.h>
24
25#include "edac_module.h"
26
27
28
29#define HB_DDR_ECC_ERR_BASE 0x128
30#define MW_DDR_ECC_ERR_BASE 0x1b4
31
32#define HB_DDR_ECC_OPT 0x00
33#define HB_DDR_ECC_U_ERR_ADDR 0x08
34#define HB_DDR_ECC_U_ERR_STAT 0x0c
35#define HB_DDR_ECC_U_ERR_DATAL 0x10
36#define HB_DDR_ECC_U_ERR_DATAH 0x14
37#define HB_DDR_ECC_C_ERR_ADDR 0x18
38#define HB_DDR_ECC_C_ERR_STAT 0x1c
39#define HB_DDR_ECC_C_ERR_DATAL 0x20
40#define HB_DDR_ECC_C_ERR_DATAH 0x24
41
42#define HB_DDR_ECC_OPT_MODE_MASK 0x3
43#define HB_DDR_ECC_OPT_FWC 0x100
44#define HB_DDR_ECC_OPT_XOR_SHIFT 16
45
46
47
48#define HB_DDR_ECC_INT_BASE 0x180
49#define MW_DDR_ECC_INT_BASE 0x218
50
51#define HB_DDR_ECC_INT_STATUS 0x00
52#define HB_DDR_ECC_INT_ACK 0x04
53
54#define HB_DDR_ECC_INT_STAT_CE 0x8
55#define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
56#define HB_DDR_ECC_INT_STAT_UE 0x20
57#define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
58
59struct hb_mc_drvdata {
60 void __iomem *mc_err_base;
61 void __iomem *mc_int_base;
62};
63
64static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
65{
66 struct mem_ctl_info *mci = dev_id;
67 struct hb_mc_drvdata *drvdata = mci->pvt_info;
68 u32 status, err_addr;
69
70
71 status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
72
73 if (status & HB_DDR_ECC_INT_STAT_UE) {
74 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
75 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
76 err_addr >> PAGE_SHIFT,
77 err_addr & ~PAGE_MASK, 0,
78 0, 0, -1,
79 mci->ctl_name, "");
80 }
81 if (status & HB_DDR_ECC_INT_STAT_CE) {
82 u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
83 syndrome = (syndrome >> 8) & 0xff;
84 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
85 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
86 err_addr >> PAGE_SHIFT,
87 err_addr & ~PAGE_MASK, syndrome,
88 0, 0, -1,
89 mci->ctl_name, "");
90 }
91
92
93 writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
94 return IRQ_HANDLED;
95}
96
97static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
98{
99 struct hb_mc_drvdata *pdata = mci->pvt_info;
100 u32 reg;
101
102 reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
103 reg &= HB_DDR_ECC_OPT_MODE_MASK;
104 reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
105 writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
106}
107
108#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
109
110static ssize_t highbank_mc_inject_ctrl(struct device *dev,
111 struct device_attribute *attr, const char *buf, size_t count)
112{
113 struct mem_ctl_info *mci = to_mci(dev);
114 u8 synd;
115
116 if (kstrtou8(buf, 16, &synd))
117 return -EINVAL;
118
119 highbank_mc_err_inject(mci, synd);
120
121 return count;
122}
123
124static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);
125
126static struct attribute *highbank_dev_attrs[] = {
127 &dev_attr_inject_ctrl.attr,
128 NULL
129};
130
131ATTRIBUTE_GROUPS(highbank_dev);
132
133struct hb_mc_settings {
134 int err_offset;
135 int int_offset;
136};
137
138static struct hb_mc_settings hb_settings = {
139 .err_offset = HB_DDR_ECC_ERR_BASE,
140 .int_offset = HB_DDR_ECC_INT_BASE,
141};
142
143static struct hb_mc_settings mw_settings = {
144 .err_offset = MW_DDR_ECC_ERR_BASE,
145 .int_offset = MW_DDR_ECC_INT_BASE,
146};
147
148static const struct of_device_id hb_ddr_ctrl_of_match[] = {
149 { .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
150 { .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
151 {},
152};
153MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
154
155static int highbank_mc_probe(struct platform_device *pdev)
156{
157 const struct of_device_id *id;
158 const struct hb_mc_settings *settings;
159 struct edac_mc_layer layers[2];
160 struct mem_ctl_info *mci;
161 struct hb_mc_drvdata *drvdata;
162 struct dimm_info *dimm;
163 struct resource *r;
164 void __iomem *base;
165 u32 control;
166 int irq;
167 int res = 0;
168
169 id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
170 if (!id)
171 return -ENODEV;
172
173 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
174 layers[0].size = 1;
175 layers[0].is_virt_csrow = true;
176 layers[1].type = EDAC_MC_LAYER_CHANNEL;
177 layers[1].size = 1;
178 layers[1].is_virt_csrow = false;
179 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
180 sizeof(struct hb_mc_drvdata));
181 if (!mci)
182 return -ENOMEM;
183
184 mci->pdev = &pdev->dev;
185 drvdata = mci->pvt_info;
186 platform_set_drvdata(pdev, mci);
187
188 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
189 return -ENOMEM;
190
191 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
192 if (!r) {
193 dev_err(&pdev->dev, "Unable to get mem resource\n");
194 res = -ENODEV;
195 goto err;
196 }
197
198 if (!devm_request_mem_region(&pdev->dev, r->start,
199 resource_size(r), dev_name(&pdev->dev))) {
200 dev_err(&pdev->dev, "Error while requesting mem region\n");
201 res = -EBUSY;
202 goto err;
203 }
204
205 base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
206 if (!base) {
207 dev_err(&pdev->dev, "Unable to map regs\n");
208 res = -ENOMEM;
209 goto err;
210 }
211
212 settings = id->data;
213 drvdata->mc_err_base = base + settings->err_offset;
214 drvdata->mc_int_base = base + settings->int_offset;
215
216 control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
217 if (!control || (control == 0x2)) {
218 dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
219 res = -ENODEV;
220 goto err;
221 }
222
223 mci->mtype_cap = MEM_FLAG_DDR3;
224 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
225 mci->edac_cap = EDAC_FLAG_SECDED;
226 mci->mod_name = pdev->dev.driver->name;
227 mci->ctl_name = id->compatible;
228 mci->dev_name = dev_name(&pdev->dev);
229 mci->scrub_mode = SCRUB_SW_SRC;
230
231
232 dimm = *mci->dimms;
233 dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
234 dimm->grain = 8;
235 dimm->dtype = DEV_X8;
236 dimm->mtype = MEM_DDR3;
237 dimm->edac_mode = EDAC_SECDED;
238
239 res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups);
240 if (res < 0)
241 goto err;
242
243 irq = platform_get_irq(pdev, 0);
244 res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
245 0, dev_name(&pdev->dev), mci);
246 if (res < 0) {
247 dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
248 goto err2;
249 }
250
251 devres_close_group(&pdev->dev, NULL);
252 return 0;
253err2:
254 edac_mc_del_mc(&pdev->dev);
255err:
256 devres_release_group(&pdev->dev, NULL);
257 edac_mc_free(mci);
258 return res;
259}
260
261static int highbank_mc_remove(struct platform_device *pdev)
262{
263 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
264
265 edac_mc_del_mc(&pdev->dev);
266 edac_mc_free(mci);
267 return 0;
268}
269
270static struct platform_driver highbank_mc_edac_driver = {
271 .probe = highbank_mc_probe,
272 .remove = highbank_mc_remove,
273 .driver = {
274 .name = "hb_mc_edac",
275 .of_match_table = hb_ddr_ctrl_of_match,
276 },
277};
278
279module_platform_driver(highbank_mc_edac_driver);
280
281MODULE_LICENSE("GPL v2");
282MODULE_AUTHOR("Calxeda, Inc.");
283MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");
284
