LXR linux/drivers/gpu/drm/amd/amdgpu/dce

   1/*
   2 * Copyright 2014 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#include <drm/drmP.h>
  24#include "amdgpu.h"
  25#include "amdgpu_pm.h"
  26#include "amdgpu_i2c.h"
  27#include "atom.h"
  28#include "amdgpu_pll.h"
  29#include "amdgpu_connectors.h"
  30#ifdef CONFIG_DRM_AMDGPU_SI
  31#include "dce_v6_0.h"
  32#endif
  33#ifdef CONFIG_DRM_AMDGPU_CIK
  34#include "dce_v8_0.h"
  35#endif
  36#include "dce_v10_0.h"
  37#include "dce_v11_0.h"
  38#include "dce_virtual.h"
  39
  40#define DCE_VIRTUAL_VBLANK_PERIOD 16666666
  41
  42
  43static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
  44static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
  45static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
  46                                              int index);
  47static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
  48                                                        int crtc,
  49                                                        enum amdgpu_interrupt_state state);
  50
  51static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  52{
  53        return 0;
  54}
  55
  56static void dce_virtual_page_flip(struct amdgpu_device *adev,
  57                              int crtc_id, u64 crtc_base, bool async)
  58{
  59        return;
  60}
  61
  62static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  63                                        u32 *vbl, u32 *position)
  64{
  65        *vbl = 0;
  66        *position = 0;
  67
  68        return -EINVAL;
  69}
  70
  71static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
  72                               enum amdgpu_hpd_id hpd)
  73{
  74        return true;
  75}
  76
  77static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
  78                                      enum amdgpu_hpd_id hpd)
  79{
  80        return;
  81}
  82
  83static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
  84{
  85        return 0;
  86}
  87
  88/**
  89 * dce_virtual_bandwidth_update - program display watermarks
  90 *
  91 * @adev: amdgpu_device pointer
  92 *
  93 * Calculate and program the display watermarks and line
  94 * buffer allocation (CIK).
  95 */
  96static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
  97{
  98        return;
  99}
 100
 101static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
 102                                      u16 *green, u16 *blue, uint32_t size,
 103                                      struct drm_modeset_acquire_ctx *ctx)
 104{
 105        return 0;
 106}
 107
 108static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
 109{
 110        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 111
 112        drm_crtc_cleanup(crtc);
 113        kfree(amdgpu_crtc);
 114}
 115
 116static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
 117        .cursor_set2 = NULL,
 118        .cursor_move = NULL,
 119        .gamma_set = dce_virtual_crtc_gamma_set,
 120        .set_config = amdgpu_display_crtc_set_config,
 121        .destroy = dce_virtual_crtc_destroy,
 122        .page_flip_target = amdgpu_display_crtc_page_flip_target,
 123};
 124
 125static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
 126{
 127        struct drm_device *dev = crtc->dev;
 128        struct amdgpu_device *adev = dev->dev_private;
 129        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 130        unsigned type;
 131
 132        if (amdgpu_sriov_vf(adev))
 133                return;
 134
 135        switch (mode) {
 136        case DRM_MODE_DPMS_ON:
 137                amdgpu_crtc->enabled = true;
 138                /* Make sure VBLANK interrupts are still enabled */
 139                type = amdgpu_display_crtc_idx_to_irq_type(adev,
 140                                                amdgpu_crtc->crtc_id);
 141                amdgpu_irq_update(adev, &adev->crtc_irq, type);
 142                drm_crtc_vblank_on(crtc);
 143                break;
 144        case DRM_MODE_DPMS_STANDBY:
 145        case DRM_MODE_DPMS_SUSPEND:
 146        case DRM_MODE_DPMS_OFF:
 147                drm_crtc_vblank_off(crtc);
 148                amdgpu_crtc->enabled = false;
 149                break;
 150        }
 151}
 152
 153
 154static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
 155{
 156        dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 157}
 158
 159static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
 160{
 161        dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 162}
 163
 164static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
 165{
 166        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 167
 168        dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 169        if (crtc->primary->fb) {
 170                int r;
 171                struct amdgpu_framebuffer *amdgpu_fb;
 172                struct amdgpu_bo *abo;
 173
 174                amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
 175                abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
 176                r = amdgpu_bo_reserve(abo, true);
 177                if (unlikely(r))
 178                        DRM_ERROR("failed to reserve abo before unpin\n");
 179                else {
 180                        amdgpu_bo_unpin(abo);
 181                        amdgpu_bo_unreserve(abo);
 182                }
 183        }
 184
 185        amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 186        amdgpu_crtc->encoder = NULL;
 187        amdgpu_crtc->connector = NULL;
 188}
 189
 190static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
 191                                  struct drm_display_mode *mode,
 192                                  struct drm_display_mode *adjusted_mode,
 193                                  int x, int y, struct drm_framebuffer *old_fb)
 194{
 195        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 196
 197        /* update the hw version fpr dpm */
 198        amdgpu_crtc->hw_mode = *adjusted_mode;
 199
 200        return 0;
 201}
 202
 203static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
 204                                     const struct drm_display_mode *mode,
 205                                     struct drm_display_mode *adjusted_mode)
 206{
 207        return true;
 208}
 209
 210
 211static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 212                                  struct drm_framebuffer *old_fb)
 213{
 214        return 0;
 215}
 216
 217static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
 218                                         struct drm_framebuffer *fb,
 219                                         int x, int y, enum mode_set_atomic state)
 220{
 221        return 0;
 222}
 223
 224static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
 225        .dpms = dce_virtual_crtc_dpms,
 226        .mode_fixup = dce_virtual_crtc_mode_fixup,
 227        .mode_set = dce_virtual_crtc_mode_set,
 228        .mode_set_base = dce_virtual_crtc_set_base,
 229        .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
 230        .prepare = dce_virtual_crtc_prepare,
 231        .commit = dce_virtual_crtc_commit,
 232        .disable = dce_virtual_crtc_disable,
 233};
 234
 235static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
 236{
 237        struct amdgpu_crtc *amdgpu_crtc;
 238
 239        amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
 240                              (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 241        if (amdgpu_crtc == NULL)
 242                return -ENOMEM;
 243
 244        drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
 245
 246        drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
 247        amdgpu_crtc->crtc_id = index;
 248        adev->mode_info.crtcs[index] = amdgpu_crtc;
 249
 250        amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 251        amdgpu_crtc->encoder = NULL;
 252        amdgpu_crtc->connector = NULL;
 253        amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
 254        drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
 255
 256        return 0;
 257}
 258
 259static int dce_virtual_early_init(void *handle)
 260{
 261        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 262
 263        dce_virtual_set_display_funcs(adev);
 264        dce_virtual_set_irq_funcs(adev);
 265
 266        adev->mode_info.num_hpd = 1;
 267        adev->mode_info.num_dig = 1;
 268        return 0;
 269}
 270
 271static struct drm_encoder *
 272dce_virtual_encoder(struct drm_connector *connector)
 273{
 274        int enc_id = connector->encoder_ids[0];
 275        struct drm_encoder *encoder;
 276        int i;
 277
 278        for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
 279                if (connector->encoder_ids[i] == 0)
 280                        break;
 281
 282                encoder = drm_encoder_find(connector->dev, NULL, connector->encoder_ids[i]);
 283                if (!encoder)
 284                        continue;
 285
 286                if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
 287                        return encoder;
 288        }
 289
 290        /* pick the first one */
 291        if (enc_id)
 292                return drm_encoder_find(connector->dev, NULL, enc_id);
 293        return NULL;
 294}
 295
 296static int dce_virtual_get_modes(struct drm_connector *connector)
 297{
 298        struct drm_device *dev = connector->dev;
 299        struct drm_display_mode *mode = NULL;
 300        unsigned i;
 301        static const struct mode_size {
 302                int w;
 303                int h;
 304        } common_modes[17] = {
 305                { 640,  480},
 306                { 720,  480},
 307                { 800,  600},
 308                { 848,  480},
 309                {1024,  768},
 310                {1152,  768},
 311                {1280,  720},
 312                {1280,  800},
 313                {1280,  854},
 314                {1280,  960},
 315                {1280, 1024},
 316                {1440,  900},
 317                {1400, 1050},
 318                {1680, 1050},
 319                {1600, 1200},
 320                {1920, 1080},
 321                {1920, 1200}
 322        };
 323
 324        for (i = 0; i < 17; i++) {
 325                mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 326                drm_mode_probed_add(connector, mode);
 327        }
 328
 329        return 0;
 330}
 331
 332static int dce_virtual_mode_valid(struct drm_connector *connector,
 333                                  struct drm_display_mode *mode)
 334{
 335        return MODE_OK;
 336}
 337
 338static int
 339dce_virtual_dpms(struct drm_connector *connector, int mode)
 340{
 341        return 0;
 342}
 343
 344static int
 345dce_virtual_set_property(struct drm_connector *connector,
 346                         struct drm_property *property,
 347                         uint64_t val)
 348{
 349        return 0;
 350}
 351
 352static void dce_virtual_destroy(struct drm_connector *connector)
 353{
 354        drm_connector_unregister(connector);
 355        drm_connector_cleanup(connector);
 356        kfree(connector);
 357}
 358
 359static void dce_virtual_force(struct drm_connector *connector)
 360{
 361        return;
 362}
 363
 364static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
 365        .get_modes = dce_virtual_get_modes,
 366        .mode_valid = dce_virtual_mode_valid,
 367        .best_encoder = dce_virtual_encoder,
 368};
 369
 370static const struct drm_connector_funcs dce_virtual_connector_funcs = {
 371        .dpms = dce_virtual_dpms,
 372        .fill_modes = drm_helper_probe_single_connector_modes,
 373        .set_property = dce_virtual_set_property,
 374        .destroy = dce_virtual_destroy,
 375        .force = dce_virtual_force,
 376};
 377
 378static int dce_virtual_sw_init(void *handle)
 379{
 380        int r, i;
 381        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 382
 383        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq);
 384        if (r)
 385                return r;
 386
 387        adev->ddev->max_vblank_count = 0;
 388
 389        adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
 390
 391        adev->ddev->mode_config.max_width = 16384;
 392        adev->ddev->mode_config.max_height = 16384;
 393
 394        adev->ddev->mode_config.preferred_depth = 24;
 395        adev->ddev->mode_config.prefer_shadow = 1;
 396
 397        adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
 398
 399        r = amdgpu_display_modeset_create_props(adev);
 400        if (r)
 401                return r;
 402
 403        adev->ddev->mode_config.max_width = 16384;
 404        adev->ddev->mode_config.max_height = 16384;
 405
 406        /* allocate crtcs, encoders, connectors */
 407        for (i = 0; i < adev->mode_info.num_crtc; i++) {
 408                r = dce_virtual_crtc_init(adev, i);
 409                if (r)
 410                        return r;
 411                r = dce_virtual_connector_encoder_init(adev, i);
 412                if (r)
 413                        return r;
 414        }
 415
 416        drm_kms_helper_poll_init(adev->ddev);
 417
 418        adev->mode_info.mode_config_initialized = true;
 419        return 0;
 420}
 421
 422static int dce_virtual_sw_fini(void *handle)
 423{
 424        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 425
 426        kfree(adev->mode_info.bios_hardcoded_edid);
 427
 428        drm_kms_helper_poll_fini(adev->ddev);
 429
 430        drm_mode_config_cleanup(adev->ddev);
 431        /* clear crtcs pointer to avoid dce irq finish routine access freed data */
 432        memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * AMDGPU_MAX_CRTCS);
 433        adev->mode_info.mode_config_initialized = false;
 434        return 0;
 435}
 436
 437static int dce_virtual_hw_init(void *handle)
 438{
 439        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 440
 441        switch (adev->asic_type) {
 442#ifdef CONFIG_DRM_AMDGPU_SI
 443        case CHIP_TAHITI:
 444        case CHIP_PITCAIRN:
 445        case CHIP_VERDE:
 446        case CHIP_OLAND:
 447                dce_v6_0_disable_dce(adev);
 448                break;
 449#endif
 450#ifdef CONFIG_DRM_AMDGPU_CIK
 451        case CHIP_BONAIRE:
 452        case CHIP_HAWAII:
 453        case CHIP_KAVERI:
 454        case CHIP_KABINI:
 455        case CHIP_MULLINS:
 456                dce_v8_0_disable_dce(adev);
 457                break;
 458#endif
 459        case CHIP_FIJI:
 460        case CHIP_TONGA:
 461                dce_v10_0_disable_dce(adev);
 462                break;
 463        case CHIP_CARRIZO:
 464        case CHIP_STONEY:
 465        case CHIP_POLARIS11:
 466        case CHIP_POLARIS10:
 467                dce_v11_0_disable_dce(adev);
 468                break;
 469        case CHIP_TOPAZ:
 470#ifdef CONFIG_DRM_AMDGPU_SI
 471        case CHIP_HAINAN:
 472#endif
 473                /* no DCE */
 474                break;
 475        case CHIP_VEGA10:
 476        case CHIP_VEGA12:
 477                break;
 478        default:
 479                DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
 480        }
 481        return 0;
 482}
 483
 484static int dce_virtual_hw_fini(void *handle)
 485{
 486        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 487        int i = 0;
 488
 489        for (i = 0; i<adev->mode_info.num_crtc; i++)
 490                if (adev->mode_info.crtcs[i])
 491                        dce_virtual_set_crtc_vblank_interrupt_state(adev, i, AMDGPU_IRQ_STATE_DISABLE);
 492
 493        return 0;
 494}
 495
 496static int dce_virtual_suspend(void *handle)
 497{
 498        return dce_virtual_hw_fini(handle);
 499}
 500
 501static int dce_virtual_resume(void *handle)
 502{
 503        return dce_virtual_hw_init(handle);
 504}
 505
 506static bool dce_virtual_is_idle(void *handle)
 507{
 508        return true;
 509}
 510
 511static int dce_virtual_wait_for_idle(void *handle)
 512{
 513        return 0;
 514}
 515
 516static int dce_virtual_soft_reset(void *handle)
 517{
 518        return 0;
 519}
 520
 521static int dce_virtual_set_clockgating_state(void *handle,
 522                                          enum amd_clockgating_state state)
 523{
 524        return 0;
 525}
 526
 527static int dce_virtual_set_powergating_state(void *handle,
 528                                          enum amd_powergating_state state)
 529{
 530        return 0;
 531}
 532
 533static const struct amd_ip_funcs dce_virtual_ip_funcs = {
 534        .name = "dce_virtual",
 535        .early_init = dce_virtual_early_init,
 536        .late_init = NULL,
 537        .sw_init = dce_virtual_sw_init,
 538        .sw_fini = dce_virtual_sw_fini,
 539        .hw_init = dce_virtual_hw_init,
 540        .hw_fini = dce_virtual_hw_fini,
 541        .suspend = dce_virtual_suspend,
 542        .resume = dce_virtual_resume,
 543        .is_idle = dce_virtual_is_idle,
 544        .wait_for_idle = dce_virtual_wait_for_idle,
 545        .soft_reset = dce_virtual_soft_reset,
 546        .set_clockgating_state = dce_virtual_set_clockgating_state,
 547        .set_powergating_state = dce_virtual_set_powergating_state,
 548};
 549
 550/* these are handled by the primary encoders */
 551static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
 552{
 553        return;
 554}
 555
 556static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
 557{
 558        return;
 559}
 560
 561static void
 562dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
 563                             struct drm_display_mode *mode,
 564                             struct drm_display_mode *adjusted_mode)
 565{
 566        return;
 567}
 568
 569static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
 570{
 571        return;
 572}
 573
 574static void
 575dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
 576{
 577        return;
 578}
 579
 580static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
 581                                    const struct drm_display_mode *mode,
 582                                    struct drm_display_mode *adjusted_mode)
 583{
 584        return true;
 585}
 586
 587static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
 588        .dpms = dce_virtual_encoder_dpms,
 589        .mode_fixup = dce_virtual_encoder_mode_fixup,
 590        .prepare = dce_virtual_encoder_prepare,
 591        .mode_set = dce_virtual_encoder_mode_set,
 592        .commit = dce_virtual_encoder_commit,
 593        .disable = dce_virtual_encoder_disable,
 594};
 595
 596static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
 597{
 598        drm_encoder_cleanup(encoder);
 599        kfree(encoder);
 600}
 601
 602static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
 603        .destroy = dce_virtual_encoder_destroy,
 604};
 605
 606static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
 607                                              int index)
 608{
 609        struct drm_encoder *encoder;
 610        struct drm_connector *connector;
 611
 612        /* add a new encoder */
 613        encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
 614        if (!encoder)
 615                return -ENOMEM;
 616        encoder->possible_crtcs = 1 << index;
 617        drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs,
 618                         DRM_MODE_ENCODER_VIRTUAL, NULL);
 619        drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
 620
 621        connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
 622        if (!connector) {
 623                kfree(encoder);
 624                return -ENOMEM;
 625        }
 626
 627        /* add a new connector */
 628        drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs,
 629                           DRM_MODE_CONNECTOR_VIRTUAL);
 630        drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
 631        connector->display_info.subpixel_order = SubPixelHorizontalRGB;
 632        connector->interlace_allowed = false;
 633        connector->doublescan_allowed = false;
 634        drm_connector_register(connector);
 635
 636        /* link them */
 637        drm_mode_connector_attach_encoder(connector, encoder);
 638
 639        return 0;
 640}
 641
 642static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
 643        .bandwidth_update = &dce_virtual_bandwidth_update,
 644        .vblank_get_counter = &dce_virtual_vblank_get_counter,
 645        .backlight_set_level = NULL,
 646        .backlight_get_level = NULL,
 647        .hpd_sense = &dce_virtual_hpd_sense,
 648        .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
 649        .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
 650        .page_flip = &dce_virtual_page_flip,
 651        .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
 652        .add_encoder = NULL,
 653        .add_connector = NULL,
 654};
 655
 656static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
 657{
 658        if (adev->mode_info.funcs == NULL)
 659                adev->mode_info.funcs = &dce_virtual_display_funcs;
 660}
 661
 662static int dce_virtual_pageflip(struct amdgpu_device *adev,
 663                                unsigned crtc_id)
 664{
 665        unsigned long flags;
 666        struct amdgpu_crtc *amdgpu_crtc;
 667        struct amdgpu_flip_work *works;
 668
 669        amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 670
 671        if (crtc_id >= adev->mode_info.num_crtc) {
 672                DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
 673                return -EINVAL;
 674        }
 675
 676        /* IRQ could occur when in initial stage */
 677        if (amdgpu_crtc == NULL)
 678                return 0;
 679
 680        spin_lock_irqsave(&adev->ddev->event_lock, flags);
 681        works = amdgpu_crtc->pflip_works;
 682        if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
 683                DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
 684                        "AMDGPU_FLIP_SUBMITTED(%d)\n",
 685                        amdgpu_crtc->pflip_status,
 686                        AMDGPU_FLIP_SUBMITTED);
 687                spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 688                return 0;
 689        }
 690
 691        /* page flip completed. clean up */
 692        amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 693        amdgpu_crtc->pflip_works = NULL;
 694
 695        /* wakeup usersapce */
 696        if (works->event)
 697                drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
 698
 699        spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 700
 701        drm_crtc_vblank_put(&amdgpu_crtc->base);
 702        schedule_work(&works->unpin_work);
 703
 704        return 0;
 705}
 706
 707static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
 708{
 709        struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
 710                                                       struct amdgpu_crtc, vblank_timer);
 711        struct drm_device *ddev = amdgpu_crtc->base.dev;
 712        struct amdgpu_device *adev = ddev->dev_private;
 713
 714        drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
 715        dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
 716        hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
 717                      HRTIMER_MODE_REL);
 718
 719        return HRTIMER_NORESTART;
 720}
 721
 722static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
 723                                                        int crtc,
 724                                                        enum amdgpu_interrupt_state state)
 725{
 726        if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
 727                DRM_DEBUG("invalid crtc %d\n", crtc);
 728                return;
 729        }
 730
 731        if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 732                DRM_DEBUG("Enable software vsync timer\n");
 733                hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer,
 734                             CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 735                hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer,
 736                                    DCE_VIRTUAL_VBLANK_PERIOD);
 737                adev->mode_info.crtcs[crtc]->vblank_timer.function =
 738                        dce_virtual_vblank_timer_handle;
 739                hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer,
 740                              DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
 741        } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
 742                DRM_DEBUG("Disable software vsync timer\n");
 743                hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer);
 744        }
 745
 746        adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
 747        DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
 748}
 749
 750
 751static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
 752                                          struct amdgpu_irq_src *source,
 753                                          unsigned type,
 754                                          enum amdgpu_interrupt_state state)
 755{
 756        if (type > AMDGPU_CRTC_IRQ_VBLANK6)
 757                return -EINVAL;
 758
 759        dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
 760
 761        return 0;
 762}
 763
 764static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
 765        .set = dce_virtual_set_crtc_irq_state,
 766        .process = NULL,
 767};
 768
 769static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
 770{
 771        adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VBLANK6 + 1;
 772        adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
 773}
 774
 775const struct amdgpu_ip_block_version dce_virtual_ip_block =
 776{
 777        .type = AMD_IP_BLOCK_TYPE_DCE,
 778        .major = 1,
 779        .minor = 0,
 780        .rev = 0,
 781        .funcs = &dce_virtual_ip_funcs,
 782};
 783