LXR linux/drivers/gpu/drm/amd/display/dc/dc_dp

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef DC_DP_TYPES_H
  27#define DC_DP_TYPES_H
  28
  29enum dc_lane_count {
  30        LANE_COUNT_UNKNOWN = 0,
  31        LANE_COUNT_ONE = 1,
  32        LANE_COUNT_TWO = 2,
  33        LANE_COUNT_FOUR = 4,
  34        LANE_COUNT_EIGHT = 8,
  35        LANE_COUNT_DP_MAX = LANE_COUNT_FOUR
  36};
  37
  38/* This is actually a reference clock (27MHz) multiplier
  39 * 162MBps bandwidth for 1.62GHz like rate,
  40 * 270MBps for 2.70GHz,
  41 * 324MBps for 3.24Ghz,
  42 * 540MBps for 5.40GHz
  43 * 810MBps for 8.10GHz
  44 */
  45enum dc_link_rate {
  46        LINK_RATE_UNKNOWN = 0,
  47        LINK_RATE_LOW = 0x06,
  48        LINK_RATE_HIGH = 0x0A,
  49        LINK_RATE_RBR2 = 0x0C,
  50        LINK_RATE_HIGH2 = 0x14,
  51        LINK_RATE_HIGH3 = 0x1E
  52};
  53
  54enum dc_link_spread {
  55        LINK_SPREAD_DISABLED = 0x00,
  56        /* 0.5 % downspread 30 kHz */
  57        LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10,
  58        /* 0.5 % downspread 33 kHz */
  59        LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11
  60};
  61
  62enum dc_voltage_swing {
  63        VOLTAGE_SWING_LEVEL0 = 0,       /* direct HW translation! */
  64        VOLTAGE_SWING_LEVEL1,
  65        VOLTAGE_SWING_LEVEL2,
  66        VOLTAGE_SWING_LEVEL3,
  67        VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3
  68};
  69
  70enum dc_pre_emphasis {
  71        PRE_EMPHASIS_DISABLED = 0,      /* direct HW translation! */
  72        PRE_EMPHASIS_LEVEL1,
  73        PRE_EMPHASIS_LEVEL2,
  74        PRE_EMPHASIS_LEVEL3,
  75        PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3
  76};
  77/* Post Cursor 2 is optional for transmitter
  78 * and it applies only to the main link operating at HBR2
  79 */
  80enum dc_post_cursor2 {
  81        POST_CURSOR2_DISABLED = 0,      /* direct HW translation! */
  82        POST_CURSOR2_LEVEL1,
  83        POST_CURSOR2_LEVEL2,
  84        POST_CURSOR2_LEVEL3,
  85        POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3,
  86};
  87
  88struct dc_link_settings {
  89        enum dc_lane_count lane_count;
  90        enum dc_link_rate link_rate;
  91        enum dc_link_spread link_spread;
  92};
  93
  94struct dc_lane_settings {
  95        enum dc_voltage_swing VOLTAGE_SWING;
  96        enum dc_pre_emphasis PRE_EMPHASIS;
  97        enum dc_post_cursor2 POST_CURSOR2;
  98};
  99
 100struct dc_link_training_settings {
 101        struct dc_link_settings link;
 102        struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
 103};
 104
 105
 106union dpcd_rev {
 107        struct {
 108                uint8_t MINOR:4;
 109                uint8_t MAJOR:4;
 110        } bits;
 111        uint8_t raw;
 112};
 113
 114union max_lane_count {
 115        struct {
 116                uint8_t MAX_LANE_COUNT:5;
 117                uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
 118                uint8_t TPS3_SUPPORTED:1;
 119                uint8_t ENHANCED_FRAME_CAP:1;
 120        } bits;
 121        uint8_t raw;
 122};
 123
 124union max_down_spread {
 125        struct {
 126                uint8_t MAX_DOWN_SPREAD:1;
 127                uint8_t RESERVED:5;
 128                uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1;
 129                uint8_t TPS4_SUPPORTED:1;
 130        } bits;
 131        uint8_t raw;
 132};
 133
 134union mstm_cap {
 135        struct {
 136                uint8_t MST_CAP:1;
 137                uint8_t RESERVED:7;
 138        } bits;
 139        uint8_t raw;
 140};
 141
 142union lane_count_set {
 143        struct {
 144                uint8_t LANE_COUNT_SET:5;
 145                uint8_t POST_LT_ADJ_REQ_GRANTED:1;
 146                uint8_t RESERVED:1;
 147                uint8_t ENHANCED_FRAMING:1;
 148        } bits;
 149        uint8_t raw;
 150};
 151
 152union lane_status {
 153        struct {
 154                uint8_t CR_DONE_0:1;
 155                uint8_t CHANNEL_EQ_DONE_0:1;
 156                uint8_t SYMBOL_LOCKED_0:1;
 157                uint8_t RESERVED0:1;
 158                uint8_t CR_DONE_1:1;
 159                uint8_t CHANNEL_EQ_DONE_1:1;
 160                uint8_t SYMBOL_LOCKED_1:1;
 161                uint8_t RESERVED_1:1;
 162        } bits;
 163        uint8_t raw;
 164};
 165
 166union device_service_irq {
 167        struct {
 168                uint8_t REMOTE_CONTROL_CMD_PENDING:1;
 169                uint8_t AUTOMATED_TEST:1;
 170                uint8_t CP_IRQ:1;
 171                uint8_t MCCS_IRQ:1;
 172                uint8_t DOWN_REP_MSG_RDY:1;
 173                uint8_t UP_REQ_MSG_RDY:1;
 174                uint8_t SINK_SPECIFIC:1;
 175                uint8_t reserved:1;
 176        } bits;
 177        uint8_t raw;
 178};
 179
 180union sink_count {
 181        struct {
 182                uint8_t SINK_COUNT:6;
 183                uint8_t CPREADY:1;
 184                uint8_t RESERVED:1;
 185        } bits;
 186        uint8_t raw;
 187};
 188
 189union lane_align_status_updated {
 190        struct {
 191                uint8_t INTERLANE_ALIGN_DONE:1;
 192                uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1;
 193                uint8_t RESERVED:4;
 194                uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1;
 195                uint8_t LINK_STATUS_UPDATED:1;
 196        } bits;
 197        uint8_t raw;
 198};
 199
 200union lane_adjust {
 201        struct {
 202                uint8_t VOLTAGE_SWING_LANE:2;
 203                uint8_t PRE_EMPHASIS_LANE:2;
 204                uint8_t RESERVED:4;
 205        } bits;
 206        uint8_t raw;
 207};
 208
 209union dpcd_training_pattern {
 210        struct {
 211                uint8_t TRAINING_PATTERN_SET:4;
 212                uint8_t RECOVERED_CLOCK_OUT_EN:1;
 213                uint8_t SCRAMBLING_DISABLE:1;
 214                uint8_t SYMBOL_ERROR_COUNT_SEL:2;
 215        } v1_4;
 216        struct {
 217                uint8_t TRAINING_PATTERN_SET:2;
 218                uint8_t LINK_QUAL_PATTERN_SET:2;
 219                uint8_t RESERVED:4;
 220        } v1_3;
 221        uint8_t raw;
 222};
 223
 224/* Training Lane is used to configure downstream DP device's voltage swing
 225and pre-emphasis levels*/
 226/* The DPCD addresses are from 0x103 to 0x106*/
 227union dpcd_training_lane {
 228        struct {
 229                uint8_t VOLTAGE_SWING_SET:2;
 230                uint8_t MAX_SWING_REACHED:1;
 231                uint8_t PRE_EMPHASIS_SET:2;
 232                uint8_t MAX_PRE_EMPHASIS_REACHED:1;
 233                uint8_t RESERVED:2;
 234        } bits;
 235        uint8_t raw;
 236};
 237
 238/* TMDS-converter related */
 239union dwnstream_port_caps_byte0 {
 240        struct {
 241                uint8_t DWN_STRM_PORTX_TYPE:3;
 242                uint8_t DWN_STRM_PORTX_HPD:1;
 243                uint8_t RESERVERD:4;
 244        } bits;
 245        uint8_t raw;
 246};
 247
 248/* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/
 249enum dpcd_downstream_port_detailed_type {
 250        DOWN_STREAM_DETAILED_DP = 0,
 251        DOWN_STREAM_DETAILED_VGA,
 252        DOWN_STREAM_DETAILED_DVI,
 253        DOWN_STREAM_DETAILED_HDMI,
 254        DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/
 255        DOWN_STREAM_DETAILED_DP_PLUS_PLUS
 256};
 257
 258union dwnstream_port_caps_byte2 {
 259        struct {
 260                uint8_t MAX_BITS_PER_COLOR_COMPONENT:2;
 261                uint8_t RESERVED:6;
 262        } bits;
 263        uint8_t raw;
 264};
 265
 266union dp_downstream_port_present {
 267        uint8_t byte;
 268        struct {
 269                uint8_t PORT_PRESENT:1;
 270                uint8_t PORT_TYPE:2;
 271                uint8_t FMT_CONVERSION:1;
 272                uint8_t DETAILED_CAPS:1;
 273                uint8_t RESERVED:3;
 274        } fields;
 275};
 276
 277union dwnstream_port_caps_byte3_dvi {
 278        struct {
 279                uint8_t RESERVED1:1;
 280                uint8_t DUAL_LINK:1;
 281                uint8_t HIGH_COLOR_DEPTH:1;
 282                uint8_t RESERVED2:5;
 283        } bits;
 284        uint8_t raw;
 285};
 286
 287union dwnstream_port_caps_byte3_hdmi {
 288        struct {
 289                uint8_t FRAME_SEQ_TO_FRAME_PACK:1;
 290                uint8_t YCrCr422_PASS_THROUGH:1;
 291                uint8_t YCrCr420_PASS_THROUGH:1;
 292                uint8_t YCrCr422_CONVERSION:1;
 293                uint8_t YCrCr420_CONVERSION:1;
 294                uint8_t RESERVED:3;
 295        } bits;
 296        uint8_t raw;
 297};
 298
 299/*4-byte structure for detailed capabilities of a down-stream port
 300(DP-to-TMDS converter).*/
 301union dwnstream_portxcaps {
 302        struct {
 303                union dwnstream_port_caps_byte0 byte0;
 304                unsigned char max_TMDS_clock;   //byte1
 305                union dwnstream_port_caps_byte2 byte2;
 306
 307                union {
 308                        union dwnstream_port_caps_byte3_dvi byteDVI;
 309                        union dwnstream_port_caps_byte3_hdmi byteHDMI;
 310                } byte3;
 311        } bytes;
 312
 313        unsigned char raw[4];
 314};
 315
 316union downstream_port {
 317        struct {
 318                unsigned char   present:1;
 319                unsigned char   type:2;
 320                unsigned char   format_conv:1;
 321                unsigned char   detailed_caps:1;
 322                unsigned char   reserved:3;
 323        } bits;
 324        unsigned char raw;
 325};
 326
 327
 328union sink_status {
 329        struct {
 330                uint8_t RX_PORT0_STATUS:1;
 331                uint8_t RX_PORT1_STATUS:1;
 332                uint8_t RESERVED:6;
 333        } bits;
 334        uint8_t raw;
 335};
 336
 337/*6-byte structure corresponding to 6 registers (200h-205h)
 338read during handling of HPD-IRQ*/
 339union hpd_irq_data {
 340        struct {
 341                union sink_count sink_cnt;/* 200h */
 342                union device_service_irq device_service_irq;/* 201h */
 343                union lane_status lane01_status;/* 202h */
 344                union lane_status lane23_status;/* 203h */
 345                union lane_align_status_updated lane_status_updated;/* 204h */
 346                union sink_status sink_status;
 347        } bytes;
 348        uint8_t raw[6];
 349};
 350
 351union down_stream_port_count {
 352        struct {
 353                uint8_t DOWN_STR_PORT_COUNT:4;
 354                uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/
 355                /*Bit 6 = MSA_TIMING_PAR_IGNORED
 356                0 = Sink device requires the MSA timing parameters
 357                1 = Sink device is capable of rendering incoming video
 358                 stream without MSA timing parameters*/
 359                uint8_t IGNORE_MSA_TIMING_PARAM:1;
 360                /*Bit 7 = OUI Support
 361                0 = OUI not supported
 362                1 = OUI supported
 363                (OUI and Device Identification mandatory for DP 1.2)*/
 364                uint8_t OUI_SUPPORT:1;
 365        } bits;
 366        uint8_t raw;
 367};
 368
 369union down_spread_ctrl {
 370        struct {
 371                uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/
 372        /* Bits 4 = SPREAD_AMP. Spreading amplitude
 373        0 = Main link signal is not downspread
 374        1 = Main link signal is downspread <= 0.5%
 375        with frequency in the range of 30kHz ~ 33kHz*/
 376                uint8_t SPREAD_AMP:1;
 377                uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/
 378        /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN
 379        0 = Source device will send valid data for the MSA Timing Params
 380        1 = Source device may send invalid data for these MSA Timing Params*/
 381                uint8_t IGNORE_MSA_TIMING_PARAM:1;
 382        } bits;
 383        uint8_t raw;
 384};
 385
 386union dpcd_edp_config {
 387        struct {
 388                uint8_t PANEL_MODE_EDP:1;
 389                uint8_t FRAMING_CHANGE_ENABLE:1;
 390                uint8_t RESERVED:5;
 391                uint8_t PANEL_SELF_TEST_ENABLE:1;
 392        } bits;
 393        uint8_t raw;
 394};
 395
 396struct dp_device_vendor_id {
 397        uint8_t ieee_oui[3];/*24-bit IEEE OUI*/
 398        uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/
 399};
 400
 401struct dp_sink_hw_fw_revision {
 402        uint8_t ieee_hw_rev;
 403        uint8_t ieee_fw_rev[2];
 404};
 405
 406/*DPCD register of DP receiver capability field bits-*/
 407union edp_configuration_cap {
 408        struct {
 409                uint8_t ALT_SCRAMBLER_RESET:1;
 410                uint8_t FRAMING_CHANGE:1;
 411                uint8_t RESERVED:1;
 412                uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1;
 413                uint8_t RESERVED2:4;
 414        } bits;
 415        uint8_t raw;
 416};
 417
 418union training_aux_rd_interval {
 419        struct {
 420                uint8_t TRAINIG_AUX_RD_INTERVAL:7;
 421                uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1;
 422        } bits;
 423        uint8_t raw;
 424};
 425
 426/* Automated test structures */
 427union test_request {
 428        struct {
 429        uint8_t LINK_TRAINING         :1;
 430        uint8_t LINK_TEST_PATTRN      :1;
 431        uint8_t EDID_REAT             :1;
 432        uint8_t PHY_TEST_PATTERN      :1;
 433        uint8_t AUDIO_TEST_PATTERN    :1;
 434        uint8_t RESERVED              :1;
 435        uint8_t TEST_STEREO_3D        :1;
 436        } bits;
 437        uint8_t raw;
 438};
 439
 440union test_response {
 441        struct {
 442                uint8_t ACK         :1;
 443                uint8_t NO_ACK      :1;
 444                uint8_t RESERVED    :6;
 445        } bits;
 446        uint8_t raw;
 447};
 448
 449union phy_test_pattern {
 450        struct {
 451                /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1
 452                 * and 3 bits for DP1.2.
 453                 */
 454                uint8_t PATTERN     :3;
 455                /* BY speci, bit7:2 is 0 for DP1.1. */
 456                uint8_t RESERVED    :5;
 457        } bits;
 458        uint8_t raw;
 459};
 460
 461/* States of Compliance Test Specification (CTS DP1.2). */
 462union compliance_test_state {
 463        struct {
 464                unsigned char STEREO_3D_RUNNING        : 1;
 465                unsigned char RESERVED                 : 7;
 466        } bits;
 467        unsigned char raw;
 468};
 469
 470union link_test_pattern {
 471        struct {
 472                /* dpcd_link_test_patterns */
 473                unsigned char PATTERN :2;
 474                unsigned char RESERVED:6;
 475        } bits;
 476        unsigned char raw;
 477};
 478
 479union test_misc {
 480        struct dpcd_test_misc_bits {
 481                unsigned char SYNC_CLOCK :1;
 482                /* dpcd_test_color_format */
 483                unsigned char CLR_FORMAT :2;
 484                /* dpcd_test_dyn_range */
 485                unsigned char DYN_RANGE  :1;
 486                unsigned char YCBCR      :1;
 487                /* dpcd_test_bit_depth */
 488                unsigned char BPC        :3;
 489        } bits;
 490        unsigned char raw;
 491};
 492
 493#endif /* DC_DP_TYPES_H */
 494