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24#ifndef PP_ATOMVOLTAGECTRL_H
25#define PP_ATOMVOLTAGECTRL_H
26
27#include "hwmgr.h"
28
29#define MEM_TYPE_GDDR5 0x50
30#define MEM_TYPE_GDDR4 0x40
31#define MEM_TYPE_GDDR3 0x30
32#define MEM_TYPE_DDR2 0x20
33#define MEM_TYPE_GDDR1 0x10
34#define MEM_TYPE_DDR3 0xb0
35#define MEM_TYPE_MASK 0xF0
36
37
38
39#define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE 0x80
40#define PP_ATOM_POWER_BUDGET_SHOW_WARNING 0x40
41#define PP_ATOM_POWER_BUDGET_SHOW_WAIVER 0x20
42#define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR 0x0F
43
44
45#define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32
46
47struct pp_atomctrl_clock_dividers {
48 uint32_t pll_post_divider;
49 uint32_t pll_feedback_divider;
50 uint32_t pll_ref_divider;
51 bool enable_post_divider;
52};
53
54typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers;
55
56union pp_atomctrl_tcipll_fb_divider {
57 struct {
58 uint32_t ul_fb_div_frac : 14;
59 uint32_t ul_fb_div : 12;
60 uint32_t un_used : 6;
61 };
62 uint32_t ul_fb_divider;
63};
64
65typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider;
66
67struct pp_atomctrl_clock_dividers_rv730 {
68 uint32_t pll_post_divider;
69 pp_atomctrl_tcipll_fb_divider mpll_feedback_divider;
70 uint32_t pll_ref_divider;
71 bool enable_post_divider;
72 bool enable_dithen;
73 uint32_t vco_mode;
74};
75typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730;
76
77
78struct pp_atomctrl_clock_dividers_kong {
79 uint32_t pll_post_divider;
80 uint32_t real_clock;
81};
82typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong;
83
84struct pp_atomctrl_clock_dividers_ci {
85 uint32_t pll_post_divider;
86 uint32_t real_clock;
87 pp_atomctrl_tcipll_fb_divider ul_fb_div;
88 uint8_t uc_pll_ref_div;
89 uint8_t uc_pll_post_div;
90 uint8_t uc_pll_cntl_flag;
91};
92typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci;
93
94struct pp_atomctrl_clock_dividers_vi {
95 uint32_t pll_post_divider;
96 uint32_t real_clock;
97 pp_atomctrl_tcipll_fb_divider ul_fb_div;
98 uint8_t uc_pll_ref_div;
99 uint8_t uc_pll_post_div;
100 uint8_t uc_pll_cntl_flag;
101};
102typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi;
103
104struct pp_atomctrl_clock_dividers_ai {
105 u16 usSclk_fcw_frac;
106 u16 usSclk_fcw_int;
107 u8 ucSclkPostDiv;
108 u8 ucSclkVcoMode;
109 u8 ucSclkPllRange;
110 u8 ucSscEnable;
111 u16 usSsc_fcw1_frac;
112 u16 usSsc_fcw1_int;
113 u16 usReserved;
114 u16 usPcc_fcw_int;
115 u16 usSsc_fcw_slew_frac;
116 u16 usPcc_fcw_slew_frac;
117};
118typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai;
119
120
121union pp_atomctrl_s_mpll_fb_divider {
122 struct {
123 uint32_t cl_kf : 12;
124 uint32_t clk_frac : 12;
125 uint32_t un_used : 8;
126 };
127 uint32_t ul_fb_divider;
128};
129typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider;
130
131enum pp_atomctrl_spread_spectrum_mode {
132 pp_atomctrl_spread_spectrum_mode_down = 0,
133 pp_atomctrl_spread_spectrum_mode_center
134};
135typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode;
136
137struct pp_atomctrl_memory_clock_param {
138 pp_atomctrl_s_mpll_fb_divider mpll_fb_divider;
139 uint32_t mpll_post_divider;
140 uint32_t bw_ctrl;
141 uint32_t dll_speed;
142 uint32_t vco_mode;
143 uint32_t yclk_sel;
144 uint32_t qdr;
145 uint32_t half_rate;
146};
147typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param;
148
149struct pp_atomctrl_internal_ss_info {
150 uint32_t speed_spectrum_percentage;
151 uint32_t speed_spectrum_rate;
152 pp_atomctrl_spread_spectrum_mode speed_spectrum_mode;
153};
154typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info;
155
156#ifndef NUMBER_OF_M3ARB_PARAMS
157#define NUMBER_OF_M3ARB_PARAMS 3
158#endif
159
160#ifndef NUMBER_OF_M3ARB_PARAM_SETS
161#define NUMBER_OF_M3ARB_PARAM_SETS 10
162#endif
163
164struct pp_atomctrl_kong_system_info {
165 uint32_t ul_bootup_uma_clock;
166 uint16_t us_max_nb_voltage;
167 uint16_t us_min_nb_voltage;
168 uint16_t us_bootup_nb_voltage;
169 uint8_t uc_htc_tmp_lmt;
170 uint8_t uc_tj_offset;
171
172 uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];
173};
174typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info;
175
176struct pp_atomctrl_memory_info {
177 uint8_t memory_vendor;
178 uint8_t memory_type;
179};
180typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info;
181
182#define MAX_AC_TIMING_ENTRIES 16
183
184struct pp_atomctrl_memory_clock_range_table {
185 uint8_t num_entries;
186 uint8_t rsv[3];
187
188 uint32_t mclk[MAX_AC_TIMING_ENTRIES];
189};
190typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table;
191
192struct pp_atomctrl_voltage_table_entry {
193 uint16_t value;
194 uint32_t smio_low;
195};
196
197typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry;
198
199struct pp_atomctrl_voltage_table {
200 uint32_t count;
201 uint32_t mask_low;
202 uint32_t phase_delay;
203 pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES];
204};
205
206typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table;
207
208#define VBIOS_MC_REGISTER_ARRAY_SIZE 32
209#define VBIOS_MAX_AC_TIMING_ENTRIES 20
210
211struct pp_atomctrl_mc_reg_entry {
212 uint32_t mclk_max;
213 uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
214};
215typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry;
216
217struct pp_atomctrl_mc_register_address {
218 uint16_t s1;
219 uint8_t uc_pre_reg_data;
220};
221
222typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address;
223
224#define MAX_SCLK_RANGE 8
225
226struct pp_atom_ctrl_sclk_range_table_entry{
227 uint8_t ucVco_setting;
228 uint8_t ucPostdiv;
229 uint16_t usFcw_pcc;
230 uint16_t usFcw_trans_upper;
231 uint16_t usRcw_trans_lower;
232};
233
234
235struct pp_atom_ctrl_sclk_range_table{
236 struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE];
237};
238
239struct pp_atomctrl_mc_reg_table {
240 uint8_t last;
241 uint8_t num_entries;
242 pp_atomctrl_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
243 pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
244};
245typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table;
246
247struct pp_atomctrl_gpio_pin_assignment {
248 uint16_t us_gpio_pin_aindex;
249 uint8_t uc_gpio_pin_bit_shift;
250};
251typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment;
252
253struct pp_atom_ctrl__avfs_parameters {
254 uint32_t ulAVFS_meanNsigma_Acontant0;
255 uint32_t ulAVFS_meanNsigma_Acontant1;
256 uint32_t ulAVFS_meanNsigma_Acontant2;
257 uint16_t usAVFS_meanNsigma_DC_tol_sigma;
258 uint16_t usAVFS_meanNsigma_Platform_mean;
259 uint16_t usAVFS_meanNsigma_Platform_sigma;
260 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0;
261 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1;
262 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2;
263 uint32_t ulGB_VDROOP_TABLE_CKSON_a0;
264 uint32_t ulGB_VDROOP_TABLE_CKSON_a1;
265 uint32_t ulGB_VDROOP_TABLE_CKSON_a2;
266 uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1;
267 uint16_t usAVFSGB_FUSE_TABLE_CKSOFF_m2;
268 uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b;
269 uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1;
270 uint16_t usAVFSGB_FUSE_TABLE_CKSON_m2;
271 uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b;
272 uint16_t usMaxVoltage_0_25mv;
273 uint8_t ucEnableGB_VDROOP_TABLE_CKSOFF;
274 uint8_t ucEnableGB_VDROOP_TABLE_CKSON;
275 uint8_t ucEnableGB_FUSE_TABLE_CKSOFF;
276 uint8_t ucEnableGB_FUSE_TABLE_CKSON;
277 uint16_t usPSM_Age_ComFactor;
278 uint8_t ucEnableApplyAVFS_CKS_OFF_Voltage;
279 uint8_t ucReserved;
280};
281
282extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
283extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
284extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage);
285extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
286extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
287extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
288extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
289extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
290extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
291extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
292extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
293extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
294extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
295extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
296extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
297 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);
298extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
299 uint32_t clock_value,
300 pp_atomctrl_clock_dividers_kong *dividers);
301extern int atomctrl_read_efuse(void *device, uint16_t start_index,
302 uint16_t end_index, uint32_t mask, uint32_t *efuse);
303extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
304 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
305extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
306extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
307 uint8_t level);
308extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
309 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);
310extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
311
312extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
313
314extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
315 uint8_t *svd_gpio_id, uint8_t *svc_gpio_id,
316 uint16_t *load_line);
317
318extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
319 uint16_t *vddc, uint16_t *vddci,
320 uint16_t virtual_voltage_id,
321 uint16_t efuse_voltage_id);
322extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id);
323#endif
324
325
